soc/codecs/max98927.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * max98927.h  --  MAX98927 ALSA Soc Audio driver
0004  *
0005  * Copyright (C) 2016-2017 Maxim Integrated Products
0006  * Author: Ryan Lee <ryans.lee@maximintegrated.com>
0007  */
0008 #ifndef _MAX98927_H
0009 #define _MAX98927_H
0010
0011 /* Register Values */
0012 #define MAX98927_R0001_INT_RAW1 0x0001
0013 #define MAX98927_R0002_INT_RAW2 0x0002
0014 #define MAX98927_R0003_INT_RAW3 0x0003
0015 #define MAX98927_R0004_INT_STATE1 0x0004
0016 #define MAX98927_R0005_INT_STATE2 0x0005
0017 #define MAX98927_R0006_INT_STATE3 0x0006
0018 #define MAX98927_R0007_INT_FLAG1 0x0007
0019 #define MAX98927_R0008_INT_FLAG2 0x0008
0020 #define MAX98927_R0009_INT_FLAG3 0x0009
0021 #define MAX98927_R000A_INT_EN1 0x000A
0022 #define MAX98927_R000B_INT_EN2 0x000B
0023 #define MAX98927_R000C_INT_EN3 0x000C
0024 #define MAX98927_R000D_INT_FLAG_CLR1    0x000D
0025 #define MAX98927_R000E_INT_FLAG_CLR2    0x000E
0026 #define MAX98927_R000F_INT_FLAG_CLR3    0x000F
0027 #define MAX98927_R0010_IRQ_CTRL 0x0010
0028 #define MAX98927_R0011_CLK_MON 0x0011
0029 #define MAX98927_R0012_WDOG_CTRL 0x0012
0030 #define MAX98927_R0013_WDOG_RST 0x0013
0031 #define MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH 0x0014
0032 #define MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH 0x0015
0033 #define MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS 0x0016
0034 #define MAX98927_R0017_PIN_CFG 0x0017
0035 #define MAX98927_R0018_PCM_RX_EN_A 0x0018
0036 #define MAX98927_R0019_PCM_RX_EN_B 0x0019
0037 #define MAX98927_R001A_PCM_TX_EN_A 0x001A
0038 #define MAX98927_R001B_PCM_TX_EN_B 0x001B
0039 #define MAX98927_R001C_PCM_TX_HIZ_CTRL_A 0x001C
0040 #define MAX98927_R001D_PCM_TX_HIZ_CTRL_B 0x001D
0041 #define MAX98927_R001E_PCM_TX_CH_SRC_A 0x001E
0042 #define MAX98927_R001F_PCM_TX_CH_SRC_B 0x001F
0043 #define MAX98927_R0020_PCM_MODE_CFG 0x0020
0044 #define MAX98927_R0021_PCM_MASTER_MODE 0x0021
0045 #define MAX98927_R0022_PCM_CLK_SETUP 0x0022
0046 #define MAX98927_R0023_PCM_SR_SETUP1 0x0023
0047 #define MAX98927_R0024_PCM_SR_SETUP2    0x0024
0048 #define MAX98927_R0025_PCM_TO_SPK_MONOMIX_A 0x0025
0049 #define MAX98927_R0026_PCM_TO_SPK_MONOMIX_B 0x0026
0050 #define MAX98927_R0027_ICC_RX_EN_A 0x0027
0051 #define MAX98927_R0028_ICC_RX_EN_B 0x0028
0052 #define MAX98927_R002B_ICC_TX_EN_A 0x002B
0053 #define MAX98927_R002C_ICC_TX_EN_B 0x002C
0054 #define MAX98927_R002E_ICC_HIZ_MANUAL_MODE 0x002E
0055 #define MAX98927_R002F_ICC_TX_HIZ_EN_A 0x002F
0056 #define MAX98927_R0030_ICC_TX_HIZ_EN_B 0x0030
0057 #define MAX98927_R0031_ICC_LNK_EN 0x0031
0058 #define MAX98927_R0032_PDM_TX_EN 0x0032
0059 #define MAX98927_R0033_PDM_TX_HIZ_CTRL 0x0033
0060 #define MAX98927_R0034_PDM_TX_CTRL 0x0034
0061 #define MAX98927_R0035_PDM_RX_CTRL 0x0035
0062 #define MAX98927_R0036_AMP_VOL_CTRL 0x0036
0063 #define MAX98927_R0037_AMP_DSP_CFG 0x0037
0064 #define MAX98927_R0038_TONE_GEN_DC_CFG 0x0038
0065 #define MAX98927_R0039_DRE_CTRL 0x0039
0066 #define MAX98927_R003A_AMP_EN 0x003A
0067 #define MAX98927_R003B_SPK_SRC_SEL 0x003B
0068 #define MAX98927_R003C_SPK_GAIN 0x003C
0069 #define MAX98927_R003D_SSM_CFG 0x003D
0070 #define MAX98927_R003E_MEAS_EN 0x003E
0071 #define MAX98927_R003F_MEAS_DSP_CFG 0x003F
0072 #define MAX98927_R0040_BOOST_CTRL0 0x0040
0073 #define MAX98927_R0041_BOOST_CTRL3 0x0041
0074 #define MAX98927_R0042_BOOST_CTRL1 0x0042
0075 #define MAX98927_R0043_MEAS_ADC_CFG 0x0043
0076 #define MAX98927_R0044_MEAS_ADC_BASE_MSB 0x0044
0077 #define MAX98927_R0045_MEAS_ADC_BASE_LSB 0x0045
0078 #define MAX98927_R0046_ADC_CH0_DIVIDE 0x0046
0079 #define MAX98927_R0047_ADC_CH1_DIVIDE 0x0047
0080 #define MAX98927_R0048_ADC_CH2_DIVIDE 0x0048
0081 #define MAX98927_R0049_ADC_CH0_FILT_CFG 0x0049
0082 #define MAX98927_R004A_ADC_CH1_FILT_CFG 0x004A
0083 #define MAX98927_R004B_ADC_CH2_FILT_CFG 0x004B
0084 #define MAX98927_R004C_MEAS_ADC_CH0_READ 0x004C
0085 #define MAX98927_R004D_MEAS_ADC_CH1_READ 0x004D
0086 #define MAX98927_R004E_MEAS_ADC_CH2_READ 0x004E
0087 #define MAX98927_R0051_BROWNOUT_STATUS 0x0051
0088 #define MAX98927_R0052_BROWNOUT_EN 0x0052
0089 #define MAX98927_R0053_BROWNOUT_INFINITE_HOLD 0x0053
0090 #define MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR 0x0054
0091 #define MAX98927_R0055_BROWNOUT_LVL_HOLD 0x0055
0092 #define MAX98927_R005A_BROWNOUT_LVL1_THRESH 0x005A
0093 #define MAX98927_R005B_BROWNOUT_LVL2_THRESH 0x005B
0094 #define MAX98927_R005C_BROWNOUT_LVL3_THRESH 0x005C
0095 #define MAX98927_R005D_BROWNOUT_LVL4_THRESH 0x005D
0096 #define MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS 0x005E
0097 #define MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL 0x005F
0098 #define MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL 0x0060
0099 #define MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE 0x0061
0100 #define MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 0x0072
0101 #define MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1 0x0073
0102 #define MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2 0x0074
0103 #define MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3 0x0075
0104 #define MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT 0x0076
0105 #define MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1 0x0077
0106 #define MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2 0x0078
0107 #define MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3 0x0079
0108 #define MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT 0x007A
0109 #define MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1 0x007B
0110 #define MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2 0x007C
0111 #define MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3 0x007D
0112 #define MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT 0x007E
0113 #define MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1 0x007F
0114 #define MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2 0x0080
0115 #define MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3 0x0081
0116 #define MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM 0x0082
0117 #define MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY 0x0083
0118 #define MAX98927_R0084_ENV_TRACK_REL_RATE 0x0084
0119 #define MAX98927_R0085_ENV_TRACK_HOLD_RATE 0x0085
0120 #define MAX98927_R0086_ENV_TRACK_CTRL 0x0086
0121 #define MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ 0x0087
0122 #define MAX98927_R00FF_GLOBAL_SHDN 0x00FF
0123 #define MAX98927_R0100_SOFT_RESET 0x0100
0124 #define MAX98927_R01FF_REV_ID 0x01FF
0125
0126 /* MAX98927_R0018_PCM_RX_EN_A */
0127 #define MAX98927_PCM_RX_CH0_EN (0x1 << 0)
0128 #define MAX98927_PCM_RX_CH1_EN (0x1 << 1)
0129 #define MAX98927_PCM_RX_CH2_EN (0x1 << 2)
0130 #define MAX98927_PCM_RX_CH3_EN (0x1 << 3)
0131 #define MAX98927_PCM_RX_CH4_EN (0x1 << 4)
0132 #define MAX98927_PCM_RX_CH5_EN (0x1 << 5)
0133 #define MAX98927_PCM_RX_CH6_EN (0x1 << 6)
0134 #define MAX98927_PCM_RX_CH7_EN (0x1 << 7)
0135
0136 /* MAX98927_R001A_PCM_TX_EN_A */
0137 #define MAX98927_PCM_TX_CH0_EN (0x1 << 0)
0138 #define MAX98927_PCM_TX_CH1_EN (0x1 << 1)
0139 #define MAX98927_PCM_TX_CH2_EN (0x1 << 2)
0140 #define MAX98927_PCM_TX_CH3_EN (0x1 << 3)
0141 #define MAX98927_PCM_TX_CH4_EN (0x1 << 4)
0142 #define MAX98927_PCM_TX_CH5_EN (0x1 << 5)
0143 #define MAX98927_PCM_TX_CH6_EN (0x1 << 6)
0144 #define MAX98927_PCM_TX_CH7_EN (0x1 << 7)
0145
0146 /* MAX98927_R001E_PCM_TX_CH_SRC_A */
0147 #define MAX98927_PCM_TX_CH_SRC_A_V_SHIFT (0)
0148 #define MAX98927_PCM_TX_CH_SRC_A_I_SHIFT (4)
0149
0150 /* MAX98927_R001F_PCM_TX_CH_SRC_B */
0151 #define MAX98927_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 5)
0152
0153 /* MAX98927_R0020_PCM_MODE_CFG */
0154 #define MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 2)
0155 #define MAX98927_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
0156 #define MAX98927_PCM_MODE_CFG_FORMAT_SHIFT (3)
0157 #define MAX98927_PCM_FORMAT_I2S (0x0 << 0)
0158 #define MAX98927_PCM_FORMAT_LJ (0x1 << 0)
0159 #define MAX98927_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
0160 #define MAX98927_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
0161 #define MAX98927_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
0162 #define MAX98927_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
0163 #define MAX98927_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
0164 #define MAX98927_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
0165 #define MAX98927_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
0166
0167 /* MAX98927_R0021_PCM_MASTER_MODE */
0168 #define MAX98927_PCM_MASTER_MODE_MASK (0x3 << 0)
0169 #define MAX98927_PCM_MASTER_MODE_SLAVE (0x0 << 0)
0170 #define MAX98927_PCM_MASTER_MODE_MASTER (0x3 << 0)
0171
0172 #define MAX98927_PCM_MASTER_MODE_MCLK_MASK (0xF << 2)
0173 #define MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT (2)
0174
0175 /* MAX98927_R0022_PCM_CLK_SETUP */
0176 #define MAX98927_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
0177
0178 /* MAX98927_R0023_PCM_SR_SETUP1 */
0179 #define MAX98927_PCM_SR_SET1_SR_MASK (0xF << 0)
0180
0181 #define MAX98927_PCM_SR_SET1_SR_8000 (0x0 << 0)
0182 #define MAX98927_PCM_SR_SET1_SR_11025 (0x1 << 0)
0183 #define MAX98927_PCM_SR_SET1_SR_12000 (0x2 << 0)
0184 #define MAX98927_PCM_SR_SET1_SR_16000 (0x3 << 0)
0185 #define MAX98927_PCM_SR_SET1_SR_22050 (0x4 << 0)
0186 #define MAX98927_PCM_SR_SET1_SR_24000 (0x5 << 0)
0187 #define MAX98927_PCM_SR_SET1_SR_32000 (0x6 << 0)
0188 #define MAX98927_PCM_SR_SET1_SR_44100 (0x7 << 0)
0189 #define MAX98927_PCM_SR_SET1_SR_48000 (0x8 << 0)
0190
0191 /* MAX98927_R0024_PCM_SR_SETUP2 */
0192 #define MAX98927_PCM_SR_SET2_SR_MASK (0xF << 4)
0193 #define MAX98927_PCM_SR_SET2_SR_SHIFT (4)
0194 #define MAX98927_PCM_SR_SET2_IVADC_SR_MASK (0xf << 0)
0195
0196 /* MAX98927_R0025_PCM_TO_SPK_MONOMIX_A */
0197 #define MAX98927_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
0198 #define MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
0199
0200 /* MAX98927_R0035_PDM_RX_CTRL */
0201 #define MAX98927_PDM_RX_EN_MASK (0x1 << 0)
0202
0203 /* MAX98927_R0036_AMP_VOL_CTRL */
0204 #define MAX98927_AMP_VOL_SEL (0x1 << 7)
0205 #define MAX98927_AMP_VOL_SEL_WIDTH (1)
0206 #define MAX98927_AMP_VOL_SEL_SHIFT (7)
0207 #define MAX98927_AMP_VOL_MASK (0x7f << 0)
0208 #define MAX98927_AMP_VOL_WIDTH (7)
0209 #define MAX98927_AMP_VOL_SHIFT (0)
0210
0211 /* MAX98927_R0037_AMP_DSP_CFG */
0212 #define MAX98927_AMP_DSP_CFG_DCBLK_EN (0x1 << 0)
0213 #define MAX98927_AMP_DSP_CFG_DITH_EN (0x1 << 1)
0214 #define MAX98927_AMP_DSP_CFG_RMP_BYPASS (0x1 << 4)
0215 #define MAX98927_AMP_DSP_CFG_DAC_INV (0x1 << 5)
0216 #define MAX98927_AMP_DSP_CFG_RMP_SHIFT (4)
0217
0218 /* MAX98927_R0039_DRE_CTRL */
0219 #define MAX98927_DRE_CTRL_DRE_EN    (0x1 << 0)
0220 #define MAX98927_DRE_EN_SHIFT 0x1
0221
0222 /* MAX98927_R003A_AMP_EN */
0223 #define MAX98927_AMP_EN_MASK (0x1 << 0)
0224
0225 /* MAX98927_R003B_SPK_SRC_SEL */
0226 #define MAX98927_SPK_SRC_MASK (0x3 << 0)
0227
0228 /* MAX98927_R003C_SPK_GAIN */
0229 #define MAX98927_SPK_PCM_GAIN_MASK (0x7 << 0)
0230 #define MAX98927_SPK_PDM_GAIN_MASK (0x7 << 4)
0231 #define MAX98927_SPK_GAIN_WIDTH (3)
0232
0233 /* MAX98927_R003E_MEAS_EN */
0234 #define MAX98927_MEAS_V_EN (0x1 << 0)
0235 #define MAX98927_MEAS_I_EN (0x1 << 1)
0236
0237 /* MAX98927_R0040_BOOST_CTRL0 */
0238 #define MAX98927_BOOST_CTRL0_VOUT_MASK (0x1f << 0)
0239 #define MAX98927_BOOST_CTRL0_PVDD_MASK (0x1 << 7)
0240 #define MAX98927_BOOST_CTRL0_PVDD_EN_SHIFT (7)
0241
0242 /* MAX98927_R0052_BROWNOUT_EN */
0243 #define MAX98927_BROWNOUT_BDE_EN (0x1 << 0)
0244 #define MAX98927_BROWNOUT_AMP_EN (0x1 << 1)
0245 #define MAX98927_BROWNOUT_DSP_EN (0x1 << 2)
0246 #define MAX98927_BROWNOUT_DSP_SHIFT (2)
0247
0248 /* MAX98927_R0100_SOFT_RESET */
0249 #define MAX98927_SOFT_RESET (0x1 << 0)
0250
0251 /* MAX98927_R00FF_GLOBAL_SHDN */
0252 #define MAX98927_GLOBAL_EN_MASK (0x1 << 0)
0253
0254 struct max98927_priv {
0255     struct regmap *regmap;
0256     struct snd_soc_component *component;
0257     struct max98927_pdata *pdata;
0258     struct gpio_desc *reset_gpio;
0259     unsigned int spk_gain;
0260     unsigned int sysclk;
0261     unsigned int v_l_slot;
0262     unsigned int i_l_slot;
0263     bool interleave_mode;
0264     unsigned int ch_size;
0265     unsigned int rate;
0266     unsigned int iface;
0267     unsigned int provider;
0268     unsigned int digital_gain;
0269     bool tdm_mode;
0270 };
0271 #endif