Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * max98925.c -- ALSA SoC Stereo MAX98925 driver
0004  * Copyright 2013-15 Maxim Integrated Products
0005  */
0006 #include <linux/delay.h>
0007 #include <linux/i2c.h>
0008 #include <linux/module.h>
0009 #include <linux/regmap.h>
0010 #include <linux/slab.h>
0011 #include <linux/cdev.h>
0012 #include <sound/pcm.h>
0013 #include <sound/pcm_params.h>
0014 #include <sound/soc.h>
0015 #include <sound/tlv.h>
0016 #include "max98925.h"
0017 
0018 static const char *const dai_text[] = {
0019     "Left", "Right", "LeftRight", "LeftRightDiv2",
0020 };
0021 
0022 static const char * const max98925_boost_voltage_text[] = {
0023     "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
0024     "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
0025 };
0026 
0027 static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
0028     MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
0029     max98925_boost_voltage_text);
0030 
0031 static const char *const hpf_text[] = {
0032     "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
0033 };
0034 
0035 static const struct reg_default max98925_reg[] = {
0036     { 0x0B, 0x00 }, /* IRQ Enable0 */
0037     { 0x0C, 0x00 }, /* IRQ Enable1 */
0038     { 0x0D, 0x00 }, /* IRQ Enable2 */
0039     { 0x0E, 0x00 }, /* IRQ Clear0 */
0040     { 0x0F, 0x00 }, /* IRQ Clear1 */
0041     { 0x10, 0x00 }, /* IRQ Clear2 */
0042     { 0x11, 0xC0 }, /* Map0 */
0043     { 0x12, 0x00 }, /* Map1 */
0044     { 0x13, 0x00 }, /* Map2 */
0045     { 0x14, 0xF0 }, /* Map3 */
0046     { 0x15, 0x00 }, /* Map4 */
0047     { 0x16, 0xAB }, /* Map5 */
0048     { 0x17, 0x89 }, /* Map6 */
0049     { 0x18, 0x00 }, /* Map7 */
0050     { 0x19, 0x00 }, /* Map8 */
0051     { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
0052     { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
0053     { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
0054     { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
0055     { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
0056     { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
0057     { 0x20, 0x50 }, /* Format */
0058     { 0x21, 0x00 }, /* TDM Slot Select */
0059     { 0x22, 0x00 }, /* DOUT Configuration VMON */
0060     { 0x23, 0x00 }, /* DOUT Configuration IMON */
0061     { 0x24, 0x00 }, /* DOUT Configuration VBAT */
0062     { 0x25, 0x00 }, /* DOUT Configuration VBST */
0063     { 0x26, 0x00 }, /* DOUT Configuration FLAG */
0064     { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
0065     { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
0066     { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
0067     { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
0068     { 0x2B, 0x02 }, /* DOUT Drive Strength */
0069     { 0x2C, 0x90 }, /* Filters */
0070     { 0x2D, 0x00 }, /* Gain */
0071     { 0x2E, 0x02 }, /* Gain Ramping */
0072     { 0x2F, 0x00 }, /* Speaker Amplifier */
0073     { 0x30, 0x0A }, /* Threshold */
0074     { 0x31, 0x00 }, /* ALC Attack */
0075     { 0x32, 0x80 }, /* ALC Atten and Release */
0076     { 0x33, 0x00 }, /* ALC Infinite Hold Release */
0077     { 0x34, 0x92 }, /* ALC Configuration */
0078     { 0x35, 0x01 }, /* Boost Converter */
0079     { 0x36, 0x00 }, /* Block Enable */
0080     { 0x37, 0x00 }, /* Configuration */
0081     { 0x38, 0x00 }, /* Global Enable */
0082     { 0x3A, 0x00 }, /* Boost Limiter */
0083 };
0084 
0085 static const struct soc_enum max98925_dai_enum =
0086     SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
0087 
0088 static const struct soc_enum max98925_hpf_enum =
0089     SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
0090 
0091 static const struct snd_kcontrol_new max98925_hpf_sel_mux =
0092     SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
0093 
0094 static const struct snd_kcontrol_new max98925_dai_sel_mux =
0095     SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
0096 
0097 static int max98925_dac_event(struct snd_soc_dapm_widget *w,
0098         struct snd_kcontrol *kcontrol, int event)
0099 {
0100     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0101     struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
0102 
0103     switch (event) {
0104     case SND_SOC_DAPM_PRE_PMU:
0105         regmap_update_bits(max98925->regmap,
0106             MAX98925_BLOCK_ENABLE,
0107             M98925_BST_EN_MASK |
0108             M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
0109             M98925_BST_EN_MASK |
0110             M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
0111         break;
0112     case SND_SOC_DAPM_POST_PMD:
0113         regmap_update_bits(max98925->regmap,
0114             MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
0115             M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
0116         break;
0117     default:
0118         return 0;
0119     }
0120     return 0;
0121 }
0122 
0123 static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
0124     SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
0125     SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
0126                 &max98925_dai_sel_mux),
0127     SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
0128                 &max98925_hpf_sel_mux),
0129     SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
0130             M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
0131             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0132     SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
0133             M98925_EN_SHIFT, 0, NULL, 0),
0134     SND_SOC_DAPM_OUTPUT("BE_OUT"),
0135 };
0136 
0137 static const struct snd_soc_dapm_route max98925_audio_map[] = {
0138     {"DAI IN MUX", "Left", "DAI_OUT"},
0139     {"DAI IN MUX", "Right", "DAI_OUT"},
0140     {"DAI IN MUX", "LeftRight", "DAI_OUT"},
0141     {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
0142     {"Rc Filter MUX", "Disable", "DAI IN MUX"},
0143     {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
0144     {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
0145     {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
0146     {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
0147     {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
0148     {"Amp Enable", NULL, "Rc Filter MUX"},
0149     {"BE_OUT", NULL, "Amp Enable"},
0150     {"BE_OUT", NULL, "Global Enable"},
0151 };
0152 
0153 static bool max98925_volatile_register(struct device *dev, unsigned int reg)
0154 {
0155     switch (reg) {
0156     case MAX98925_VBAT_DATA:
0157     case MAX98925_VBST_DATA:
0158     case MAX98925_LIVE_STATUS0:
0159     case MAX98925_LIVE_STATUS1:
0160     case MAX98925_LIVE_STATUS2:
0161     case MAX98925_STATE0:
0162     case MAX98925_STATE1:
0163     case MAX98925_STATE2:
0164     case MAX98925_FLAG0:
0165     case MAX98925_FLAG1:
0166     case MAX98925_FLAG2:
0167     case MAX98925_REV_VERSION:
0168         return true;
0169     default:
0170         return false;
0171     }
0172 }
0173 
0174 static bool max98925_readable_register(struct device *dev, unsigned int reg)
0175 {
0176     switch (reg) {
0177     case MAX98925_IRQ_CLEAR0:
0178     case MAX98925_IRQ_CLEAR1:
0179     case MAX98925_IRQ_CLEAR2:
0180     case MAX98925_ALC_HOLD_RLS:
0181         return false;
0182     default:
0183         return true;
0184     }
0185 }
0186 
0187 static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
0188 
0189 static const struct snd_kcontrol_new max98925_snd_controls[] = {
0190     SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
0191         M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
0192         max98925_spk_tlv),
0193     SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
0194                 M98925_SPK_RMP_EN_SHIFT, 1, 0),
0195     SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
0196                 M98925_SPK_ZCD_EN_SHIFT, 1, 0),
0197     SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
0198                 M98925_ALC_EN_SHIFT, 1, 0),
0199     SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
0200                 (1<<M98925_ALC_TH_WIDTH)-1, 0),
0201     SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
0202 };
0203 
0204 /* codec sample rate and n/m dividers parameter table */
0205 static const struct {
0206     int rate;
0207     int  sr;
0208     int divisors[3][2];
0209 } rate_table[] = {
0210     {
0211         .rate = 8000,
0212         .sr = 0,
0213         .divisors = { {1, 375}, {5, 1764}, {1, 384} }
0214     },
0215     {
0216         .rate = 11025,
0217         .sr = 1,
0218         .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
0219     },
0220     {
0221         .rate = 12000,
0222         .sr = 2,
0223         .divisors = { {1, 250}, {5, 1176}, {1, 256} }
0224     },
0225     {
0226         .rate = 16000,
0227         .sr = 3,
0228         .divisors = { {2, 375}, {5, 882}, {1, 192} }
0229     },
0230     {
0231         .rate = 22050,
0232         .sr = 4,
0233         .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
0234     },
0235     {
0236         .rate = 24000,
0237         .sr = 5,
0238         .divisors = { {1, 125}, {5, 588}, {1, 128} }
0239     },
0240     {
0241         .rate = 32000,
0242         .sr = 6,
0243         .divisors = { {4, 375}, {5, 441}, {1, 96} }
0244     },
0245     {
0246         .rate = 44100,
0247         .sr = 7,
0248         .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
0249     },
0250     {
0251         .rate = 48000,
0252         .sr = 8,
0253         .divisors = { {2, 125}, {5, 294}, {1, 64} }
0254     },
0255 };
0256 
0257 static inline int max98925_rate_value(struct snd_soc_component *component,
0258         int rate, int clock, int *value, int *n, int *m)
0259 {
0260     int ret = -EINVAL;
0261     int i;
0262 
0263     for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
0264         if (rate_table[i].rate >= rate) {
0265             *value = rate_table[i].sr;
0266             *n = rate_table[i].divisors[clock][0];
0267             *m = rate_table[i].divisors[clock][1];
0268             ret = 0;
0269             break;
0270         }
0271     }
0272     return ret;
0273 }
0274 
0275 static void max98925_set_sense_data(struct max98925_priv *max98925)
0276 {
0277     /* set VMON slots */
0278     regmap_update_bits(max98925->regmap,
0279         MAX98925_DOUT_CFG_VMON,
0280         M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
0281     regmap_update_bits(max98925->regmap,
0282         MAX98925_DOUT_CFG_VMON,
0283         M98925_DAI_VMON_SLOT_MASK,
0284         max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
0285     /* set IMON slots */
0286     regmap_update_bits(max98925->regmap,
0287         MAX98925_DOUT_CFG_IMON,
0288         M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
0289     regmap_update_bits(max98925->regmap,
0290         MAX98925_DOUT_CFG_IMON,
0291         M98925_DAI_IMON_SLOT_MASK,
0292         max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
0293 }
0294 
0295 static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
0296                  unsigned int fmt)
0297 {
0298     struct snd_soc_component *component = codec_dai->component;
0299     struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
0300     unsigned int invert = 0;
0301 
0302     dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
0303     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0304     case SND_SOC_DAIFMT_CBC_CFC:
0305         regmap_update_bits(max98925->regmap,
0306             MAX98925_DAI_CLK_MODE2,
0307             M98925_DAI_MAS_MASK, 0);
0308         max98925_set_sense_data(max98925);
0309         break;
0310     case SND_SOC_DAIFMT_CBP_CFP:
0311         /*
0312          * set left channel DAI to provider mode,
0313          * right channel always consumer
0314          */
0315         regmap_update_bits(max98925->regmap,
0316             MAX98925_DAI_CLK_MODE2,
0317             M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
0318         break;
0319     default:
0320         dev_err(component->dev, "DAI clock mode unsupported");
0321         return -EINVAL;
0322     }
0323 
0324     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0325     case SND_SOC_DAIFMT_NB_NF:
0326         break;
0327     case SND_SOC_DAIFMT_NB_IF:
0328         invert = M98925_DAI_WCI_MASK;
0329         break;
0330     case SND_SOC_DAIFMT_IB_NF:
0331         invert = M98925_DAI_BCI_MASK;
0332         break;
0333     case SND_SOC_DAIFMT_IB_IF:
0334         invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
0335         break;
0336     default:
0337         dev_err(component->dev, "DAI invert mode unsupported");
0338         return -EINVAL;
0339     }
0340 
0341     regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
0342             M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
0343     return 0;
0344 }
0345 
0346 static int max98925_set_clock(struct max98925_priv *max98925,
0347         struct snd_pcm_hw_params *params)
0348 {
0349     unsigned int dai_sr = 0, clock, mdll, n, m;
0350     struct snd_soc_component *component = max98925->component;
0351     int rate = params_rate(params);
0352     /* BCLK/LRCLK ratio calculation */
0353     int blr_clk_ratio = params_channels(params) * max98925->ch_size;
0354 
0355     switch (blr_clk_ratio) {
0356     case 32:
0357         regmap_update_bits(max98925->regmap,
0358             MAX98925_DAI_CLK_MODE2,
0359             M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
0360         break;
0361     case 48:
0362         regmap_update_bits(max98925->regmap,
0363             MAX98925_DAI_CLK_MODE2,
0364             M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
0365         break;
0366     case 64:
0367         regmap_update_bits(max98925->regmap,
0368             MAX98925_DAI_CLK_MODE2,
0369             M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
0370         break;
0371     default:
0372         return -EINVAL;
0373     }
0374 
0375     switch (max98925->sysclk) {
0376     case 6000000:
0377         clock = 0;
0378         mdll  = M98925_MDLL_MULT_MCLKx16;
0379         break;
0380     case 11289600:
0381         clock = 1;
0382         mdll  = M98925_MDLL_MULT_MCLKx8;
0383         break;
0384     case 12000000:
0385         clock = 0;
0386         mdll  = M98925_MDLL_MULT_MCLKx8;
0387         break;
0388     case 12288000:
0389         clock = 2;
0390         mdll  = M98925_MDLL_MULT_MCLKx8;
0391         break;
0392     default:
0393         dev_info(max98925->component->dev, "unsupported sysclk %d\n",
0394                     max98925->sysclk);
0395         return -EINVAL;
0396     }
0397 
0398     if (max98925_rate_value(component, rate, clock, &dai_sr, &n, &m))
0399         return -EINVAL;
0400 
0401     /* set DAI_SR to correct LRCLK frequency */
0402     regmap_update_bits(max98925->regmap,
0403             MAX98925_DAI_CLK_MODE2,
0404             M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
0405     /* set DAI m divider */
0406     regmap_write(max98925->regmap,
0407         MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
0408     regmap_write(max98925->regmap,
0409         MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
0410     /* set DAI n divider */
0411     regmap_write(max98925->regmap,
0412         MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
0413     regmap_write(max98925->regmap,
0414         MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
0415     /* set MDLL */
0416     regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
0417             M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
0418     return 0;
0419 }
0420 
0421 static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
0422                    struct snd_pcm_hw_params *params,
0423                    struct snd_soc_dai *dai)
0424 {
0425     struct snd_soc_component *component = dai->component;
0426     struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
0427 
0428     switch (params_width(params)) {
0429     case 16:
0430         regmap_update_bits(max98925->regmap,
0431                 MAX98925_FORMAT,
0432                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
0433         max98925->ch_size = 16;
0434         break;
0435     case 24:
0436         regmap_update_bits(max98925->regmap,
0437                 MAX98925_FORMAT,
0438                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
0439         max98925->ch_size = 24;
0440         break;
0441     case 32:
0442         regmap_update_bits(max98925->regmap,
0443                 MAX98925_FORMAT,
0444                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
0445         max98925->ch_size = 32;
0446         break;
0447     default:
0448         pr_err("%s: format unsupported %d",
0449                 __func__, params_format(params));
0450         return -EINVAL;
0451     }
0452     dev_dbg(component->dev, "%s: format supported %d",
0453                 __func__, params_format(params));
0454     return max98925_set_clock(max98925, params);
0455 }
0456 
0457 static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
0458                    int clk_id, unsigned int freq, int dir)
0459 {
0460     struct snd_soc_component *component = dai->component;
0461     struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
0462 
0463     switch (clk_id) {
0464     case 0:
0465         /* use MCLK for Left channel, right channel always BCLK */
0466         regmap_update_bits(max98925->regmap,
0467                 MAX98925_DAI_CLK_MODE1,
0468                 M98925_DAI_CLK_SOURCE_MASK, 0);
0469         break;
0470     case 1:
0471         /* configure dai clock source to BCLK instead of MCLK */
0472         regmap_update_bits(max98925->regmap,
0473                 MAX98925_DAI_CLK_MODE1,
0474                 M98925_DAI_CLK_SOURCE_MASK,
0475                 M98925_DAI_CLK_SOURCE_MASK);
0476         break;
0477     default:
0478         return -EINVAL;
0479     }
0480     max98925->sysclk = freq;
0481     return 0;
0482 }
0483 
0484 #define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0485             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0486 
0487 static const struct snd_soc_dai_ops max98925_dai_ops = {
0488     .set_sysclk = max98925_dai_set_sysclk,
0489     .set_fmt = max98925_dai_set_fmt,
0490     .hw_params = max98925_dai_hw_params,
0491 };
0492 
0493 static struct snd_soc_dai_driver max98925_dai[] = {
0494     {
0495         .name = "max98925-aif1",
0496         .playback = {
0497             .stream_name = "HiFi Playback",
0498             .channels_min = 1,
0499             .channels_max = 2,
0500             .rates = SNDRV_PCM_RATE_8000_48000,
0501             .formats = MAX98925_FORMATS,
0502         },
0503         .capture = {
0504             .stream_name = "HiFi Capture",
0505             .channels_min = 1,
0506             .channels_max = 2,
0507             .rates = SNDRV_PCM_RATE_8000_48000,
0508             .formats = MAX98925_FORMATS,
0509         },
0510         .ops = &max98925_dai_ops,
0511     }
0512 };
0513 
0514 static int max98925_probe(struct snd_soc_component *component)
0515 {
0516     struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
0517 
0518     max98925->component = component;
0519     regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
0520     /* It's not the default but we need to set DAI_DLY */
0521     regmap_write(max98925->regmap,
0522             MAX98925_FORMAT, M98925_DAI_DLY_MASK);
0523     regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
0524     regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
0525     regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
0526     regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
0527     regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
0528     regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
0529     regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
0530     regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
0531     /* Disable ALC muting */
0532     regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
0533     return 0;
0534 }
0535 
0536 static const struct snd_soc_component_driver soc_component_dev_max98925 = {
0537     .probe          = max98925_probe,
0538     .controls       = max98925_snd_controls,
0539     .num_controls       = ARRAY_SIZE(max98925_snd_controls),
0540     .dapm_routes        = max98925_audio_map,
0541     .num_dapm_routes    = ARRAY_SIZE(max98925_audio_map),
0542     .dapm_widgets       = max98925_dapm_widgets,
0543     .num_dapm_widgets   = ARRAY_SIZE(max98925_dapm_widgets),
0544     .idle_bias_on       = 1,
0545     .use_pmdown_time    = 1,
0546     .endianness     = 1,
0547 };
0548 
0549 static const struct regmap_config max98925_regmap = {
0550     .reg_bits         = 8,
0551     .val_bits         = 8,
0552     .max_register     = MAX98925_REV_VERSION,
0553     .reg_defaults     = max98925_reg,
0554     .num_reg_defaults = ARRAY_SIZE(max98925_reg),
0555     .volatile_reg     = max98925_volatile_register,
0556     .readable_reg     = max98925_readable_register,
0557     .cache_type       = REGCACHE_RBTREE,
0558 };
0559 
0560 static int max98925_i2c_probe(struct i2c_client *i2c)
0561 {
0562     int ret, reg;
0563     u32 value;
0564     struct max98925_priv *max98925;
0565 
0566     max98925 = devm_kzalloc(&i2c->dev,
0567             sizeof(*max98925), GFP_KERNEL);
0568     if (!max98925)
0569         return -ENOMEM;
0570 
0571     i2c_set_clientdata(i2c, max98925);
0572     max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
0573     if (IS_ERR(max98925->regmap)) {
0574         ret = PTR_ERR(max98925->regmap);
0575         dev_err(&i2c->dev,
0576                 "Failed to allocate regmap: %d\n", ret);
0577         return ret;
0578     }
0579 
0580     if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
0581         if (value > M98925_DAI_VMON_SLOT_1E_1F) {
0582             dev_err(&i2c->dev, "vmon slot number is wrong:\n");
0583             return -EINVAL;
0584         }
0585         max98925->v_slot = value;
0586     }
0587     if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
0588         if (value > M98925_DAI_IMON_SLOT_1E_1F) {
0589             dev_err(&i2c->dev, "imon slot number is wrong:\n");
0590             return -EINVAL;
0591         }
0592         max98925->i_slot = value;
0593     }
0594 
0595     ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, &reg);
0596     if (ret < 0) {
0597         dev_err(&i2c->dev, "Read revision failed\n");
0598         return ret;
0599     }
0600 
0601     if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) {
0602         ret = -ENODEV;
0603         dev_err(&i2c->dev, "Invalid revision (%d 0x%02X)\n",
0604             ret, reg);
0605         return ret;
0606     }
0607 
0608     dev_info(&i2c->dev, "device version 0x%02X\n", reg);
0609 
0610     ret = devm_snd_soc_register_component(&i2c->dev,
0611             &soc_component_dev_max98925,
0612             max98925_dai, ARRAY_SIZE(max98925_dai));
0613     if (ret < 0)
0614         dev_err(&i2c->dev,
0615                 "Failed to register component: %d\n", ret);
0616     return ret;
0617 }
0618 
0619 static const struct i2c_device_id max98925_i2c_id[] = {
0620     { "max98925", 0 },
0621     { }
0622 };
0623 MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
0624 
0625 #ifdef CONFIG_OF
0626 static const struct of_device_id max98925_of_match[] = {
0627     { .compatible = "maxim,max98925", },
0628     { }
0629 };
0630 MODULE_DEVICE_TABLE(of, max98925_of_match);
0631 #endif
0632 
0633 static struct i2c_driver max98925_i2c_driver = {
0634     .driver = {
0635         .name = "max98925",
0636         .of_match_table = of_match_ptr(max98925_of_match),
0637     },
0638     .probe_new  = max98925_i2c_probe,
0639     .id_table = max98925_i2c_id,
0640 };
0641 
0642 module_i2c_driver(max98925_i2c_driver)
0643 
0644 MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
0645 MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
0646 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!