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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Driver for the MAX9860 Mono Audio Voice Codec
0004 //
0005 // https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf
0006 //
0007 // The driver does not support sidetone since the DVST register field is
0008 // backwards with the mute near the maximum level instead of the minimum.
0009 //
0010 // Author: Peter Rosin <peda@axentia.s>
0011 //         Copyright 2016 Axentia Technologies
0012 
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/clk.h>
0016 #include <linux/kernel.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/regmap.h>
0019 #include <linux/i2c.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <sound/soc.h>
0022 #include <sound/soc-dapm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/tlv.h>
0025 
0026 #include "max9860.h"
0027 
0028 struct max9860_priv {
0029     struct regmap *regmap;
0030     struct regulator *dvddio;
0031     struct notifier_block dvddio_nb;
0032     u8 psclk;
0033     unsigned long pclk_rate;
0034     int fmt;
0035 };
0036 
0037 static int max9860_dvddio_event(struct notifier_block *nb,
0038                 unsigned long event, void *data)
0039 {
0040     struct max9860_priv *max9860 = container_of(nb, struct max9860_priv,
0041                             dvddio_nb);
0042     if (event & REGULATOR_EVENT_DISABLE) {
0043         regcache_mark_dirty(max9860->regmap);
0044         regcache_cache_only(max9860->regmap, true);
0045     }
0046 
0047     return 0;
0048 }
0049 
0050 static const struct reg_default max9860_reg_defaults[] = {
0051     { MAX9860_PWRMAN,       0x00 },
0052     { MAX9860_INTEN,        0x00 },
0053     { MAX9860_SYSCLK,       0x00 },
0054     { MAX9860_AUDIOCLKHIGH, 0x00 },
0055     { MAX9860_AUDIOCLKLOW,  0x00 },
0056     { MAX9860_IFC1A,        0x00 },
0057     { MAX9860_IFC1B,        0x00 },
0058     { MAX9860_VOICEFLTR,    0x00 },
0059     { MAX9860_DACATTN,      0x00 },
0060     { MAX9860_ADCLEVEL,     0x00 },
0061     { MAX9860_DACGAIN,      0x00 },
0062     { MAX9860_MICGAIN,      0x00 },
0063     { MAX9860_MICADC,       0x00 },
0064     { MAX9860_NOISEGATE,    0x00 },
0065 };
0066 
0067 static bool max9860_readable(struct device *dev, unsigned int reg)
0068 {
0069     switch (reg) {
0070     case MAX9860_INTRSTATUS ... MAX9860_MICGAIN:
0071     case MAX9860_MICADC ... MAX9860_PWRMAN:
0072     case MAX9860_REVISION:
0073         return true;
0074     }
0075 
0076     return false;
0077 }
0078 
0079 static bool max9860_writeable(struct device *dev, unsigned int reg)
0080 {
0081     switch (reg) {
0082     case MAX9860_INTEN ... MAX9860_MICGAIN:
0083     case MAX9860_MICADC ... MAX9860_PWRMAN:
0084         return true;
0085     }
0086 
0087     return false;
0088 }
0089 
0090 static bool max9860_volatile(struct device *dev, unsigned int reg)
0091 {
0092     switch (reg) {
0093     case MAX9860_INTRSTATUS:
0094     case MAX9860_MICREADBACK:
0095         return true;
0096     }
0097 
0098     return false;
0099 }
0100 
0101 static bool max9860_precious(struct device *dev, unsigned int reg)
0102 {
0103     switch (reg) {
0104     case MAX9860_INTRSTATUS:
0105         return true;
0106     }
0107 
0108     return false;
0109 }
0110 
0111 static const struct regmap_config max9860_regmap = {
0112     .reg_bits = 8,
0113     .val_bits = 8,
0114 
0115     .readable_reg = max9860_readable,
0116     .writeable_reg = max9860_writeable,
0117     .volatile_reg = max9860_volatile,
0118     .precious_reg = max9860_precious,
0119 
0120     .max_register = MAX9860_MAX_REGISTER,
0121     .reg_defaults = max9860_reg_defaults,
0122     .num_reg_defaults = ARRAY_SIZE(max9860_reg_defaults),
0123     .cache_type = REGCACHE_RBTREE,
0124 };
0125 
0126 static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
0127 static const DECLARE_TLV_DB_SCALE(dvg_tlv, 0, 600, 0);
0128 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
0129 static const DECLARE_TLV_DB_RANGE(pam_tlv,
0130     0, MAX9860_PAM_MAX - 1,             TLV_DB_SCALE_ITEM(-2000, 2000, 1),
0131     MAX9860_PAM_MAX, MAX9860_PAM_MAX,   TLV_DB_SCALE_ITEM(3000, 0, 0));
0132 static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
0133 static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
0134 static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
0135 
0136 static const char * const agchld_text[] = {
0137     "AGC Disabled", "50ms", "100ms", "400ms"
0138 };
0139 
0140 static SOC_ENUM_SINGLE_DECL(agchld_enum, MAX9860_MICADC,
0141                 MAX9860_AGCHLD_SHIFT, agchld_text);
0142 
0143 static const char * const agcsrc_text[] = {
0144     "Left ADC", "Left/Right ADC"
0145 };
0146 
0147 static SOC_ENUM_SINGLE_DECL(agcsrc_enum, MAX9860_MICADC,
0148                 MAX9860_AGCSRC_SHIFT, agcsrc_text);
0149 
0150 static const char * const agcatk_text[] = {
0151     "3ms", "12ms", "50ms", "200ms"
0152 };
0153 
0154 static SOC_ENUM_SINGLE_DECL(agcatk_enum, MAX9860_MICADC,
0155                 MAX9860_AGCATK_SHIFT, agcatk_text);
0156 
0157 static const char * const agcrls_text[] = {
0158     "78ms", "156ms", "312ms", "625ms",
0159     "1.25s", "2.5s", "5s", "10s"
0160 };
0161 
0162 static SOC_ENUM_SINGLE_DECL(agcrls_enum, MAX9860_MICADC,
0163                 MAX9860_AGCRLS_SHIFT, agcrls_text);
0164 
0165 static const char * const filter_text[] = {
0166     "Disabled",
0167     "Elliptical HP 217Hz notch (16kHz)",
0168     "Butterworth HP 500Hz (16kHz)",
0169     "Elliptical HP 217Hz notch (8kHz)",
0170     "Butterworth HP 500Hz (8kHz)",
0171     "Butterworth HP 200Hz (48kHz)"
0172 };
0173 
0174 static SOC_ENUM_SINGLE_DECL(avflt_enum, MAX9860_VOICEFLTR,
0175                 MAX9860_AVFLT_SHIFT, filter_text);
0176 
0177 static SOC_ENUM_SINGLE_DECL(dvflt_enum, MAX9860_VOICEFLTR,
0178                 MAX9860_DVFLT_SHIFT, filter_text);
0179 
0180 static const struct snd_kcontrol_new max9860_controls[] = {
0181 SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
0182            MAX9860_DVA_SHIFT, MAX9860_DVA_MUTE, 1, dva_tlv),
0183 SOC_SINGLE_TLV("DAC Gain Volume", MAX9860_DACGAIN,
0184            MAX9860_DVG_SHIFT, MAX9860_DVG_MAX, 0, dvg_tlv),
0185 SOC_DOUBLE_TLV("Line Capture Volume", MAX9860_ADCLEVEL,
0186            MAX9860_ADCLL_SHIFT, MAX9860_ADCRL_SHIFT, MAX9860_ADCxL_MIN, 1,
0187            adc_tlv),
0188 
0189 SOC_ENUM("AGC Hold Time", agchld_enum),
0190 SOC_ENUM("AGC/Noise Gate Source", agcsrc_enum),
0191 SOC_ENUM("AGC Attack Time", agcatk_enum),
0192 SOC_ENUM("AGC Release Time", agcrls_enum),
0193 
0194 SOC_SINGLE_TLV("Noise Gate Threshold Volume", MAX9860_NOISEGATE,
0195            MAX9860_ANTH_SHIFT, MAX9860_ANTH_MAX, 0, anth_tlv),
0196 SOC_SINGLE_TLV("AGC Signal Threshold Volume", MAX9860_NOISEGATE,
0197            MAX9860_AGCTH_SHIFT, MAX9860_AGCTH_MIN, 1, agcth_tlv),
0198 
0199 SOC_SINGLE_TLV("Mic PGA Volume", MAX9860_MICGAIN,
0200            MAX9860_PGAM_SHIFT, MAX9860_PGAM_MIN, 1, pgam_tlv),
0201 SOC_SINGLE_TLV("Mic Preamp Volume", MAX9860_MICGAIN,
0202            MAX9860_PAM_SHIFT, MAX9860_PAM_MAX, 0, pam_tlv),
0203 
0204 SOC_ENUM("ADC Filter", avflt_enum),
0205 SOC_ENUM("DAC Filter", dvflt_enum),
0206 };
0207 
0208 static const struct snd_soc_dapm_widget max9860_dapm_widgets[] = {
0209 SND_SOC_DAPM_INPUT("MICL"),
0210 SND_SOC_DAPM_INPUT("MICR"),
0211 
0212 SND_SOC_DAPM_ADC("ADCL", NULL, MAX9860_PWRMAN, MAX9860_ADCLEN_SHIFT, 0),
0213 SND_SOC_DAPM_ADC("ADCR", NULL, MAX9860_PWRMAN, MAX9860_ADCREN_SHIFT, 0),
0214 
0215 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
0216 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
0217 
0218 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
0219 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
0220 
0221 SND_SOC_DAPM_DAC("DAC", NULL, MAX9860_PWRMAN, MAX9860_DACEN_SHIFT, 0),
0222 
0223 SND_SOC_DAPM_OUTPUT("OUT"),
0224 
0225 SND_SOC_DAPM_SUPPLY("Supply", SND_SOC_NOPM, 0, 0,
0226             NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0227 SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 0, 0),
0228 SND_SOC_DAPM_REGULATOR_SUPPLY("DVDD", 0, 0),
0229 SND_SOC_DAPM_CLOCK_SUPPLY("mclk"),
0230 };
0231 
0232 static const struct snd_soc_dapm_route max9860_dapm_routes[] = {
0233     { "ADCL", NULL, "MICL" },
0234     { "ADCR", NULL, "MICR" },
0235     { "AIFOUTL", NULL, "ADCL" },
0236     { "AIFOUTR", NULL, "ADCR" },
0237 
0238     { "DAC", NULL, "AIFINL" },
0239     { "DAC", NULL, "AIFINR" },
0240     { "OUT", NULL, "DAC" },
0241 
0242     { "Supply", NULL, "AVDD" },
0243     { "Supply", NULL, "DVDD" },
0244     { "Supply", NULL, "mclk" },
0245 
0246     { "DAC", NULL, "Supply" },
0247     { "ADCL", NULL, "Supply" },
0248     { "ADCR", NULL, "Supply" },
0249 };
0250 
0251 static int max9860_hw_params(struct snd_pcm_substream *substream,
0252                  struct snd_pcm_hw_params *params,
0253                  struct snd_soc_dai *dai)
0254 {
0255     struct snd_soc_component *component = dai->component;
0256     struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
0257     u8 master;
0258     u8 ifc1a = 0;
0259     u8 ifc1b = 0;
0260     u8 sysclk = 0;
0261     unsigned long n;
0262     int ret;
0263 
0264     dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
0265         params_rate(params),
0266         params_channels(params));
0267 
0268     if (params_channels(params) == 2)
0269         ifc1b |= MAX9860_ST;
0270 
0271     switch (max9860->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0272     case SND_SOC_DAIFMT_CBC_CFC:
0273         master = 0;
0274         break;
0275     case SND_SOC_DAIFMT_CBP_CFP:
0276         master = MAX9860_MASTER;
0277         break;
0278     default:
0279         return -EINVAL;
0280     }
0281     ifc1a |= master;
0282 
0283     if (master) {
0284         if (params_width(params) * params_channels(params) > 48)
0285             ifc1b |= MAX9860_BSEL_64X;
0286         else
0287             ifc1b |= MAX9860_BSEL_48X;
0288     }
0289 
0290     switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0291     case SND_SOC_DAIFMT_I2S:
0292         ifc1a |= MAX9860_DDLY;
0293         ifc1b |= MAX9860_ADLY;
0294         break;
0295     case SND_SOC_DAIFMT_LEFT_J:
0296         ifc1a |= MAX9860_WCI;
0297         break;
0298     case SND_SOC_DAIFMT_DSP_A:
0299         if (params_width(params) != 16) {
0300             dev_err(component->dev,
0301                 "DSP_A works for 16 bits per sample only.\n");
0302             return -EINVAL;
0303         }
0304         ifc1a |= MAX9860_DDLY | MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
0305         ifc1b |= MAX9860_ADLY;
0306         break;
0307     case SND_SOC_DAIFMT_DSP_B:
0308         if (params_width(params) != 16) {
0309             dev_err(component->dev,
0310                 "DSP_B works for 16 bits per sample only.\n");
0311             return -EINVAL;
0312         }
0313         ifc1a |= MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
0314         break;
0315     default:
0316         return -EINVAL;
0317     }
0318 
0319     switch (max9860->fmt & SND_SOC_DAIFMT_INV_MASK) {
0320     case SND_SOC_DAIFMT_NB_NF:
0321         break;
0322     case SND_SOC_DAIFMT_NB_IF:
0323         switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0324         case SND_SOC_DAIFMT_DSP_A:
0325         case SND_SOC_DAIFMT_DSP_B:
0326             return -EINVAL;
0327         }
0328         ifc1a ^= MAX9860_WCI;
0329         break;
0330     case SND_SOC_DAIFMT_IB_IF:
0331         switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0332         case SND_SOC_DAIFMT_DSP_A:
0333         case SND_SOC_DAIFMT_DSP_B:
0334             return -EINVAL;
0335         }
0336         ifc1a ^= MAX9860_WCI;
0337         fallthrough;
0338     case SND_SOC_DAIFMT_IB_NF:
0339         ifc1a ^= MAX9860_DBCI;
0340         ifc1b ^= MAX9860_ABCI;
0341         break;
0342     default:
0343         return -EINVAL;
0344     }
0345 
0346     dev_dbg(component->dev, "IFC1A  %02x\n", ifc1a);
0347     ret = regmap_write(max9860->regmap, MAX9860_IFC1A, ifc1a);
0348     if (ret) {
0349         dev_err(component->dev, "Failed to set IFC1A: %d\n", ret);
0350         return ret;
0351     }
0352     dev_dbg(component->dev, "IFC1B  %02x\n", ifc1b);
0353     ret = regmap_write(max9860->regmap, MAX9860_IFC1B, ifc1b);
0354     if (ret) {
0355         dev_err(component->dev, "Failed to set IFC1B: %d\n", ret);
0356         return ret;
0357     }
0358 
0359     /*
0360      * Check if Integer Clock Mode is possible, but avoid it in slave mode
0361      * since we then do not know if lrclk is derived from pclk and the
0362      * datasheet mentions that the frequencies have to match exactly in
0363      * order for this to work.
0364      */
0365     if (params_rate(params) == 8000 || params_rate(params) == 16000) {
0366         if (master) {
0367             switch (max9860->pclk_rate) {
0368             case 12000000:
0369                 sysclk = MAX9860_FREQ_12MHZ;
0370                 break;
0371             case 13000000:
0372                 sysclk = MAX9860_FREQ_13MHZ;
0373                 break;
0374             case 19200000:
0375                 sysclk = MAX9860_FREQ_19_2MHZ;
0376                 break;
0377             default:
0378                 /*
0379                  * Integer Clock Mode not possible. Leave
0380                  * sysclk at zero and fall through to the
0381                  * code below for PLL mode.
0382                  */
0383                 break;
0384             }
0385 
0386             if (sysclk && params_rate(params) == 16000)
0387                 sysclk |= MAX9860_16KHZ;
0388         }
0389     }
0390 
0391     /*
0392      * Largest possible n:
0393      *    65536 * 96 * 48kHz / 10MHz -> 30199
0394      * Smallest possible n:
0395      *    65536 * 96 *  8kHz / 20MHz -> 2517
0396      * Both fit nicely in the available 15 bits, no need to apply any mask.
0397      */
0398     n = DIV_ROUND_CLOSEST_ULL(65536ULL * 96 * params_rate(params),
0399                   max9860->pclk_rate);
0400 
0401     if (!sysclk) {
0402         /* PLL mode */
0403         if (params_rate(params) > 24000)
0404             sysclk |= MAX9860_16KHZ;
0405 
0406         if (!master)
0407             n |= 1; /* trigger rapid pll lock mode */
0408     }
0409 
0410     sysclk |= max9860->psclk;
0411     dev_dbg(component->dev, "SYSCLK %02x\n", sysclk);
0412     ret = regmap_write(max9860->regmap,
0413                MAX9860_SYSCLK, sysclk);
0414     if (ret) {
0415         dev_err(component->dev, "Failed to set SYSCLK: %d\n", ret);
0416         return ret;
0417     }
0418     dev_dbg(component->dev, "N %lu\n", n);
0419     ret = regmap_write(max9860->regmap,
0420                MAX9860_AUDIOCLKHIGH, n >> 8);
0421     if (ret) {
0422         dev_err(component->dev, "Failed to set NHI: %d\n", ret);
0423         return ret;
0424     }
0425     ret = regmap_write(max9860->regmap,
0426                MAX9860_AUDIOCLKLOW, n & 0xff);
0427     if (ret) {
0428         dev_err(component->dev, "Failed to set NLO: %d\n", ret);
0429         return ret;
0430     }
0431 
0432     if (!master) {
0433         dev_dbg(component->dev, "Enable PLL\n");
0434         ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH,
0435                      MAX9860_PLL, MAX9860_PLL);
0436         if (ret) {
0437             dev_err(component->dev, "Failed to enable PLL: %d\n",
0438                 ret);
0439             return ret;
0440         }
0441     }
0442 
0443     return 0;
0444 }
0445 
0446 static int max9860_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0447 {
0448     struct snd_soc_component *component = dai->component;
0449     struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
0450 
0451     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0452     case SND_SOC_DAIFMT_CBP_CFP:
0453     case SND_SOC_DAIFMT_CBC_CFC:
0454         max9860->fmt = fmt;
0455         return 0;
0456 
0457     default:
0458         return -EINVAL;
0459     }
0460 }
0461 
0462 static const struct snd_soc_dai_ops max9860_dai_ops = {
0463     .hw_params = max9860_hw_params,
0464     .set_fmt = max9860_set_fmt,
0465 };
0466 
0467 static struct snd_soc_dai_driver max9860_dai = {
0468     .name = "max9860-hifi",
0469     .playback = {
0470         .stream_name = "Playback",
0471         .channels_min = 1,
0472         .channels_max = 2,
0473         .rates = SNDRV_PCM_RATE_CONTINUOUS,
0474         .rate_min = 8000,
0475         .rate_max = 48000,
0476         .formats = SNDRV_PCM_FMTBIT_S16_LE |
0477                SNDRV_PCM_FMTBIT_S24_LE |
0478                SNDRV_PCM_FMTBIT_S32_LE,
0479     },
0480     .capture = {
0481         .stream_name = "Capture",
0482         .channels_min = 1,
0483         .channels_max = 2,
0484         .rates = SNDRV_PCM_RATE_CONTINUOUS,
0485         .rate_min = 8000,
0486         .rate_max = 48000,
0487         .formats = SNDRV_PCM_FMTBIT_S16_LE |
0488                SNDRV_PCM_FMTBIT_S24_LE |
0489                SNDRV_PCM_FMTBIT_S32_LE,
0490     },
0491     .ops = &max9860_dai_ops,
0492     .symmetric_rate = 1,
0493 };
0494 
0495 static int max9860_set_bias_level(struct snd_soc_component *component,
0496                   enum snd_soc_bias_level level)
0497 {
0498     struct max9860_priv *max9860 = dev_get_drvdata(component->dev);
0499     int ret;
0500 
0501     switch (level) {
0502     case SND_SOC_BIAS_ON:
0503     case SND_SOC_BIAS_PREPARE:
0504         break;
0505 
0506     case SND_SOC_BIAS_STANDBY:
0507         ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
0508                      MAX9860_SHDN, MAX9860_SHDN);
0509         if (ret) {
0510             dev_err(component->dev, "Failed to remove SHDN: %d\n",
0511                 ret);
0512             return ret;
0513         }
0514         break;
0515 
0516     case SND_SOC_BIAS_OFF:
0517         ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
0518                      MAX9860_SHDN, 0);
0519         if (ret) {
0520             dev_err(component->dev, "Failed to request SHDN: %d\n",
0521                 ret);
0522             return ret;
0523         }
0524         break;
0525     }
0526 
0527     return 0;
0528 }
0529 
0530 static const struct snd_soc_component_driver max9860_component_driver = {
0531     .set_bias_level     = max9860_set_bias_level,
0532     .controls       = max9860_controls,
0533     .num_controls       = ARRAY_SIZE(max9860_controls),
0534     .dapm_widgets       = max9860_dapm_widgets,
0535     .num_dapm_widgets   = ARRAY_SIZE(max9860_dapm_widgets),
0536     .dapm_routes        = max9860_dapm_routes,
0537     .num_dapm_routes    = ARRAY_SIZE(max9860_dapm_routes),
0538     .use_pmdown_time    = 1,
0539     .endianness     = 1,
0540 };
0541 
0542 #ifdef CONFIG_PM
0543 static int max9860_suspend(struct device *dev)
0544 {
0545     struct max9860_priv *max9860 = dev_get_drvdata(dev);
0546     int ret;
0547 
0548     ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
0549                  MAX9860_PSCLK, MAX9860_PSCLK_OFF);
0550     if (ret) {
0551         dev_err(dev, "Failed to disable clock: %d\n", ret);
0552         return ret;
0553     }
0554 
0555     regulator_disable(max9860->dvddio);
0556 
0557     return 0;
0558 }
0559 
0560 static int max9860_resume(struct device *dev)
0561 {
0562     struct max9860_priv *max9860 = dev_get_drvdata(dev);
0563     int ret;
0564 
0565     ret = regulator_enable(max9860->dvddio);
0566     if (ret) {
0567         dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
0568         return ret;
0569     }
0570 
0571     regcache_cache_only(max9860->regmap, false);
0572     ret = regcache_sync(max9860->regmap);
0573     if (ret) {
0574         dev_err(dev, "Failed to sync cache: %d\n", ret);
0575         return ret;
0576     }
0577 
0578     ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
0579                  MAX9860_PSCLK, max9860->psclk);
0580     if (ret) {
0581         dev_err(dev, "Failed to enable clock: %d\n", ret);
0582         return ret;
0583     }
0584 
0585     return 0;
0586 }
0587 #endif
0588 
0589 static const struct dev_pm_ops max9860_pm_ops = {
0590     SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL)
0591 };
0592 
0593 static int max9860_probe(struct i2c_client *i2c)
0594 {
0595     struct device *dev = &i2c->dev;
0596     struct max9860_priv *max9860;
0597     int ret;
0598     struct clk *mclk;
0599     unsigned long mclk_rate;
0600     int i;
0601     int intr;
0602 
0603     max9860 = devm_kzalloc(dev, sizeof(struct max9860_priv), GFP_KERNEL);
0604     if (!max9860)
0605         return -ENOMEM;
0606 
0607     max9860->dvddio = devm_regulator_get(dev, "DVDDIO");
0608     if (IS_ERR(max9860->dvddio))
0609         return dev_err_probe(dev, PTR_ERR(max9860->dvddio),
0610                      "Failed to get DVDDIO supply\n");
0611 
0612     max9860->dvddio_nb.notifier_call = max9860_dvddio_event;
0613 
0614     ret = devm_regulator_register_notifier(max9860->dvddio,
0615                            &max9860->dvddio_nb);
0616     if (ret)
0617         dev_err(dev, "Failed to register DVDDIO notifier: %d\n", ret);
0618 
0619     ret = regulator_enable(max9860->dvddio);
0620     if (ret != 0) {
0621         dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
0622         return ret;
0623     }
0624 
0625     max9860->regmap = devm_regmap_init_i2c(i2c, &max9860_regmap);
0626     if (IS_ERR(max9860->regmap)) {
0627         ret = PTR_ERR(max9860->regmap);
0628         goto err_regulator;
0629     }
0630 
0631     dev_set_drvdata(dev, max9860);
0632 
0633     /*
0634      * mclk has to be in the 10MHz to 60MHz range.
0635      * psclk is used to scale mclk into pclk so that
0636      * pclk is in the 10MHz to 20MHz range.
0637      */
0638     mclk = clk_get(dev, "mclk");
0639 
0640     if (IS_ERR(mclk)) {
0641         ret = PTR_ERR(mclk);
0642         dev_err_probe(dev, ret, "Failed to get MCLK\n");
0643         goto err_regulator;
0644     }
0645 
0646     mclk_rate = clk_get_rate(mclk);
0647     clk_put(mclk);
0648 
0649     if (mclk_rate > 60000000 || mclk_rate < 10000000) {
0650         dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
0651             mclk_rate);
0652         ret = -EINVAL;
0653         goto err_regulator;
0654     }
0655     if (mclk_rate >= 40000000)
0656         max9860->psclk = 3;
0657     else if (mclk_rate >= 20000000)
0658         max9860->psclk = 2;
0659     else
0660         max9860->psclk = 1;
0661     max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
0662     max9860->psclk <<= MAX9860_PSCLK_SHIFT;
0663     dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);
0664 
0665     regcache_cache_bypass(max9860->regmap, true);
0666     for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
0667         ret = regmap_write(max9860->regmap,
0668                    max9860_regmap.reg_defaults[i].reg,
0669                    max9860_regmap.reg_defaults[i].def);
0670         if (ret) {
0671             dev_err(dev, "Failed to initialize register %u: %d\n",
0672                 max9860_regmap.reg_defaults[i].reg, ret);
0673             goto err_regulator;
0674         }
0675     }
0676     regcache_cache_bypass(max9860->regmap, false);
0677 
0678     ret = regmap_read(max9860->regmap, MAX9860_INTRSTATUS, &intr);
0679     if (ret) {
0680         dev_err(dev, "Failed to clear INTRSTATUS: %d\n", ret);
0681         goto err_regulator;
0682     }
0683 
0684     pm_runtime_set_active(dev);
0685     pm_runtime_enable(dev);
0686     pm_runtime_idle(dev);
0687 
0688     ret = devm_snd_soc_register_component(dev, &max9860_component_driver,
0689                           &max9860_dai, 1);
0690     if (ret) {
0691         dev_err(dev, "Failed to register CODEC: %d\n", ret);
0692         goto err_pm;
0693     }
0694 
0695     return 0;
0696 
0697 err_pm:
0698     pm_runtime_disable(dev);
0699 err_regulator:
0700     regulator_disable(max9860->dvddio);
0701     return ret;
0702 }
0703 
0704 static int max9860_remove(struct i2c_client *i2c)
0705 {
0706     struct device *dev = &i2c->dev;
0707     struct max9860_priv *max9860 = dev_get_drvdata(dev);
0708 
0709     pm_runtime_disable(dev);
0710     regulator_disable(max9860->dvddio);
0711     return 0;
0712 }
0713 
0714 static const struct i2c_device_id max9860_i2c_id[] = {
0715     { "max9860", },
0716     { }
0717 };
0718 MODULE_DEVICE_TABLE(i2c, max9860_i2c_id);
0719 
0720 static const struct of_device_id max9860_of_match[] = {
0721     { .compatible = "maxim,max9860", },
0722     { }
0723 };
0724 MODULE_DEVICE_TABLE(of, max9860_of_match);
0725 
0726 static struct i2c_driver max9860_i2c_driver = {
0727     .probe_new      = max9860_probe,
0728     .remove         = max9860_remove,
0729     .id_table       = max9860_i2c_id,
0730     .driver         = {
0731         .name           = "max9860",
0732         .of_match_table = max9860_of_match,
0733         .pm             = &max9860_pm_ops,
0734     },
0735 };
0736 
0737 module_i2c_driver(max9860_i2c_driver);
0738 
0739 MODULE_DESCRIPTION("ASoC MAX9860 Mono Audio Voice Codec driver");
0740 MODULE_AUTHOR("Peter Rosin <peda@axentia.se>");
0741 MODULE_LICENSE("GPL v2");
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