soc/codecs/max98520.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2021, Maxim Integrated.
0004  */
0005
0006 #ifndef _MAX98520_H
0007 #define _MAX98520_H
0008
0009 #define MAX98520_R2000_SW_RESET 0x2000
0010 #define MAX98520_R2001_STATUS_1 0x2001
0011 #define MAX98520_R2002_STATUS_2 0x2002
0012 #define MAX98520_R2020_THERM_WARN_THRESH 0x2020
0013 #define MAX98520_R2021_THERM_SHDN_THRESH 0x2021
0014 #define MAX98520_R2022_THERM_HYSTERESIS 0x2022
0015 #define MAX98520_R2023_THERM_FOLDBACK_SET 0x2023
0016 #define MAX98520_R2027_THERM_FOLDBACK_EN 0x2027
0017 #define MAX98520_R2030_CLK_MON_CTRL 0x2030
0018 #define MAX98520_R2037_ERR_MON_CTRL 0x2037
0019 #define MAX98520_R2040_PCM_MODE_CFG 0x2040
0020 #define MAX98520_R2041_PCM_CLK_SETUP 0x2041
0021 #define MAX98520_R2042_PCM_SR_SETUP 0x2042
0022 #define MAX98520_R2043_PCM_RX_SRC1 0x2043
0023 #define MAX98520_R2044_PCM_RX_SRC2 0x2044
0024 #define MAX98520_R204F_PCM_RX_EN 0x204F
0025 #define MAX98520_R2090_AMP_VOL_CTRL 0x2090
0026 #define MAX98520_R2091_AMP_PATH_GAIN 0x2091
0027 #define MAX98520_R2092_AMP_DSP_CFG 0x2092
0028 #define MAX98520_R2094_SSM_CFG 0x2094
0029 #define MAX98520_R2095_AMP_CFG 0x2095
0030 #define MAX98520_R209F_AMP_EN 0x209F
0031 #define MAX98520_R20B0_ADC_SR 0x20B0
0032 #define MAX98520_R20B1_ADC_RESOLUTION 0x20B1
0033 #define MAX98520_R20B2_ADC_PVDD0_CFG 0x20B2
0034 #define MAX98520_R20B3_ADC_THERMAL_CFG 0x20B3
0035 #define MAX98520_R20B4_ADC_READBACK_CTRL 0x20B4
0036 #define MAX98520_R20B5_ADC_READBACK_UPDATE 0x20B5
0037 #define MAX98520_R20B6_ADC_PVDD_READBACK_MSB 0x20B6
0038 #define MAX98520_R20B7_ADC_PVDD_READBACK_LSB 0x20B7
0039 #define MAX98520_R20B8_ADC_TEMP_READBACK_MSB 0x20B8
0040 #define MAX98520_R20B9_ADC_TEMP_READBACK_LSB 0x20B9
0041 #define MAX98520_R20BA_ADC_LOW_PVDD_READBACK_MSB 0x20BA
0042 #define MAX98520_R20BB_ADC_LOW_READBACK_LSB 0x20BB
0043 #define MAX98520_R20BC_ADC_HIGH_TEMP_READBACK_MSB 0x20BC
0044 #define MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB 0x20BD
0045 #define MAX98520_R20CF_MEAS_ADC_CFG 0x20CF
0046 #define MAX98520_R20D0_DHT_CFG1 0x20D0
0047 #define MAX98520_R20D1_LIMITER_CFG1 0x20D1
0048 #define MAX98520_R20D2_LIMITER_CFG2 0x20D2
0049 #define MAX98520_R20D3_DHT_CFG2 0x20D3
0050 #define MAX98520_R20D4_DHT_CFG3 0x20D4
0051 #define MAX98520_R20D5_DHT_CFG4 0x20D5
0052 #define MAX98520_R20D6_DHT_HYSTERESIS_CFG 0x20D6
0053 #define MAX98520_R20D8_DHT_EN 0x20D8
0054 #define MAX98520_R210E_AUTO_RESTART_BEHAVIOR 0x210E
0055 #define MAX98520_R210F_GLOBAL_EN 0x210F
0056 #define MAX98520_R2161_BOOST_TM1 0x2161
0057 #define MAX98520_R2162_BOOST_TM2 0x2162
0058 #define MAX98520_R2163_BOOST_TM3 0x2163
0059 #define MAX98520_R21FF_REVISION_ID 0x21FF
0060
0061 /* MAX98520_R2030_CLK_MON_CTRL */
0062 #define MAX98520_CMON_AUTORESTART_SHIFT (0)
0063
0064 /* MAX98520_R2037_ERR_MON_CTRL */
0065 #define MAX98520_CTRL_CMON_EN_SHIFT (0)
0066
0067 /* MAX98520_R2040_PCM_MODE_CFG */
0068 #define MAX98520_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
0069 #define MAX98520_PCM_MODE_CFG_FORMAT_SHIFT (3)
0070 #define MAX98520_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
0071 #define MAX98520_PCM_FORMAT_I2S (0x0 << 3)
0072 #define MAX98520_PCM_FORMAT_LJ (0x1 << 3)
0073 #define MAX98520_PCM_FORMAT_TDM_MODE0 (0x3 << 3)
0074 #define MAX98520_PCM_FORMAT_TDM_MODE1 (0x4 << 3)
0075 #define MAX98520_PCM_FORMAT_TDM_MODE2 (0x5 << 3)
0076 #define MAX98520_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
0077 #define MAX98520_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
0078 #define MAX98520_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
0079 #define MAX98520_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
0080
0081 /* MAX98520_R2041_PCM_CLK_SETUP */
0082 #define MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
0083 #define MAX98520_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
0084
0085 /* MAX98520_R2042_PCM_SR_SETUP */
0086 #define MAX98520_PCM_SR_SHIFT (0)
0087 #define MAX98520_IVADC_SR_SHIFT (4)
0088 #define MAX98520_PCM_SR_MASK (0xF << MAX98520_PCM_SR_SHIFT)
0089 #define MAX98520_IVADC_SR_MASK (0xF << MAX98520_IVADC_SR_SHIFT)
0090 #define MAX98520_PCM_SR_8000 (0x0)
0091 #define MAX98520_PCM_SR_11025 (0x1)
0092 #define MAX98520_PCM_SR_12000 (0x2)
0093 #define MAX98520_PCM_SR_16000 (0x3)
0094 #define MAX98520_PCM_SR_22050 (0x4)
0095 #define MAX98520_PCM_SR_24000 (0x5)
0096 #define MAX98520_PCM_SR_32000 (0x6)
0097 #define MAX98520_PCM_SR_44100 (0x7)
0098 #define MAX98520_PCM_SR_48000 (0x8)
0099 #define MAX98520_PCM_SR_88200 (0x9)
0100 #define MAX98520_PCM_SR_96000 (0xA)
0101 #define MAX98520_PCM_SR_176400 (0xB)
0102 #define MAX98520_PCM_SR_192000 (0xC)
0103
0104 /* MAX98520_R2044_PCM_RX_SRC2 */
0105 #define MAX98520_PCM_DMIX_CH1_SHIFT (0xF << 0)
0106 #define MAX98520_PCM_DMIX_CH0_SRC_MASK (0xF << 0)
0107 #define MAX98520_PCM_DMIX_CH1_SRC_MASK (0xF << MAX98520_PCM_DMIX_CH1_SHIFT)
0108
0109 /* MAX98520_R204F_PCM_RX_EN */
0110 #define MAX98520_PCM_RX_EN_MASK (0x1 << 0)
0111 #define MAX98520_PCM_RX_BYP_EN_MASK (0x1 << 1)
0112
0113 /* MAX98520_R2092_AMP_DSP_CFG */
0114 #define MAX98520_DSP_SPK_DCBLK_EN_SHIFT (0)
0115 #define MAX98520_DSP_SPK_DITH_EN_SHIFT (1)
0116 #define MAX98520_DSP_SPK_INVERT_SHIFT (2)
0117 #define MAX98520_DSP_SPK_VOL_RMPUP_SHIFT (3)
0118 #define MAX98520_DSP_SPK_VOL_RMPDN_SHIFT (4)
0119 #define MAX98520_DSP_SPK_SAFE_EN_SHIFT (5)
0120
0121 #define MAX98520_SPK_SAFE_EN_MASK (0x1 << MAX98520_DSP_SPK_SAFE_EN_SHIFT)
0122
0123 /* MAX98520_R2094_SSM_CFG */
0124 #define MAX98520_SSM_EN_SHIFT (0)
0125 #define MAX98520_SSM_MOD_SHIFT (1)
0126 #define MAX98520_SSM_RCVR_MODE_SHIFT (3)
0127
0128 /* MAX98520_R2095_AMP_CFG */
0129 #define MAX98520_CFG_DYN_MODE_SHIFT (4)
0130 #define MAX98520_CFG_SPK_MODE_SHIFT (3)
0131
0132 /* MAX98520_R20D0_DHT_CFG1 */
0133 #define MAX98520_DHT_VROT_PNT_SHIFT (0)
0134
0135 /* MAX98520_R20D1_LIMITER_CFG1 */
0136 #define MAX98520_DHT_SUPPLY_HR_SHIFT (0)
0137
0138 /* MAX98520_R20D2_DHT_CFG2 */
0139 #define MAX98520_DHT_LIMITER_MODE_SHIFT (0)
0140 #define MAX98520_DHT_LIMITER_THRESHOLD_SHIFT (1)
0141
0142 /* MAX98520_R20D3_DHT_CFG2 */
0143 #define MAX98520_DHT_MAX_ATTEN_SHIFT (0)
0144
0145 /* MAX98520_R20D6_DHT_HYSTERESIS_CFG */
0146 #define MAX98520_DHT_HYSTERESIS_SWITCH_SHIFT (0)
0147 #define MAX98520_DHT_HYSTERESIS_SHIFT (1)
0148
0149 /* MAX98520_R20B2_ADC_PVDD0_CFG, MAX98520_R20B3_ADC_THERMAL_CFG */
0150 #define MAX98520_FLT_EN_SHIFT (4)
0151
0152 struct max98520_priv {
0153     struct regmap *regmap;
0154     struct gpio_desc *reset_gpio;
0155     unsigned int ch_size;
0156     bool tdm_mode;
0157 };
0158 #endif
0159