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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2021, Maxim Integrated
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/delay.h>
0006 #include <linux/i2c.h>
0007 #include <linux/module.h>
0008 #include <linux/regmap.h>
0009 #include <linux/slab.h>
0010 #include <linux/cdev.h>
0011 #include <sound/pcm.h>
0012 #include <sound/pcm_params.h>
0013 #include <sound/soc.h>
0014 #include <linux/gpio.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/of.h>
0017 #include <linux/of_gpio.h>
0018 #include <sound/tlv.h>
0019 #include "max98520.h"
0020 
0021 static struct reg_default max98520_reg[] = {
0022     {MAX98520_R2000_SW_RESET, 0x00},
0023     {MAX98520_R2001_STATUS_1, 0x00},
0024     {MAX98520_R2002_STATUS_2, 0x00},
0025     {MAX98520_R2020_THERM_WARN_THRESH, 0x46},
0026     {MAX98520_R2021_THERM_SHDN_THRESH, 0x64},
0027     {MAX98520_R2022_THERM_HYSTERESIS, 0x02},
0028     {MAX98520_R2023_THERM_FOLDBACK_SET, 0x31},
0029     {MAX98520_R2027_THERM_FOLDBACK_EN, 0x01},
0030     {MAX98520_R2030_CLK_MON_CTRL, 0x00},
0031     {MAX98520_R2037_ERR_MON_CTRL, 0x01},
0032     {MAX98520_R2040_PCM_MODE_CFG, 0xC0},
0033     {MAX98520_R2041_PCM_CLK_SETUP, 0x04},
0034     {MAX98520_R2042_PCM_SR_SETUP, 0x08},
0035     {MAX98520_R2043_PCM_RX_SRC1, 0x00},
0036     {MAX98520_R2044_PCM_RX_SRC2, 0x00},
0037     {MAX98520_R204F_PCM_RX_EN, 0x00},
0038     {MAX98520_R2090_AMP_VOL_CTRL, 0x00},
0039     {MAX98520_R2091_AMP_PATH_GAIN, 0x03},
0040     {MAX98520_R2092_AMP_DSP_CFG, 0x02},
0041     {MAX98520_R2094_SSM_CFG, 0x01},
0042     {MAX98520_R2095_AMP_CFG, 0xF0},
0043     {MAX98520_R209F_AMP_EN, 0x00},
0044     {MAX98520_R20B0_ADC_SR, 0x00},
0045     {MAX98520_R20B1_ADC_RESOLUTION, 0x00},
0046     {MAX98520_R20B2_ADC_PVDD0_CFG, 0x02},
0047     {MAX98520_R20B3_ADC_THERMAL_CFG, 0x02},
0048     {MAX98520_R20B4_ADC_READBACK_CTRL, 0x00},
0049     {MAX98520_R20B5_ADC_READBACK_UPDATE, 0x00},
0050     {MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0x00},
0051     {MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0x00},
0052     {MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0x00},
0053     {MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0x00},
0054     {MAX98520_R20BA_ADC_LOW_PVDD_READBACK_MSB, 0xFF},
0055     {MAX98520_R20BB_ADC_LOW_READBACK_LSB, 0x01},
0056     {MAX98520_R20BC_ADC_HIGH_TEMP_READBACK_MSB, 0x00},
0057     {MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB, 0x00},
0058     {MAX98520_R20CF_MEAS_ADC_CFG, 0x00},
0059     {MAX98520_R20D0_DHT_CFG1, 0x00},
0060     {MAX98520_R20D1_LIMITER_CFG1, 0x08},
0061     {MAX98520_R20D2_LIMITER_CFG2, 0x00},
0062     {MAX98520_R20D3_DHT_CFG2, 0x14},
0063     {MAX98520_R20D4_DHT_CFG3, 0x02},
0064     {MAX98520_R20D5_DHT_CFG4, 0x04},
0065     {MAX98520_R20D6_DHT_HYSTERESIS_CFG, 0x07},
0066     {MAX98520_R20D8_DHT_EN, 0x00},
0067     {MAX98520_R210E_AUTO_RESTART_BEHAVIOR, 0x00},
0068     {MAX98520_R210F_GLOBAL_EN, 0x00},
0069     {MAX98520_R21FF_REVISION_ID, 0x00},
0070 };
0071 
0072 static int max98520_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0073 {
0074     struct snd_soc_component *component = codec_dai->component;
0075     struct max98520_priv *max98520 =
0076         snd_soc_component_get_drvdata(component);
0077     unsigned int format = 0;
0078     unsigned int invert = 0;
0079 
0080     dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
0081 
0082     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0083     case SND_SOC_DAIFMT_NB_NF:
0084         break;
0085     case SND_SOC_DAIFMT_IB_NF:
0086         invert = MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE;
0087         break;
0088     default:
0089         dev_err(component->dev, "DAI invert mode unsupported\n");
0090         return -EINVAL;
0091     }
0092 
0093     regmap_update_bits(max98520->regmap,
0094                MAX98520_R2041_PCM_CLK_SETUP,
0095                MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE,
0096                invert);
0097 
0098     /* interface format */
0099     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0100     case SND_SOC_DAIFMT_I2S:
0101         format = MAX98520_PCM_FORMAT_I2S;
0102         break;
0103     case SND_SOC_DAIFMT_LEFT_J:
0104         format = MAX98520_PCM_FORMAT_LJ;
0105         break;
0106     case SND_SOC_DAIFMT_DSP_A:
0107         format = MAX98520_PCM_FORMAT_TDM_MODE1;
0108         break;
0109     case SND_SOC_DAIFMT_DSP_B:
0110         format = MAX98520_PCM_FORMAT_TDM_MODE0;
0111         break;
0112     default:
0113         return -EINVAL;
0114     }
0115 
0116     regmap_update_bits(max98520->regmap,
0117                MAX98520_R2040_PCM_MODE_CFG,
0118                MAX98520_PCM_MODE_CFG_FORMAT_MASK,
0119                format << MAX98520_PCM_MODE_CFG_FORMAT_SHIFT);
0120 
0121     return 0;
0122 }
0123 
0124 /* BCLKs per LRCLK */
0125 static const int bclk_sel_table[] = {
0126     32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
0127 };
0128 
0129 static int max98520_get_bclk_sel(int bclk)
0130 {
0131     int i;
0132     /* match BCLKs per LRCLK */
0133     for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
0134         if (bclk_sel_table[i] == bclk)
0135             return i + 2;
0136     }
0137     return 0;
0138 }
0139 
0140 static int max98520_set_clock(struct snd_soc_component *component,
0141                   struct snd_pcm_hw_params *params)
0142 {
0143     struct max98520_priv *max98520 =
0144         snd_soc_component_get_drvdata(component);
0145     /* BCLK/LRCLK ratio calculation */
0146     int blr_clk_ratio = params_channels(params) * max98520->ch_size;
0147     int value;
0148 
0149     if (!max98520->tdm_mode) {
0150         /* BCLK configuration */
0151         value = max98520_get_bclk_sel(blr_clk_ratio);
0152         if (!value) {
0153             dev_err(component->dev, "format unsupported %d\n",
0154                 params_format(params));
0155             return -EINVAL;
0156         }
0157 
0158         regmap_update_bits(max98520->regmap,
0159                    MAX98520_R2041_PCM_CLK_SETUP,
0160                    MAX98520_PCM_CLK_SETUP_BSEL_MASK,
0161                    value);
0162     }
0163     dev_dbg(component->dev, "%s tdm_mode:%d out\n", __func__, max98520->tdm_mode);
0164     return 0;
0165 }
0166 
0167 static int max98520_dai_hw_params(struct snd_pcm_substream *substream,
0168                   struct snd_pcm_hw_params *params,
0169                   struct snd_soc_dai *dai)
0170 {
0171     struct snd_soc_component *component = dai->component;
0172     struct max98520_priv *max98520 =
0173         snd_soc_component_get_drvdata(component);
0174     unsigned int sampling_rate = 0;
0175     unsigned int chan_sz = 0;
0176 
0177     /* pcm mode configuration */
0178     switch (snd_pcm_format_width(params_format(params))) {
0179     case 16:
0180         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
0181         break;
0182     case 24:
0183         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
0184         break;
0185     case 32:
0186         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
0187         break;
0188     default:
0189         dev_err(component->dev, "format unsupported %d\n",
0190             params_format(params));
0191         goto err;
0192     }
0193 
0194     max98520->ch_size = snd_pcm_format_width(params_format(params));
0195 
0196     regmap_update_bits(max98520->regmap,
0197                MAX98520_R2040_PCM_MODE_CFG,
0198                MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0199 
0200     dev_dbg(component->dev, "format supported %d",
0201         params_format(params));
0202 
0203     /* sampling rate configuration */
0204     switch (params_rate(params)) {
0205     case 8000:
0206         sampling_rate = MAX98520_PCM_SR_8000;
0207         break;
0208     case 11025:
0209         sampling_rate = MAX98520_PCM_SR_11025;
0210         break;
0211     case 12000:
0212         sampling_rate = MAX98520_PCM_SR_12000;
0213         break;
0214     case 16000:
0215         sampling_rate = MAX98520_PCM_SR_16000;
0216         break;
0217     case 22050:
0218         sampling_rate = MAX98520_PCM_SR_22050;
0219         break;
0220     case 24000:
0221         sampling_rate = MAX98520_PCM_SR_24000;
0222         break;
0223     case 32000:
0224         sampling_rate = MAX98520_PCM_SR_32000;
0225         break;
0226     case 44100:
0227         sampling_rate = MAX98520_PCM_SR_44100;
0228         break;
0229     case 48000:
0230         sampling_rate = MAX98520_PCM_SR_48000;
0231         break;
0232     case 88200:
0233         sampling_rate = MAX98520_PCM_SR_88200;
0234         break;
0235     case 96000:
0236         sampling_rate = MAX98520_PCM_SR_96000;
0237         break;
0238     case 176400:
0239         sampling_rate = MAX98520_PCM_SR_176400;
0240         break;
0241     case 192000:
0242         sampling_rate = MAX98520_PCM_SR_192000;
0243         break;
0244     default:
0245         dev_err(component->dev, "rate %d not supported\n",
0246             params_rate(params));
0247         goto err;
0248     }
0249 
0250     dev_dbg(component->dev, " %s ch_size: %d, sampling rate : %d out\n", __func__,
0251         snd_pcm_format_width(params_format(params)), params_rate(params));
0252     /* set DAI_SR to correct LRCLK frequency */
0253     regmap_update_bits(max98520->regmap,
0254                MAX98520_R2042_PCM_SR_SETUP,
0255                MAX98520_PCM_SR_MASK,
0256                sampling_rate);
0257 
0258     return max98520_set_clock(component, params);
0259 err:
0260     dev_dbg(component->dev, "%s out error", __func__);
0261     return -EINVAL;
0262 }
0263 
0264 static int max98520_dai_tdm_slot(struct snd_soc_dai *dai,
0265                  unsigned int tx_mask, unsigned int rx_mask,
0266                  int slots, int slot_width)
0267 {
0268     struct snd_soc_component *component = dai->component;
0269     struct max98520_priv *max98520 =
0270         snd_soc_component_get_drvdata(component);
0271     int bsel;
0272     unsigned int chan_sz = 0;
0273 
0274     if (!tx_mask && !rx_mask && !slots && !slot_width)
0275         max98520->tdm_mode = false;
0276     else
0277         max98520->tdm_mode = true;
0278 
0279     /* BCLK configuration */
0280     bsel = max98520_get_bclk_sel(slots * slot_width);
0281     if (bsel == 0) {
0282         dev_err(component->dev, "BCLK %d not supported\n",
0283             slots * slot_width);
0284         return -EINVAL;
0285     }
0286 
0287     regmap_update_bits(max98520->regmap,
0288                MAX98520_R2041_PCM_CLK_SETUP,
0289                MAX98520_PCM_CLK_SETUP_BSEL_MASK,
0290                bsel);
0291 
0292     /* Channel size configuration */
0293     switch (slot_width) {
0294     case 16:
0295         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
0296         break;
0297     case 24:
0298         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
0299         break;
0300     case 32:
0301         chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
0302         break;
0303     default:
0304         dev_err(component->dev, "format unsupported %d\n",
0305             slot_width);
0306         return -EINVAL;
0307     }
0308 
0309     regmap_update_bits(max98520->regmap,
0310                MAX98520_R2040_PCM_MODE_CFG,
0311                MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0312 
0313     /* Rx slot configuration */
0314     regmap_update_bits(max98520->regmap,
0315                MAX98520_R2044_PCM_RX_SRC2,
0316                MAX98520_PCM_DMIX_CH0_SRC_MASK,
0317                rx_mask);
0318     regmap_update_bits(max98520->regmap,
0319                MAX98520_R2044_PCM_RX_SRC2,
0320                MAX98520_PCM_DMIX_CH1_SRC_MASK,
0321                rx_mask << MAX98520_PCM_DMIX_CH1_SHIFT);
0322 
0323     return 0;
0324 }
0325 
0326 #define MAX98520_RATES SNDRV_PCM_RATE_8000_192000
0327 
0328 #define MAX98520_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0329     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0330 
0331 static const struct snd_soc_dai_ops max98520_dai_ops = {
0332     .set_fmt = max98520_dai_set_fmt,
0333     .hw_params = max98520_dai_hw_params,
0334     .set_tdm_slot = max98520_dai_tdm_slot,
0335 };
0336 
0337 static int max98520_dac_event(struct snd_soc_dapm_widget *w,
0338                   struct snd_kcontrol *kcontrol, int event)
0339 {
0340     struct snd_soc_component *component =
0341         snd_soc_dapm_to_component(w->dapm);
0342     struct max98520_priv *max98520 =
0343         snd_soc_component_get_drvdata(component);
0344 
0345     switch (event) {
0346     case SND_SOC_DAPM_POST_PMU:
0347         dev_dbg(component->dev, " AMP ON\n");
0348 
0349         regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 1);
0350         regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 1);
0351         usleep_range(30000, 31000);
0352         break;
0353     case SND_SOC_DAPM_POST_PMD:
0354         dev_dbg(component->dev, " AMP OFF\n");
0355 
0356         regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 0);
0357         regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 0);
0358         usleep_range(30000, 31000);
0359         break;
0360     default:
0361         return 0;
0362     }
0363     return 0;
0364 }
0365 
0366 static const char * const max98520_switch_text[] = {
0367     "Left", "Right", "LeftRight"};
0368 
0369 static const struct soc_enum dai_sel_enum =
0370     SOC_ENUM_SINGLE(MAX98520_R2043_PCM_RX_SRC1,
0371             0, 3, max98520_switch_text);
0372 
0373 static const struct snd_kcontrol_new max98520_dai_controls =
0374     SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
0375 
0376 static const struct snd_kcontrol_new max98520_left_input_mixer_controls[] = {
0377     SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 0, 0x0, 0),
0378     SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 0, 0x1, 0),
0379     SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 0, 0x2, 0),
0380     SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 0, 0x3, 0),
0381     SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 0, 0x4, 0),
0382     SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 0, 0x5, 0),
0383     SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 0, 0x6, 0),
0384     SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 0, 0x7, 0),
0385     SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 0, 0x8, 0),
0386     SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 0, 0x9, 0),
0387     SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 0, 0xa, 0),
0388     SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 0, 0xb, 0),
0389     SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 0, 0xc, 0),
0390     SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 0, 0xd, 0),
0391     SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 0, 0xe, 0),
0392     SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 0, 0xf, 0),
0393 };
0394 
0395 static const struct snd_kcontrol_new max98520_right_input_mixer_controls[] = {
0396     SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 4, 0x0, 0),
0397     SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 4, 0x1, 0),
0398     SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 4, 0x2, 0),
0399     SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 4, 0x3, 0),
0400     SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 4, 0x4, 0),
0401     SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 4, 0x5, 0),
0402     SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 4, 0x6, 0),
0403     SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 4, 0x7, 0),
0404     SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 4, 0x8, 0),
0405     SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 4, 0x9, 0),
0406     SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 4, 0xa, 0),
0407     SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 4, 0xb, 0),
0408     SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 4, 0xc, 0),
0409     SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 4, 0xd, 0),
0410     SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 4, 0xe, 0),
0411     SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 4, 0xf, 0),
0412 };
0413 
0414 static const struct snd_soc_dapm_widget max98520_dapm_widgets[] = {
0415     SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
0416                SND_SOC_NOPM, 0, 0, max98520_dac_event,
0417     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0418     SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, &max98520_dai_controls),
0419     SND_SOC_DAPM_OUTPUT("BE_OUT"),
0420     /* Left Input Selection */
0421     SND_SOC_DAPM_MIXER("Left Input Selection", SND_SOC_NOPM, 0, 0,
0422                &max98520_left_input_mixer_controls[0],
0423                ARRAY_SIZE(max98520_left_input_mixer_controls)),
0424     /* Right Input Selection */
0425     SND_SOC_DAPM_MIXER("Right Input Selection", SND_SOC_NOPM, 0, 0,
0426                &max98520_right_input_mixer_controls[0],
0427                ARRAY_SIZE(max98520_right_input_mixer_controls)),
0428 };
0429 
0430 static const DECLARE_TLV_DB_SCALE(max98520_digital_tlv, -6300, 50, 1);
0431 static const DECLARE_TLV_DB_SCALE(max98520_spk_tlv, -600, 300, 0);
0432 
0433 static const DECLARE_TLV_DB_RANGE(max98520_dht_lim_thresh_tlv,
0434     0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
0435 );
0436 
0437 static const DECLARE_TLV_DB_RANGE(max98520_dht_hysteresis_tlv,
0438     0, 3, TLV_DB_SCALE_ITEM(100, 100, 0),
0439     4, 7, TLV_DB_SCALE_ITEM(600, 200, 0),
0440 );
0441 
0442 static const DECLARE_TLV_DB_RANGE(max98520_dht_rotation_point_tlv,
0443     0, 1, TLV_DB_SCALE_ITEM(-1500, 300, 0),
0444     2, 4, TLV_DB_SCALE_ITEM(-1000, 200, 0),
0445     5, 10, TLV_DB_SCALE_ITEM(-500, 100, 0),
0446 );
0447 
0448 static const DECLARE_TLV_DB_RANGE(max98520_dht_supply_hr_tlv,
0449     0, 16, TLV_DB_SCALE_ITEM(-2000, 250, 0),
0450 );
0451 
0452 static const DECLARE_TLV_DB_RANGE(max98520_dht_max_atten_tlv,
0453     1, 20, TLV_DB_SCALE_ITEM(-2000, 100, 0),
0454 );
0455 
0456 static const char * const max98520_dht_attack_rate_text[] = {
0457     "20us", "40us", "80us", "160us", "320us", "640us",
0458     "1.28ms", "2.56ms", "5.12ms", "10.24ms", "20.48ms", "40.96ms",
0459     "81.92ms", "163.84ms"
0460 };
0461 
0462 static SOC_ENUM_SINGLE_DECL(max98520_dht_attack_rate_enum,
0463                 MAX98520_R20D4_DHT_CFG3, 0,
0464                 max98520_dht_attack_rate_text);
0465 
0466 static const char * const max98520_dht_release_rate_text[] = {
0467     "2ms", "4ms", "8ms", "16ms", "32ms", "64ms", "128ms", "256ms", "512ms",
0468     "1.024s", "2.048s", "4.096s", "8.192s", "16.384s"
0469 };
0470 
0471 static SOC_ENUM_SINGLE_DECL(max98520_dht_release_rate_enum,
0472                 MAX98520_R20D5_DHT_CFG4, 0,
0473                 max98520_dht_release_rate_text);
0474 
0475 static bool max98520_readable_register(struct device *dev, unsigned int reg)
0476 {
0477     switch (reg) {
0478     case MAX98520_R2000_SW_RESET:
0479     case MAX98520_R2027_THERM_FOLDBACK_EN:
0480     case MAX98520_R2030_CLK_MON_CTRL:
0481     case MAX98520_R2037_ERR_MON_CTRL:
0482     case MAX98520_R204F_PCM_RX_EN:
0483     case MAX98520_R209F_AMP_EN:
0484     case MAX98520_R20CF_MEAS_ADC_CFG:
0485     case MAX98520_R20D8_DHT_EN:
0486     case MAX98520_R21FF_REVISION_ID:
0487     case MAX98520_R2001_STATUS_1... MAX98520_R2002_STATUS_2:
0488     case MAX98520_R2020_THERM_WARN_THRESH... MAX98520_R2023_THERM_FOLDBACK_SET:
0489     case MAX98520_R2040_PCM_MODE_CFG... MAX98520_R2044_PCM_RX_SRC2:
0490     case MAX98520_R2090_AMP_VOL_CTRL... MAX98520_R2092_AMP_DSP_CFG:
0491     case MAX98520_R2094_SSM_CFG... MAX98520_R2095_AMP_CFG:
0492     case MAX98520_R20B0_ADC_SR... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
0493     case MAX98520_R20D0_DHT_CFG1... MAX98520_R20D6_DHT_HYSTERESIS_CFG:
0494     case MAX98520_R210E_AUTO_RESTART_BEHAVIOR... MAX98520_R210F_GLOBAL_EN:
0495     case MAX98520_R2161_BOOST_TM1... MAX98520_R2163_BOOST_TM3:
0496         return true;
0497     default:
0498         return false;
0499     }
0500 };
0501 
0502 static bool max98520_volatile_reg(struct device *dev, unsigned int reg)
0503 {
0504     switch (reg) {
0505     case MAX98520_R210F_GLOBAL_EN:
0506     case MAX98520_R21FF_REVISION_ID:
0507     case MAX98520_R2000_SW_RESET:
0508     case MAX98520_R2001_STATUS_1 ... MAX98520_R2002_STATUS_2:
0509     case MAX98520_R20B4_ADC_READBACK_CTRL
0510         ... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
0511         return true;
0512     default:
0513         return false;
0514     }
0515 }
0516 
0517 static const struct snd_kcontrol_new max98520_snd_controls[] = {
0518 /* Volume */
0519 SOC_SINGLE_TLV("Digital Volume", MAX98520_R2090_AMP_VOL_CTRL,
0520            0, 0x7F, 1, max98520_digital_tlv),
0521 SOC_SINGLE_TLV("Speaker Volume", MAX98520_R2091_AMP_PATH_GAIN,
0522            0, 0x5, 0, max98520_spk_tlv),
0523 /* Volume Ramp Up/Down Enable*/
0524 SOC_SINGLE("Ramp Up Switch", MAX98520_R2092_AMP_DSP_CFG,
0525        MAX98520_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0),
0526 SOC_SINGLE("Ramp Down Switch", MAX98520_R2092_AMP_DSP_CFG,
0527        MAX98520_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0),
0528 /* Clock Monitor Enable */
0529 SOC_SINGLE("CLK Monitor Switch", MAX98520_R2037_ERR_MON_CTRL,
0530        MAX98520_CTRL_CMON_EN_SHIFT, 1, 0),
0531 /* Clock Monitor Config */
0532 SOC_SINGLE("CLKMON Autorestart Switch", MAX98520_R2030_CLK_MON_CTRL,
0533        MAX98520_CMON_AUTORESTART_SHIFT, 1, 0),
0534 /* Dither Enable */
0535 SOC_SINGLE("Dither Switch", MAX98520_R2092_AMP_DSP_CFG,
0536        MAX98520_DSP_SPK_DITH_EN_SHIFT, 1, 0),
0537 /* DC Blocker Enable */
0538 SOC_SINGLE("DC Blocker Switch", MAX98520_R2092_AMP_DSP_CFG,
0539        MAX98520_DSP_SPK_DCBLK_EN_SHIFT, 1, 0),
0540 /* Speaker Safe Mode Enable */
0541 SOC_SINGLE("Speaker Safemode Switch", MAX98520_R2092_AMP_DSP_CFG,
0542        MAX98520_DSP_SPK_SAFE_EN_SHIFT, 1, 0),
0543 /* AMP SSM Enable */
0544 SOC_SINGLE("CP Bypass Switch", MAX98520_R2094_SSM_CFG,
0545        MAX98520_SSM_RCVR_MODE_SHIFT, 1, 0),
0546 /* Dynamic Headroom Tracking */
0547 SOC_SINGLE("DHT Switch", MAX98520_R20D8_DHT_EN, 0, 1, 0),
0548 SOC_SINGLE("DHT Limiter Mode", MAX98520_R20D2_LIMITER_CFG2,
0549        MAX98520_DHT_LIMITER_MODE_SHIFT, 1, 0),
0550 SOC_SINGLE("DHT Hysteresis Switch", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
0551        MAX98520_DHT_HYSTERESIS_SWITCH_SHIFT, 1, 0),
0552 SOC_SINGLE_TLV("DHT Rot Pnt", MAX98520_R20D0_DHT_CFG1,
0553            MAX98520_DHT_VROT_PNT_SHIFT, 10, 1, max98520_dht_rotation_point_tlv),
0554 SOC_SINGLE_TLV("DHT Supply Headroom", MAX98520_R20D1_LIMITER_CFG1,
0555            MAX98520_DHT_SUPPLY_HR_SHIFT, 16, 0, max98520_dht_supply_hr_tlv),
0556 SOC_SINGLE_TLV("DHT Limiter Threshold", MAX98520_R20D2_LIMITER_CFG2,
0557            MAX98520_DHT_LIMITER_THRESHOLD_SHIFT, 0xF, 1, max98520_dht_lim_thresh_tlv),
0558 SOC_SINGLE_TLV("DHT Max Attenuation", MAX98520_R20D3_DHT_CFG2,
0559            MAX98520_DHT_MAX_ATTEN_SHIFT, 20, 1, max98520_dht_max_atten_tlv),
0560 SOC_SINGLE_TLV("DHT Hysteresis", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
0561            MAX98520_DHT_HYSTERESIS_SHIFT, 0x7, 0, max98520_dht_hysteresis_tlv),
0562 SOC_ENUM("DHT Attack Rate", max98520_dht_attack_rate_enum),
0563 SOC_ENUM("DHT Release Rate", max98520_dht_release_rate_enum),
0564 /* ADC configuration */
0565 SOC_SINGLE("ADC PVDD CH Switch", MAX98520_R20CF_MEAS_ADC_CFG, 0, 1, 0),
0566 SOC_SINGLE("ADC PVDD FLT Switch", MAX98520_R20B2_ADC_PVDD0_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
0567 SOC_SINGLE("ADC TEMP FLT Switch", MAX98520_R20B3_ADC_THERMAL_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
0568 SOC_SINGLE("ADC PVDD MSB", MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0, 0xFF, 0),
0569 SOC_SINGLE("ADC PVDD LSB", MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0, 0x01, 0),
0570 SOC_SINGLE("ADC TEMP MSB", MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0, 0xFF, 0),
0571 SOC_SINGLE("ADC TEMP LSB", MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0, 0x01, 0),
0572 };
0573 
0574 static const struct snd_soc_dapm_route max98520_audio_map[] = {
0575     /* Plabyack */
0576     {"DAI Sel Mux", "Left", "Amp Enable"},
0577     {"DAI Sel Mux", "Right", "Amp Enable"},
0578     {"DAI Sel Mux", "LeftRight", "Amp Enable"},
0579     {"BE_OUT", NULL, "DAI Sel Mux"},
0580 };
0581 
0582 static struct snd_soc_dai_driver max98520_dai[] = {
0583     {
0584         .name = "max98520-aif1",
0585         .playback = {
0586             .stream_name = "HiFi Playback",
0587             .channels_min = 1,
0588             .channels_max = 2,
0589             .rates = MAX98520_RATES,
0590             .formats = MAX98520_FORMATS,
0591         },
0592         .ops = &max98520_dai_ops,
0593     }
0594 
0595 };
0596 
0597 static int max98520_probe(struct snd_soc_component *component)
0598 {
0599     struct max98520_priv *max98520 =
0600         snd_soc_component_get_drvdata(component);
0601 
0602     /* Software Reset */
0603     regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
0604 
0605     /* L/R mono mix configuration : "DAI Sel" for 0x2043 */
0606     regmap_write(max98520->regmap, MAX98520_R2043_PCM_RX_SRC1, 0x2);
0607 
0608     /* PCM input channles configuration : "Left Input Selection" for 0x2044 */
0609     /* PCM input channles configuration : "Right Input Selection" for 0x2044 */
0610     regmap_write(max98520->regmap, MAX98520_R2044_PCM_RX_SRC2, 0x10);
0611 
0612     /* Enable DC blocker */
0613     regmap_update_bits(max98520->regmap, MAX98520_R2092_AMP_DSP_CFG, 1, 1);
0614     /* Enable Clock Monitor Auto-restart */
0615     regmap_write(max98520->regmap, MAX98520_R2030_CLK_MON_CTRL, 0x1);
0616 
0617     /* set Rx Enable */
0618     regmap_update_bits(max98520->regmap,
0619                MAX98520_R204F_PCM_RX_EN,
0620                MAX98520_PCM_RX_EN_MASK,
0621                1);
0622 
0623     return 0;
0624 }
0625 
0626 static int __maybe_unused max98520_suspend(struct device *dev)
0627 {
0628     struct max98520_priv *max98520 = dev_get_drvdata(dev);
0629 
0630     regcache_cache_only(max98520->regmap, true);
0631     regcache_mark_dirty(max98520->regmap);
0632     return 0;
0633 }
0634 
0635 static int __maybe_unused max98520_resume(struct device *dev)
0636 {
0637     struct max98520_priv *max98520 = dev_get_drvdata(dev);
0638 
0639     regcache_cache_only(max98520->regmap, false);
0640     regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
0641     regcache_sync(max98520->regmap);
0642     return 0;
0643 }
0644 
0645 static const struct dev_pm_ops max98520_pm = {
0646     SET_SYSTEM_SLEEP_PM_OPS(max98520_suspend, max98520_resume)
0647 };
0648 
0649 static const struct snd_soc_component_driver soc_codec_dev_max98520 = {
0650     .probe          = max98520_probe,
0651     .controls       = max98520_snd_controls,
0652     .num_controls       = ARRAY_SIZE(max98520_snd_controls),
0653     .dapm_widgets       = max98520_dapm_widgets,
0654     .num_dapm_widgets   = ARRAY_SIZE(max98520_dapm_widgets),
0655     .dapm_routes        = max98520_audio_map,
0656     .num_dapm_routes    = ARRAY_SIZE(max98520_audio_map),
0657     .idle_bias_on       = 1,
0658     .use_pmdown_time    = 1,
0659     .endianness     = 1,
0660 };
0661 
0662 static const struct regmap_config max98520_regmap = {
0663     .reg_bits = 16,
0664     .val_bits = 8,
0665     .max_register = MAX98520_R21FF_REVISION_ID,
0666     .reg_defaults  = max98520_reg,
0667     .num_reg_defaults = ARRAY_SIZE(max98520_reg),
0668     .readable_reg = max98520_readable_register,
0669     .volatile_reg = max98520_volatile_reg,
0670     .cache_type = REGCACHE_RBTREE,
0671 };
0672 
0673 static void max98520_power_on(struct max98520_priv *max98520, bool poweron)
0674 {
0675     if (max98520->reset_gpio)
0676         gpiod_set_value_cansleep(max98520->reset_gpio, !poweron);
0677 }
0678 
0679 static int max98520_i2c_probe(struct i2c_client *i2c)
0680 {
0681     int ret;
0682     int reg = 0;
0683     struct max98520_priv *max98520;
0684     struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
0685 
0686     ret = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA);
0687     if (!ret) {
0688         dev_err(&i2c->dev, "I2C check functionality failed\n");
0689         return -ENXIO;
0690     }
0691 
0692     max98520 = devm_kzalloc(&i2c->dev, sizeof(*max98520), GFP_KERNEL);
0693 
0694     if (!max98520)
0695         return -ENOMEM;
0696 
0697     i2c_set_clientdata(i2c, max98520);
0698 
0699     /* regmap initialization */
0700     max98520->regmap = devm_regmap_init_i2c(i2c, &max98520_regmap);
0701     if (IS_ERR(max98520->regmap)) {
0702         ret = PTR_ERR(max98520->regmap);
0703         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
0704         return ret;
0705     }
0706 
0707     /* Power on device */
0708     max98520->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
0709     if (max98520->reset_gpio) {
0710         if (IS_ERR(max98520->reset_gpio)) {
0711             ret = PTR_ERR(max98520->reset_gpio);
0712             dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret);
0713             return ret;
0714         }
0715 
0716         max98520_power_on(max98520, 1);
0717     }
0718 
0719     /* Check Revision ID */
0720     ret = regmap_read(max98520->regmap, MAX98520_R21FF_REVISION_ID, &reg);
0721     if (ret < 0) {
0722         dev_err(&i2c->dev,
0723             "Failed to read: 0x%02X\n", MAX98520_R21FF_REVISION_ID);
0724         return ret;
0725     }
0726     dev_info(&i2c->dev, "MAX98520 revisionID: 0x%02X\n", reg);
0727 
0728     /* codec registration */
0729     ret = devm_snd_soc_register_component(&i2c->dev,
0730                           &soc_codec_dev_max98520,
0731                           max98520_dai, ARRAY_SIZE(max98520_dai));
0732     if (ret < 0)
0733         dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
0734 
0735     return ret;
0736 }
0737 
0738 static const struct i2c_device_id max98520_i2c_id[] = {
0739     { "max98520", 0},
0740     { },
0741 };
0742 
0743 MODULE_DEVICE_TABLE(i2c, max98520_i2c_id);
0744 
0745 #if defined(CONFIG_OF)
0746 static const struct of_device_id max98520_of_match[] = {
0747     { .compatible = "maxim,max98520", },
0748     { }
0749 };
0750 MODULE_DEVICE_TABLE(of, max98520_of_match);
0751 #endif
0752 
0753 static struct i2c_driver max98520_i2c_driver = {
0754     .driver = {
0755         .name = "max98520",
0756         .of_match_table = of_match_ptr(max98520_of_match),
0757         .pm = &max98520_pm,
0758     },
0759     .probe_new = max98520_i2c_probe,
0760     .id_table = max98520_i2c_id,
0761 };
0762 
0763 module_i2c_driver(max98520_i2c_driver)
0764 
0765 MODULE_DESCRIPTION("ALSA SoC MAX98520 driver");
0766 MODULE_AUTHOR("George Song <george.song@maximintegrated.com>");
0767 MODULE_LICENSE("GPL");
0768
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