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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * max98390.c  --  MAX98390 ALSA Soc Audio driver
0004  *
0005  * Copyright (C) 2020 Maxim Integrated Products
0006  *
0007  */
0008 
0009 #include <linux/acpi.h>
0010 #include <linux/cdev.h>
0011 #include <linux/dmi.h>
0012 #include <linux/firmware.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/i2c.h>
0015 #include <linux/module.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/regmap.h>
0018 #include <linux/slab.h>
0019 #include <linux/time.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/tlv.h>
0024 
0025 #include "max98390.h"
0026 
0027 static struct reg_default max98390_reg_defaults[] = {
0028     {MAX98390_INT_EN1, 0xf0},
0029     {MAX98390_INT_EN2, 0x00},
0030     {MAX98390_INT_EN3, 0x00},
0031     {MAX98390_INT_FLAG_CLR1, 0x00},
0032     {MAX98390_INT_FLAG_CLR2, 0x00},
0033     {MAX98390_INT_FLAG_CLR3, 0x00},
0034     {MAX98390_IRQ_CTRL, 0x01},
0035     {MAX98390_CLK_MON, 0x6d},
0036     {MAX98390_DAT_MON, 0x03},
0037     {MAX98390_WDOG_CTRL, 0x00},
0038     {MAX98390_WDOG_RST, 0x00},
0039     {MAX98390_MEAS_ADC_THERM_WARN_THRESH, 0x75},
0040     {MAX98390_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
0041     {MAX98390_MEAS_ADC_THERM_HYSTERESIS, 0x08},
0042     {MAX98390_PIN_CFG, 0x55},
0043     {MAX98390_PCM_RX_EN_A, 0x00},
0044     {MAX98390_PCM_RX_EN_B, 0x00},
0045     {MAX98390_PCM_TX_EN_A, 0x00},
0046     {MAX98390_PCM_TX_EN_B, 0x00},
0047     {MAX98390_PCM_TX_HIZ_CTRL_A, 0xff},
0048     {MAX98390_PCM_TX_HIZ_CTRL_B, 0xff},
0049     {MAX98390_PCM_CH_SRC_1, 0x00},
0050     {MAX98390_PCM_CH_SRC_2, 0x00},
0051     {MAX98390_PCM_CH_SRC_3, 0x00},
0052     {MAX98390_PCM_MODE_CFG, 0xc0},
0053     {MAX98390_PCM_MASTER_MODE, 0x1c},
0054     {MAX98390_PCM_CLK_SETUP, 0x44},
0055     {MAX98390_PCM_SR_SETUP, 0x08},
0056     {MAX98390_ICC_RX_EN_A, 0x00},
0057     {MAX98390_ICC_RX_EN_B, 0x00},
0058     {MAX98390_ICC_TX_EN_A, 0x00},
0059     {MAX98390_ICC_TX_EN_B, 0x00},
0060     {MAX98390_ICC_HIZ_MANUAL_MODE, 0x00},
0061     {MAX98390_ICC_TX_HIZ_EN_A, 0x00},
0062     {MAX98390_ICC_TX_HIZ_EN_B, 0x00},
0063     {MAX98390_ICC_LNK_EN, 0x00},
0064     {MAX98390_R2039_AMP_DSP_CFG, 0x0f},
0065     {MAX98390_R203A_AMP_EN, 0x81},
0066     {MAX98390_TONE_GEN_DC_CFG, 0x00},
0067     {MAX98390_SPK_SRC_SEL, 0x00},
0068     {MAX98390_SSM_CFG, 0x85},
0069     {MAX98390_MEAS_EN, 0x03},
0070     {MAX98390_MEAS_DSP_CFG, 0x0f},
0071     {MAX98390_BOOST_CTRL0, 0x1c},
0072     {MAX98390_BOOST_CTRL3, 0x01},
0073     {MAX98390_BOOST_CTRL1, 0x40},
0074     {MAX98390_MEAS_ADC_CFG, 0x07},
0075     {MAX98390_MEAS_ADC_BASE_MSB, 0x00},
0076     {MAX98390_MEAS_ADC_BASE_LSB, 0x23},
0077     {MAX98390_ADC_CH0_DIVIDE, 0x00},
0078     {MAX98390_ADC_CH1_DIVIDE, 0x00},
0079     {MAX98390_ADC_CH2_DIVIDE, 0x00},
0080     {MAX98390_ADC_CH0_FILT_CFG, 0x00},
0081     {MAX98390_ADC_CH1_FILT_CFG, 0x00},
0082     {MAX98390_ADC_CH2_FILT_CFG, 0x00},
0083     {MAX98390_PWR_GATE_CTL, 0x2c},
0084     {MAX98390_BROWNOUT_EN, 0x00},
0085     {MAX98390_BROWNOUT_INFINITE_HOLD, 0x00},
0086     {MAX98390_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
0087     {MAX98390_BROWNOUT_LVL_HOLD, 0x00},
0088     {MAX98390_BROWNOUT_LVL1_THRESH, 0x00},
0089     {MAX98390_BROWNOUT_LVL2_THRESH, 0x00},
0090     {MAX98390_BROWNOUT_LVL3_THRESH, 0x00},
0091     {MAX98390_BROWNOUT_LVL4_THRESH, 0x00},
0092     {MAX98390_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
0093     {MAX98390_BROWNOUT_AMP_LIMITER_ATK_REL, 0x1f},
0094     {MAX98390_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
0095     {MAX98390_BROWNOUT_AMP1_CLIP_MODE, 0x00},
0096     {MAX98390_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
0097     {MAX98390_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
0098     {MAX98390_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
0099     {MAX98390_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
0100     {MAX98390_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
0101     {MAX98390_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
0102     {MAX98390_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
0103     {MAX98390_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
0104     {MAX98390_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
0105     {MAX98390_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
0106     {MAX98390_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
0107     {MAX98390_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
0108     {MAX98390_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
0109     {MAX98390_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
0110     {MAX98390_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
0111     {MAX98390_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
0112     {MAX98390_BROWNOUT_ILIM_HLD, 0x00},
0113     {MAX98390_BROWNOUT_LIM_HLD, 0x00},
0114     {MAX98390_BROWNOUT_CLIP_HLD, 0x00},
0115     {MAX98390_BROWNOUT_GAIN_HLD, 0x00},
0116     {MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0f},
0117     {MAX98390_ENV_TRACK_BOOST_VOUT_DELAY, 0x80},
0118     {MAX98390_ENV_TRACK_REL_RATE, 0x07},
0119     {MAX98390_ENV_TRACK_HOLD_RATE, 0x07},
0120     {MAX98390_ENV_TRACK_CTRL, 0x01},
0121     {MAX98390_BOOST_BYPASS1, 0x49},
0122     {MAX98390_BOOST_BYPASS2, 0x2b},
0123     {MAX98390_BOOST_BYPASS3, 0x08},
0124     {MAX98390_FET_SCALING1, 0x00},
0125     {MAX98390_FET_SCALING2, 0x03},
0126     {MAX98390_FET_SCALING3, 0x00},
0127     {MAX98390_FET_SCALING4, 0x07},
0128     {MAX98390_SPK_SPEEDUP, 0x00},
0129     {DSMIG_WB_DRC_RELEASE_TIME_1, 0x00},
0130     {DSMIG_WB_DRC_RELEASE_TIME_2, 0x00},
0131     {DSMIG_WB_DRC_ATTACK_TIME_1, 0x00},
0132     {DSMIG_WB_DRC_ATTACK_TIME_2, 0x00},
0133     {DSMIG_WB_DRC_COMPRESSION_RATIO, 0x00},
0134     {DSMIG_WB_DRC_COMPRESSION_THRESHOLD, 0x00},
0135     {DSMIG_WB_DRC_MAKEUPGAIN, 0x00},
0136     {DSMIG_WB_DRC_NOISE_GATE_THRESHOLD, 0x00},
0137     {DSMIG_WBDRC_HPF_ENABLE, 0x00},
0138     {DSMIG_WB_DRC_TEST_SMOOTHER_OUT_EN, 0x00},
0139     {DSMIG_PPR_THRESHOLD, 0x00},
0140     {DSM_STEREO_BASS_CHANNEL_SELECT, 0x00},
0141     {DSM_TPROT_THRESHOLD_BYTE0, 0x00},
0142     {DSM_TPROT_THRESHOLD_BYTE1, 0x00},
0143     {DSM_TPROT_ROOM_TEMPERATURE_BYTE0, 0x00},
0144     {DSM_TPROT_ROOM_TEMPERATURE_BYTE1, 0x00},
0145     {DSM_TPROT_RECIP_RDC_ROOM_BYTE0, 0x00},
0146     {DSM_TPROT_RECIP_RDC_ROOM_BYTE1, 0x00},
0147     {DSM_TPROT_RECIP_RDC_ROOM_BYTE2, 0x00},
0148     {DSM_TPROT_RECIP_TCONST_BYTE0, 0x00},
0149     {DSM_TPROT_RECIP_TCONST_BYTE1, 0x00},
0150     {DSM_TPROT_RECIP_TCONST_BYTE2, 0x00},
0151     {DSM_THERMAL_ATTENUATION_SETTINGS, 0x00},
0152     {DSM_THERMAL_PILOT_TONE_ATTENUATION, 0x00},
0153     {DSM_TPROT_PG_TEMP_THRESH_BYTE0, 0x00},
0154     {DSM_TPROT_PG_TEMP_THRESH_BYTE1, 0x00},
0155     {DSMIG_DEBUZZER_THRESHOLD, 0x00},
0156     {DSMIG_DEBUZZER_ALPHA_COEF_TEST_ONLY, 0x08},
0157     {DSM_VOL_ENA, 0x20},
0158     {DSM_VOL_CTRL, 0xa0},
0159     {DSMIG_EN, 0x00},
0160     {MAX98390_R23E1_DSP_GLOBAL_EN, 0x00},
0161     {MAX98390_R23FF_GLOBAL_EN, 0x00},
0162 };
0163 
0164 static int max98390_dsm_calibrate(struct snd_soc_component *component);
0165 
0166 static int max98390_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0167 {
0168     struct snd_soc_component *component = codec_dai->component;
0169     struct max98390_priv *max98390 =
0170         snd_soc_component_get_drvdata(component);
0171     unsigned int mode;
0172     unsigned int format;
0173     unsigned int invert = 0;
0174 
0175     dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
0176 
0177     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0178     case SND_SOC_DAIFMT_CBC_CFC:
0179         mode = MAX98390_PCM_MASTER_MODE_SLAVE;
0180         break;
0181     case SND_SOC_DAIFMT_CBP_CFP:
0182         max98390->provider = true;
0183         mode = MAX98390_PCM_MASTER_MODE_MASTER;
0184         break;
0185     default:
0186         dev_err(component->dev, "DAI clock mode unsupported\n");
0187         return -EINVAL;
0188     }
0189 
0190     regmap_update_bits(max98390->regmap,
0191         MAX98390_PCM_MASTER_MODE,
0192         MAX98390_PCM_MASTER_MODE_MASK,
0193         mode);
0194 
0195     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0196     case SND_SOC_DAIFMT_NB_NF:
0197         break;
0198     case SND_SOC_DAIFMT_IB_NF:
0199         invert = MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE;
0200         break;
0201     default:
0202         dev_err(component->dev, "DAI invert mode unsupported\n");
0203         return -EINVAL;
0204     }
0205 
0206     regmap_update_bits(max98390->regmap,
0207         MAX98390_PCM_MODE_CFG,
0208         MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE,
0209         invert);
0210 
0211     /* interface format */
0212     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0213     case SND_SOC_DAIFMT_I2S:
0214         format = MAX98390_PCM_FORMAT_I2S;
0215         break;
0216     case SND_SOC_DAIFMT_LEFT_J:
0217         format = MAX98390_PCM_FORMAT_LJ;
0218         break;
0219     case SND_SOC_DAIFMT_DSP_A:
0220         format = MAX98390_PCM_FORMAT_TDM_MODE1;
0221         break;
0222     case SND_SOC_DAIFMT_DSP_B:
0223         format = MAX98390_PCM_FORMAT_TDM_MODE0;
0224         break;
0225     default:
0226         return -EINVAL;
0227     }
0228 
0229     regmap_update_bits(max98390->regmap,
0230         MAX98390_PCM_MODE_CFG,
0231         MAX98390_PCM_MODE_CFG_FORMAT_MASK,
0232         format << MAX98390_PCM_MODE_CFG_FORMAT_SHIFT);
0233 
0234     return 0;
0235 }
0236 
0237 static int max98390_get_bclk_sel(int bclk)
0238 {
0239     int i;
0240     /* BCLKs per LRCLK */
0241     static int bclk_sel_table[] = {
0242         32, 48, 64, 96, 128, 192, 256, 320, 384, 512,
0243     };
0244     /* match BCLKs per LRCLK */
0245     for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
0246         if (bclk_sel_table[i] == bclk)
0247             return i + 2;
0248     }
0249     return 0;
0250 }
0251 
0252 static int max98390_set_clock(struct snd_soc_component *component,
0253         struct snd_pcm_hw_params *params)
0254 {
0255     struct max98390_priv *max98390 =
0256         snd_soc_component_get_drvdata(component);
0257     /* codec MCLK rate in master mode */
0258     static int rate_table[] = {
0259         5644800, 6000000, 6144000, 6500000,
0260         9600000, 11289600, 12000000, 12288000,
0261         13000000, 19200000,
0262     };
0263     /* BCLK/LRCLK ratio calculation */
0264     int blr_clk_ratio = params_channels(params)
0265         * snd_pcm_format_width(params_format(params));
0266     int value;
0267 
0268     if (max98390->provider) {
0269         int i;
0270         /* match rate to closest value */
0271         for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
0272             if (rate_table[i] >= max98390->sysclk)
0273                 break;
0274         }
0275         if (i == ARRAY_SIZE(rate_table)) {
0276             dev_err(component->dev, "failed to find proper clock rate.\n");
0277             return -EINVAL;
0278         }
0279 
0280         regmap_update_bits(max98390->regmap,
0281             MAX98390_PCM_MASTER_MODE,
0282             MAX98390_PCM_MASTER_MODE_MCLK_MASK,
0283             i << MAX98390_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
0284     }
0285 
0286     if (!max98390->tdm_mode) {
0287         /* BCLK configuration */
0288         value = max98390_get_bclk_sel(blr_clk_ratio);
0289         if (!value) {
0290             dev_err(component->dev, "format unsupported %d\n",
0291                 params_format(params));
0292             return -EINVAL;
0293         }
0294 
0295         regmap_update_bits(max98390->regmap,
0296             MAX98390_PCM_CLK_SETUP,
0297             MAX98390_PCM_CLK_SETUP_BSEL_MASK,
0298             value);
0299     }
0300     return 0;
0301 }
0302 
0303 static int max98390_dai_hw_params(struct snd_pcm_substream *substream,
0304         struct snd_pcm_hw_params *params,
0305         struct snd_soc_dai *dai)
0306 {
0307     struct snd_soc_component *component =
0308         dai->component;
0309     struct max98390_priv *max98390 =
0310         snd_soc_component_get_drvdata(component);
0311 
0312     unsigned int sampling_rate;
0313     unsigned int chan_sz;
0314 
0315     /* pcm mode configuration */
0316     switch (snd_pcm_format_width(params_format(params))) {
0317     case 16:
0318         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
0319         break;
0320     case 24:
0321         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
0322         break;
0323     case 32:
0324         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
0325         break;
0326     default:
0327         dev_err(component->dev, "format unsupported %d\n",
0328             params_format(params));
0329         goto err;
0330     }
0331 
0332     regmap_update_bits(max98390->regmap,
0333         MAX98390_PCM_MODE_CFG,
0334         MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0335 
0336     dev_dbg(component->dev, "format supported %d",
0337         params_format(params));
0338 
0339     /* sampling rate configuration */
0340     switch (params_rate(params)) {
0341     case 8000:
0342         sampling_rate = MAX98390_PCM_SR_SET1_SR_8000;
0343         break;
0344     case 11025:
0345         sampling_rate = MAX98390_PCM_SR_SET1_SR_11025;
0346         break;
0347     case 12000:
0348         sampling_rate = MAX98390_PCM_SR_SET1_SR_12000;
0349         break;
0350     case 16000:
0351         sampling_rate = MAX98390_PCM_SR_SET1_SR_16000;
0352         break;
0353     case 22050:
0354         sampling_rate = MAX98390_PCM_SR_SET1_SR_22050;
0355         break;
0356     case 24000:
0357         sampling_rate = MAX98390_PCM_SR_SET1_SR_24000;
0358         break;
0359     case 32000:
0360         sampling_rate = MAX98390_PCM_SR_SET1_SR_32000;
0361         break;
0362     case 44100:
0363         sampling_rate = MAX98390_PCM_SR_SET1_SR_44100;
0364         break;
0365     case 48000:
0366         sampling_rate = MAX98390_PCM_SR_SET1_SR_48000;
0367         break;
0368     default:
0369         dev_err(component->dev, "rate %d not supported\n",
0370             params_rate(params));
0371         goto err;
0372     }
0373 
0374     /* set DAI_SR to correct LRCLK frequency */
0375     regmap_update_bits(max98390->regmap,
0376         MAX98390_PCM_SR_SETUP,
0377         MAX98390_PCM_SR_SET1_SR_MASK,
0378         sampling_rate);
0379 
0380     return max98390_set_clock(component, params);
0381 err:
0382     return -EINVAL;
0383 }
0384 
0385 static int max98390_dai_tdm_slot(struct snd_soc_dai *dai,
0386         unsigned int tx_mask, unsigned int rx_mask,
0387         int slots, int slot_width)
0388 {
0389     struct snd_soc_component *component = dai->component;
0390     struct max98390_priv *max98390 =
0391         snd_soc_component_get_drvdata(component);
0392 
0393     int bsel;
0394     unsigned int chan_sz;
0395 
0396     if (!tx_mask && !rx_mask && !slots && !slot_width)
0397         max98390->tdm_mode = false;
0398     else
0399         max98390->tdm_mode = true;
0400 
0401     dev_dbg(component->dev,
0402         "Tdm mode : %d\n", max98390->tdm_mode);
0403 
0404     /* BCLK configuration */
0405     bsel = max98390_get_bclk_sel(slots * slot_width);
0406     if (!bsel) {
0407         dev_err(component->dev, "BCLK %d not supported\n",
0408             slots * slot_width);
0409         return -EINVAL;
0410     }
0411 
0412     regmap_update_bits(max98390->regmap,
0413         MAX98390_PCM_CLK_SETUP,
0414         MAX98390_PCM_CLK_SETUP_BSEL_MASK,
0415         bsel);
0416 
0417     /* Channel size configuration */
0418     switch (slot_width) {
0419     case 16:
0420         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
0421         break;
0422     case 24:
0423         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
0424         break;
0425     case 32:
0426         chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
0427         break;
0428     default:
0429         dev_err(component->dev, "format unsupported %d\n",
0430             slot_width);
0431         return -EINVAL;
0432     }
0433 
0434     regmap_update_bits(max98390->regmap,
0435         MAX98390_PCM_MODE_CFG,
0436         MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0437 
0438     /* Rx slot configuration */
0439     regmap_write(max98390->regmap,
0440         MAX98390_PCM_RX_EN_A,
0441         rx_mask & 0xFF);
0442     regmap_write(max98390->regmap,
0443         MAX98390_PCM_RX_EN_B,
0444         (rx_mask & 0xFF00) >> 8);
0445 
0446     /* Tx slot Hi-Z configuration */
0447     regmap_write(max98390->regmap,
0448         MAX98390_PCM_TX_HIZ_CTRL_A,
0449         ~tx_mask & 0xFF);
0450     regmap_write(max98390->regmap,
0451         MAX98390_PCM_TX_HIZ_CTRL_B,
0452         (~tx_mask & 0xFF00) >> 8);
0453 
0454     return 0;
0455 }
0456 
0457 static int max98390_dai_set_sysclk(struct snd_soc_dai *dai,
0458         int clk_id, unsigned int freq, int dir)
0459 {
0460     struct snd_soc_component *component = dai->component;
0461     struct max98390_priv *max98390 =
0462         snd_soc_component_get_drvdata(component);
0463 
0464     max98390->sysclk = freq;
0465     return 0;
0466 }
0467 
0468 static const struct snd_soc_dai_ops max98390_dai_ops = {
0469     .set_sysclk = max98390_dai_set_sysclk,
0470     .set_fmt = max98390_dai_set_fmt,
0471     .hw_params = max98390_dai_hw_params,
0472     .set_tdm_slot = max98390_dai_tdm_slot,
0473 };
0474 
0475 static int max98390_dac_event(struct snd_soc_dapm_widget *w,
0476         struct snd_kcontrol *kcontrol, int event)
0477 {
0478     struct snd_soc_component *component =
0479         snd_soc_dapm_to_component(w->dapm);
0480     struct max98390_priv *max98390 =
0481         snd_soc_component_get_drvdata(component);
0482 
0483     switch (event) {
0484     case SND_SOC_DAPM_POST_PMU:
0485         regmap_update_bits(max98390->regmap,
0486             MAX98390_R203A_AMP_EN,
0487             MAX98390_AMP_EN_MASK, 1);
0488         regmap_update_bits(max98390->regmap,
0489             MAX98390_R23FF_GLOBAL_EN,
0490             MAX98390_GLOBAL_EN_MASK, 1);
0491         break;
0492     case SND_SOC_DAPM_POST_PMD:
0493         regmap_update_bits(max98390->regmap,
0494             MAX98390_R23FF_GLOBAL_EN,
0495             MAX98390_GLOBAL_EN_MASK, 0);
0496         regmap_update_bits(max98390->regmap,
0497             MAX98390_R203A_AMP_EN,
0498             MAX98390_AMP_EN_MASK, 0);
0499         break;
0500     }
0501     return 0;
0502 }
0503 
0504 static const char * const max98390_switch_text[] = {
0505     "Left", "Right", "LeftRight"};
0506 
0507 static const char * const max98390_boost_voltage_text[] = {
0508     "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
0509     "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
0510     "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
0511     "9.5V", "9.625V", "9.75V", "9.875V", "10V"
0512 };
0513 
0514 static SOC_ENUM_SINGLE_DECL(max98390_boost_voltage,
0515         MAX98390_BOOST_CTRL0, 0,
0516         max98390_boost_voltage_text);
0517 
0518 static DECLARE_TLV_DB_SCALE(max98390_spk_tlv, 300, 300, 0);
0519 static DECLARE_TLV_DB_SCALE(max98390_digital_tlv, -8000, 50, 0);
0520 
0521 static const char * const max98390_current_limit_text[] = {
0522     "0.00A", "0.50A", "1.00A", "1.05A", "1.10A", "1.15A", "1.20A", "1.25A",
0523     "1.30A", "1.35A", "1.40A", "1.45A", "1.50A", "1.55A", "1.60A", "1.65A",
0524     "1.70A", "1.75A", "1.80A", "1.85A", "1.90A", "1.95A", "2.00A", "2.05A",
0525     "2.10A", "2.15A", "2.20A", "2.25A", "2.30A", "2.35A", "2.40A", "2.45A",
0526     "2.50A", "2.55A", "2.60A", "2.65A", "2.70A", "2.75A", "2.80A", "2.85A",
0527     "2.90A", "2.95A", "3.00A", "3.05A", "3.10A", "3.15A", "3.20A", "3.25A",
0528     "3.30A", "3.35A", "3.40A", "3.45A", "3.50A", "3.55A", "3.60A", "3.65A",
0529     "3.70A", "3.75A", "3.80A", "3.85A", "3.90A", "3.95A", "4.00A", "4.05A",
0530     "4.10A"
0531 };
0532 
0533 static SOC_ENUM_SINGLE_DECL(max98390_current_limit,
0534         MAX98390_BOOST_CTRL1, 0,
0535         max98390_current_limit_text);
0536 
0537 static int max98390_ref_rdc_put(struct snd_kcontrol *kcontrol,
0538         struct snd_ctl_elem_value *ucontrol)
0539 {
0540     struct snd_soc_component *component =
0541         snd_soc_kcontrol_component(kcontrol);
0542     struct max98390_priv *max98390 =
0543         snd_soc_component_get_drvdata(component);
0544 
0545     max98390->ref_rdc_value = ucontrol->value.integer.value[0];
0546 
0547     regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
0548         max98390->ref_rdc_value & 0x000000ff);
0549     regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
0550         (max98390->ref_rdc_value >> 8) & 0x000000ff);
0551     regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
0552         (max98390->ref_rdc_value >> 16) & 0x000000ff);
0553 
0554     return 0;
0555 }
0556 
0557 static int max98390_ref_rdc_get(struct snd_kcontrol *kcontrol,
0558         struct snd_ctl_elem_value *ucontrol)
0559 {
0560     struct snd_soc_component *component =
0561         snd_soc_kcontrol_component(kcontrol);
0562     struct max98390_priv *max98390 =
0563         snd_soc_component_get_drvdata(component);
0564 
0565     ucontrol->value.integer.value[0] = max98390->ref_rdc_value;
0566 
0567     return 0;
0568 }
0569 
0570 static int max98390_ambient_temp_put(struct snd_kcontrol *kcontrol,
0571         struct snd_ctl_elem_value *ucontrol)
0572 {
0573     struct snd_soc_component *component =
0574         snd_soc_kcontrol_component(kcontrol);
0575     struct max98390_priv *max98390 =
0576         snd_soc_component_get_drvdata(component);
0577 
0578     max98390->ambient_temp_value = ucontrol->value.integer.value[0];
0579 
0580     regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
0581         (max98390->ambient_temp_value >> 8) & 0x000000ff);
0582     regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
0583         (max98390->ambient_temp_value) & 0x000000ff);
0584 
0585     return 0;
0586 }
0587 
0588 static int max98390_ambient_temp_get(struct snd_kcontrol *kcontrol,
0589         struct snd_ctl_elem_value *ucontrol)
0590 {
0591     struct snd_soc_component *component =
0592         snd_soc_kcontrol_component(kcontrol);
0593     struct max98390_priv *max98390 =
0594         snd_soc_component_get_drvdata(component);
0595 
0596     ucontrol->value.integer.value[0] = max98390->ambient_temp_value;
0597 
0598     return 0;
0599 }
0600 
0601 static int max98390_adaptive_rdc_put(struct snd_kcontrol *kcontrol,
0602         struct snd_ctl_elem_value *ucontrol)
0603 {
0604     struct snd_soc_component *component =
0605         snd_soc_kcontrol_component(kcontrol);
0606 
0607     dev_warn(component->dev, "Put adaptive rdc not supported\n");
0608 
0609     return 0;
0610 }
0611 
0612 static int max98390_adaptive_rdc_get(struct snd_kcontrol *kcontrol,
0613         struct snd_ctl_elem_value *ucontrol)
0614 {
0615     int rdc, rdc0;
0616     struct snd_soc_component *component =
0617         snd_soc_kcontrol_component(kcontrol);
0618     struct max98390_priv *max98390 =
0619         snd_soc_component_get_drvdata(component);
0620 
0621     regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
0622     regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc0);
0623     ucontrol->value.integer.value[0] = rdc0 | rdc << 8;
0624 
0625     return 0;
0626 }
0627 
0628 static int max98390_dsm_calib_get(struct snd_kcontrol *kcontrol,
0629         struct snd_ctl_elem_value *ucontrol)
0630 {
0631     /* Do nothing */
0632     return 0;
0633 }
0634 
0635 static int max98390_dsm_calib_put(struct snd_kcontrol *kcontrol,
0636         struct snd_ctl_elem_value *ucontrol)
0637 {
0638     struct snd_soc_component *component =
0639         snd_soc_kcontrol_component(kcontrol);
0640 
0641     max98390_dsm_calibrate(component);
0642 
0643     return 0;
0644 }
0645 
0646 static const struct snd_kcontrol_new max98390_snd_controls[] = {
0647     SOC_SINGLE_TLV("Digital Volume", DSM_VOL_CTRL,
0648         0, 184, 0,
0649         max98390_digital_tlv),
0650     SOC_SINGLE_TLV("Speaker Volume", MAX98390_R203D_SPK_GAIN,
0651         0, 6, 0,
0652         max98390_spk_tlv),
0653     SOC_SINGLE("Ramp Up Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
0654         MAX98390_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
0655     SOC_SINGLE("Ramp Down Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
0656         MAX98390_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
0657     SOC_SINGLE("Boost Clock Phase", MAX98390_BOOST_CTRL3,
0658         MAX98390_BOOST_CLK_PHASE_CFG_SHIFT, 3, 0),
0659     SOC_ENUM("Boost Output Voltage", max98390_boost_voltage),
0660     SOC_ENUM("Current Limit", max98390_current_limit),
0661     SOC_SINGLE_EXT("DSM Rdc", SND_SOC_NOPM, 0, 0xffffff, 0,
0662         max98390_ref_rdc_get, max98390_ref_rdc_put),
0663     SOC_SINGLE_EXT("DSM Ambient Temp", SND_SOC_NOPM, 0, 0xffff, 0,
0664         max98390_ambient_temp_get, max98390_ambient_temp_put),
0665     SOC_SINGLE_EXT("DSM Adaptive Rdc", SND_SOC_NOPM, 0, 0xffff, 0,
0666         max98390_adaptive_rdc_get, max98390_adaptive_rdc_put),
0667     SOC_SINGLE_EXT("DSM Calibration", SND_SOC_NOPM, 0, 1, 0,
0668         max98390_dsm_calib_get, max98390_dsm_calib_put),
0669 };
0670 
0671 static const struct soc_enum dai_sel_enum =
0672     SOC_ENUM_SINGLE(MAX98390_PCM_CH_SRC_1,
0673         MAX98390_PCM_RX_CH_SRC_SHIFT,
0674         3, max98390_switch_text);
0675 
0676 static const struct snd_kcontrol_new max98390_dai_controls =
0677     SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
0678 
0679 static const struct snd_soc_dapm_widget max98390_dapm_widgets[] = {
0680     SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
0681         SND_SOC_NOPM, 0, 0, max98390_dac_event,
0682         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0683     SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
0684         &max98390_dai_controls),
0685     SND_SOC_DAPM_OUTPUT("BE_OUT"),
0686 };
0687 
0688 static const struct snd_soc_dapm_route max98390_audio_map[] = {
0689     /* Plabyack */
0690     {"DAI Sel Mux", "Left", "Amp Enable"},
0691     {"DAI Sel Mux", "Right", "Amp Enable"},
0692     {"DAI Sel Mux", "LeftRight", "Amp Enable"},
0693     {"BE_OUT", NULL, "DAI Sel Mux"},
0694 };
0695 
0696 static bool max98390_readable_register(struct device *dev, unsigned int reg)
0697 {
0698     switch (reg) {
0699     case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
0700     case MAX98390_IRQ_CTRL ... MAX98390_WDOG_CTRL:
0701     case MAX98390_MEAS_ADC_THERM_WARN_THRESH
0702         ... MAX98390_BROWNOUT_INFINITE_HOLD:
0703     case MAX98390_BROWNOUT_LVL_HOLD ... DSMIG_DEBUZZER_THRESHOLD:
0704     case DSM_VOL_ENA ... MAX98390_R24FF_REV_ID:
0705         return true;
0706     default:
0707         return false;
0708     }
0709 };
0710 
0711 static bool max98390_volatile_reg(struct device *dev, unsigned int reg)
0712 {
0713     switch (reg) {
0714     case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
0715     case MAX98390_MEAS_ADC_CH0_READ ... MAX98390_MEAS_ADC_CH2_READ:
0716     case MAX98390_PWR_GATE_STATUS ... MAX98390_BROWNOUT_STATUS:
0717     case MAX98390_BROWNOUT_LOWEST_STATUS:
0718     case MAX98390_ENV_TRACK_BOOST_VOUT_READ:
0719     case DSM_STBASS_HPF_B0_BYTE0 ... DSM_DEBUZZER_ATTACK_TIME_BYTE2:
0720     case THERMAL_RDC_RD_BACK_BYTE1 ... DSMIG_DEBUZZER_THRESHOLD:
0721     case DSM_THERMAL_GAIN ... DSM_WBDRC_GAIN:
0722         return true;
0723     default:
0724         return false;
0725     }
0726 }
0727 
0728 #define MAX98390_RATES SNDRV_PCM_RATE_8000_48000
0729 
0730 #define MAX98390_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0731     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0732 
0733 static struct snd_soc_dai_driver max98390_dai[] = {
0734     {
0735         .name = "max98390-aif1",
0736         .playback = {
0737             .stream_name = "HiFi Playback",
0738             .channels_min = 1,
0739             .channels_max = 2,
0740             .rates = MAX98390_RATES,
0741             .formats = MAX98390_FORMATS,
0742         },
0743         .capture = {
0744             .stream_name = "HiFi Capture",
0745             .channels_min = 1,
0746             .channels_max = 2,
0747             .rates = MAX98390_RATES,
0748             .formats = MAX98390_FORMATS,
0749         },
0750         .ops = &max98390_dai_ops,
0751     }
0752 };
0753 
0754 static int max98390_dsm_init(struct snd_soc_component *component)
0755 {
0756     int ret;
0757     int param_size, param_start_addr;
0758     char filename[128];
0759     const char *vendor, *product;
0760     struct max98390_priv *max98390 =
0761         snd_soc_component_get_drvdata(component);
0762     const struct firmware *fw;
0763     char *dsm_param;
0764 
0765     vendor = dmi_get_system_info(DMI_SYS_VENDOR);
0766     product = dmi_get_system_info(DMI_PRODUCT_NAME);
0767 
0768     if (!strcmp(max98390->dsm_param_name, "default")) {
0769         if (vendor && product) {
0770             snprintf(filename, sizeof(filename),
0771                 "dsm_param_%s_%s.bin", vendor, product);
0772         } else {
0773             sprintf(filename, "dsm_param.bin");
0774         }
0775     } else {
0776         snprintf(filename, sizeof(filename), "%s",
0777             max98390->dsm_param_name);
0778     }
0779     ret = request_firmware(&fw, filename, component->dev);
0780     if (ret) {
0781         ret = request_firmware(&fw, "dsm_param.bin", component->dev);
0782         if (ret) {
0783             ret = request_firmware(&fw, "dsmparam.bin",
0784                 component->dev);
0785             if (ret)
0786                 goto err;
0787         }
0788     }
0789 
0790     dev_dbg(component->dev,
0791         "max98390: param fw size %zd\n",
0792         fw->size);
0793     if (fw->size < MAX98390_DSM_PARAM_MIN_SIZE) {
0794         dev_err(component->dev,
0795             "param fw is invalid.\n");
0796         ret = -EINVAL;
0797         goto err_alloc;
0798     }
0799     dsm_param = (char *)fw->data;
0800     param_start_addr = (dsm_param[0] & 0xff) | (dsm_param[1] & 0xff) << 8;
0801     param_size = (dsm_param[2] & 0xff) | (dsm_param[3] & 0xff) << 8;
0802     if (param_size > MAX98390_DSM_PARAM_MAX_SIZE ||
0803         param_start_addr < MAX98390_IRQ_CTRL ||
0804         fw->size < param_size + MAX98390_DSM_PAYLOAD_OFFSET) {
0805         dev_err(component->dev,
0806             "param fw is invalid.\n");
0807         ret = -EINVAL;
0808         goto err_alloc;
0809     }
0810     regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
0811     dsm_param += MAX98390_DSM_PAYLOAD_OFFSET;
0812     regmap_bulk_write(max98390->regmap, param_start_addr,
0813         dsm_param, param_size);
0814     regmap_write(max98390->regmap, MAX98390_R23E1_DSP_GLOBAL_EN, 0x01);
0815 
0816 err_alloc:
0817     release_firmware(fw);
0818 err:
0819     return ret;
0820 }
0821 
0822 static int max98390_dsm_calibrate(struct snd_soc_component *component)
0823 {
0824     unsigned int rdc, rdc_cal_result, temp;
0825     unsigned int rdc_integer, rdc_factor;
0826     struct max98390_priv *max98390 =
0827         snd_soc_component_get_drvdata(component);
0828 
0829     regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x81);
0830     regmap_write(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, 0x01);
0831 
0832     regmap_read(max98390->regmap,
0833         THERMAL_RDC_RD_BACK_BYTE1, &rdc);
0834     regmap_read(max98390->regmap,
0835         THERMAL_RDC_RD_BACK_BYTE0, &rdc_cal_result);
0836     rdc_cal_result |= (rdc << 8) & 0x0000FFFF;
0837     if (rdc_cal_result)
0838         max98390->ref_rdc_value = 268435456U / rdc_cal_result;
0839 
0840     regmap_read(max98390->regmap, MAX98390_MEAS_ADC_CH2_READ, &temp);
0841     max98390->ambient_temp_value = temp * 52 - 1188;
0842 
0843     rdc_integer =  rdc_cal_result * 937  / 65536;
0844     rdc_factor = ((rdc_cal_result * 937 * 100) / 65536)
0845                     - (rdc_integer * 100);
0846 
0847     dev_info(component->dev, "rdc resistance about %d.%02d ohm, reg=0x%X temp reg=0x%X\n",
0848          rdc_integer, rdc_factor, rdc_cal_result, temp);
0849 
0850     regmap_write(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, 0x00);
0851     regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
0852 
0853     return 0;
0854 }
0855 
0856 static void max98390_init_regs(struct snd_soc_component *component)
0857 {
0858     struct max98390_priv *max98390 =
0859         snd_soc_component_get_drvdata(component);
0860 
0861     regmap_write(max98390->regmap, MAX98390_CLK_MON, 0x6f);
0862     regmap_write(max98390->regmap, MAX98390_DAT_MON, 0x00);
0863     regmap_write(max98390->regmap, MAX98390_PWR_GATE_CTL, 0x00);
0864     regmap_write(max98390->regmap, MAX98390_PCM_RX_EN_A, 0x03);
0865     regmap_write(max98390->regmap, MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0e);
0866     regmap_write(max98390->regmap, MAX98390_BOOST_BYPASS1, 0x46);
0867     regmap_write(max98390->regmap, MAX98390_FET_SCALING3, 0x03);
0868 
0869     /* voltage, current slot configuration */
0870     regmap_write(max98390->regmap,
0871         MAX98390_PCM_CH_SRC_2,
0872         (max98390->i_l_slot << 4 |
0873         max98390->v_l_slot)&0xFF);
0874 
0875     if (max98390->v_l_slot < 8) {
0876         regmap_update_bits(max98390->regmap,
0877             MAX98390_PCM_TX_HIZ_CTRL_A,
0878             1 << max98390->v_l_slot, 0);
0879         regmap_update_bits(max98390->regmap,
0880             MAX98390_PCM_TX_EN_A,
0881             1 << max98390->v_l_slot,
0882             1 << max98390->v_l_slot);
0883     } else {
0884         regmap_update_bits(max98390->regmap,
0885             MAX98390_PCM_TX_HIZ_CTRL_B,
0886             1 << (max98390->v_l_slot - 8), 0);
0887         regmap_update_bits(max98390->regmap,
0888             MAX98390_PCM_TX_EN_B,
0889             1 << (max98390->v_l_slot - 8),
0890             1 << (max98390->v_l_slot - 8));
0891     }
0892 
0893     if (max98390->i_l_slot < 8) {
0894         regmap_update_bits(max98390->regmap,
0895             MAX98390_PCM_TX_HIZ_CTRL_A,
0896             1 << max98390->i_l_slot, 0);
0897         regmap_update_bits(max98390->regmap,
0898             MAX98390_PCM_TX_EN_A,
0899             1 << max98390->i_l_slot,
0900             1 << max98390->i_l_slot);
0901     } else {
0902         regmap_update_bits(max98390->regmap,
0903             MAX98390_PCM_TX_HIZ_CTRL_B,
0904             1 << (max98390->i_l_slot - 8), 0);
0905         regmap_update_bits(max98390->regmap,
0906             MAX98390_PCM_TX_EN_B,
0907             1 << (max98390->i_l_slot - 8),
0908             1 << (max98390->i_l_slot - 8));
0909     }
0910 }
0911 
0912 static int max98390_probe(struct snd_soc_component *component)
0913 {
0914     struct max98390_priv *max98390 =
0915         snd_soc_component_get_drvdata(component);
0916 
0917     regmap_write(max98390->regmap, MAX98390_SOFTWARE_RESET, 0x01);
0918     /* Sleep reset settle time */
0919     msleep(20);
0920 
0921     /* Amp init setting */
0922     max98390_init_regs(component);
0923     /* Update dsm bin param */
0924     max98390_dsm_init(component);
0925 
0926     /* Dsm Setting */
0927     if (max98390->ref_rdc_value) {
0928         regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
0929             max98390->ref_rdc_value & 0x000000ff);
0930         regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
0931             (max98390->ref_rdc_value >> 8) & 0x000000ff);
0932         regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
0933             (max98390->ref_rdc_value >> 16) & 0x000000ff);
0934     }
0935     if (max98390->ambient_temp_value) {
0936         regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
0937             (max98390->ambient_temp_value >> 8) & 0x000000ff);
0938         regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
0939             (max98390->ambient_temp_value) & 0x000000ff);
0940     }
0941 
0942     return 0;
0943 }
0944 
0945 #ifdef CONFIG_PM_SLEEP
0946 static int max98390_suspend(struct device *dev)
0947 {
0948     struct max98390_priv *max98390 = dev_get_drvdata(dev);
0949 
0950     dev_dbg(dev, "%s:Enter\n", __func__);
0951 
0952     regcache_cache_only(max98390->regmap, true);
0953     regcache_mark_dirty(max98390->regmap);
0954 
0955     return 0;
0956 }
0957 
0958 static int max98390_resume(struct device *dev)
0959 {
0960     struct max98390_priv *max98390 = dev_get_drvdata(dev);
0961 
0962     dev_dbg(dev, "%s:Enter\n", __func__);
0963 
0964     regcache_cache_only(max98390->regmap, false);
0965     regcache_sync(max98390->regmap);
0966 
0967     return 0;
0968 }
0969 #endif
0970 
0971 static const struct dev_pm_ops max98390_pm = {
0972     SET_SYSTEM_SLEEP_PM_OPS(max98390_suspend, max98390_resume)
0973 };
0974 
0975 static const struct snd_soc_component_driver soc_codec_dev_max98390 = {
0976     .probe          = max98390_probe,
0977     .controls       = max98390_snd_controls,
0978     .num_controls       = ARRAY_SIZE(max98390_snd_controls),
0979     .dapm_widgets       = max98390_dapm_widgets,
0980     .num_dapm_widgets   = ARRAY_SIZE(max98390_dapm_widgets),
0981     .dapm_routes        = max98390_audio_map,
0982     .num_dapm_routes    = ARRAY_SIZE(max98390_audio_map),
0983     .idle_bias_on       = 1,
0984     .use_pmdown_time    = 1,
0985     .endianness     = 1,
0986 };
0987 
0988 static const struct regmap_config max98390_regmap = {
0989     .reg_bits         = 16,
0990     .val_bits         = 8,
0991     .max_register     = MAX98390_R24FF_REV_ID,
0992     .reg_defaults     = max98390_reg_defaults,
0993     .num_reg_defaults = ARRAY_SIZE(max98390_reg_defaults),
0994     .readable_reg     = max98390_readable_register,
0995     .volatile_reg     = max98390_volatile_reg,
0996     .cache_type       = REGCACHE_RBTREE,
0997 };
0998 
0999 static void max98390_slot_config(struct i2c_client *i2c,
1000     struct max98390_priv *max98390)
1001 {
1002     int value;
1003     struct device *dev = &i2c->dev;
1004 
1005     if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
1006         max98390->v_l_slot = value & 0xF;
1007     else
1008         max98390->v_l_slot = 0;
1009 
1010     if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
1011         max98390->i_l_slot = value & 0xF;
1012     else
1013         max98390->i_l_slot = 1;
1014 }
1015 
1016 static int max98390_i2c_probe(struct i2c_client *i2c)
1017 {
1018     int ret = 0;
1019     int reg = 0;
1020 
1021     struct max98390_priv *max98390 = NULL;
1022     struct i2c_adapter *adapter = i2c->adapter;
1023     struct gpio_desc *reset_gpio;
1024 
1025     ret = i2c_check_functionality(adapter,
1026         I2C_FUNC_SMBUS_BYTE
1027         | I2C_FUNC_SMBUS_BYTE_DATA);
1028     if (!ret) {
1029         dev_err(&i2c->dev, "I2C check functionality failed\n");
1030         return -ENXIO;
1031     }
1032 
1033     max98390 = devm_kzalloc(&i2c->dev, sizeof(*max98390), GFP_KERNEL);
1034     if (!max98390) {
1035         ret = -ENOMEM;
1036         return ret;
1037     }
1038     i2c_set_clientdata(i2c, max98390);
1039 
1040     ret = device_property_read_u32(&i2c->dev, "maxim,temperature_calib",
1041                        &max98390->ambient_temp_value);
1042     if (ret) {
1043         dev_info(&i2c->dev,
1044              "no optional property 'temperature_calib' found, default:\n");
1045     }
1046     ret = device_property_read_u32(&i2c->dev, "maxim,r0_calib",
1047                        &max98390->ref_rdc_value);
1048     if (ret) {
1049         dev_info(&i2c->dev,
1050              "no optional property 'r0_calib' found, default:\n");
1051     }
1052 
1053     dev_info(&i2c->dev,
1054         "%s: r0_calib: 0x%x,temperature_calib: 0x%x",
1055         __func__, max98390->ref_rdc_value,
1056         max98390->ambient_temp_value);
1057 
1058     ret = device_property_read_string(&i2c->dev, "maxim,dsm_param_name",
1059                        &max98390->dsm_param_name);
1060     if (ret)
1061         max98390->dsm_param_name = "default";
1062 
1063     /* voltage/current slot configuration */
1064     max98390_slot_config(i2c, max98390);
1065 
1066     /* regmap initialization */
1067     max98390->regmap = devm_regmap_init_i2c(i2c, &max98390_regmap);
1068     if (IS_ERR(max98390->regmap)) {
1069         ret = PTR_ERR(max98390->regmap);
1070         dev_err(&i2c->dev,
1071             "Failed to allocate regmap: %d\n", ret);
1072         return ret;
1073     }
1074 
1075     reset_gpio = devm_gpiod_get_optional(&i2c->dev,
1076                          "reset", GPIOD_OUT_HIGH);
1077 
1078     /* Power on device */
1079     if (reset_gpio) {
1080         usleep_range(1000, 2000);
1081         /* bring out of reset */
1082         gpiod_set_value_cansleep(reset_gpio, 0);
1083         usleep_range(1000, 2000);
1084     }
1085 
1086     /* Check Revision ID */
1087     ret = regmap_read(max98390->regmap,
1088         MAX98390_R24FF_REV_ID, &reg);
1089     if (ret) {
1090         dev_err(&i2c->dev,
1091             "ret=%d, Failed to read: 0x%02X\n",
1092             ret, MAX98390_R24FF_REV_ID);
1093         return ret;
1094     }
1095     dev_info(&i2c->dev, "MAX98390 revisionID: 0x%02X\n", reg);
1096 
1097     ret = devm_snd_soc_register_component(&i2c->dev,
1098             &soc_codec_dev_max98390,
1099             max98390_dai, ARRAY_SIZE(max98390_dai));
1100 
1101     return ret;
1102 }
1103 
1104 static const struct i2c_device_id max98390_i2c_id[] = {
1105     { "max98390", 0},
1106     {},
1107 };
1108 
1109 MODULE_DEVICE_TABLE(i2c, max98390_i2c_id);
1110 
1111 #if defined(CONFIG_OF)
1112 static const struct of_device_id max98390_of_match[] = {
1113     { .compatible = "maxim,max98390", },
1114     {}
1115 };
1116 MODULE_DEVICE_TABLE(of, max98390_of_match);
1117 #endif
1118 
1119 #ifdef CONFIG_ACPI
1120 static const struct acpi_device_id max98390_acpi_match[] = {
1121     { "MX98390", 0 },
1122     {},
1123 };
1124 MODULE_DEVICE_TABLE(acpi, max98390_acpi_match);
1125 #endif
1126 
1127 static struct i2c_driver max98390_i2c_driver = {
1128     .driver = {
1129         .name = "max98390",
1130         .of_match_table = of_match_ptr(max98390_of_match),
1131         .acpi_match_table = ACPI_PTR(max98390_acpi_match),
1132         .pm = &max98390_pm,
1133     },
1134     .probe_new = max98390_i2c_probe,
1135     .id_table = max98390_i2c_id,
1136 };
1137 
1138 module_i2c_driver(max98390_i2c_driver)
1139 
1140 MODULE_DESCRIPTION("ALSA SoC MAX98390 driver");
1141 MODULE_AUTHOR("Steve Lee <steves.lee@maximintegrated.com>");
1142 MODULE_LICENSE("GPL");
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