soc/codecs/max98373.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017, Maxim Integrated
0003
0004 #include <linux/acpi.h>
0005 #include <linux/delay.h>
0006 #include <linux/i2c.h>
0007 #include <linux/module.h>
0008 #include <linux/pm_runtime.h>
0009 #include <linux/regmap.h>
0010 #include <linux/slab.h>
0011 #include <linux/cdev.h>
0012 #include <sound/pcm.h>
0013 #include <sound/pcm_params.h>
0014 #include <sound/soc.h>
0015 #include <linux/gpio.h>
0016 #include <linux/of.h>
0017 #include <linux/of_gpio.h>
0018 #include <sound/tlv.h>
0019 #include "max98373.h"
0020
0021 static int max98373_dac_event(struct snd_soc_dapm_widget *w,
0022     struct snd_kcontrol *kcontrol, int event)
0023 {
0024     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0025     struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0026
0027     switch (event) {
0028     case SND_SOC_DAPM_POST_PMU:
0029         regmap_update_bits(max98373->regmap,
0030             MAX98373_R20FF_GLOBAL_SHDN,
0031             MAX98373_GLOBAL_EN_MASK, 1);
0032         usleep_range(30000, 31000);
0033         break;
0034     case SND_SOC_DAPM_POST_PMD:
0035         regmap_update_bits(max98373->regmap,
0036             MAX98373_R20FF_GLOBAL_SHDN,
0037             MAX98373_GLOBAL_EN_MASK, 0);
0038         usleep_range(30000, 31000);
0039         max98373->tdm_mode = false;
0040         break;
0041     default:
0042         return 0;
0043     }
0044     return 0;
0045 }
0046
0047 static const char * const max98373_switch_text[] = {
0048     "Left", "Right", "LeftRight"};
0049
0050 static const struct soc_enum dai_sel_enum =
0051     SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0052         MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
0053         3, max98373_switch_text);
0054
0055 static const struct snd_kcontrol_new max98373_dai_controls =
0056     SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
0057
0058 static const struct snd_kcontrol_new max98373_vi_control =
0059     SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
0060
0061 static const struct snd_kcontrol_new max98373_spkfb_control =
0062     SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
0063
0064 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
0065 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
0066     MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
0067     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0068 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
0069     &max98373_dai_controls),
0070 SND_SOC_DAPM_OUTPUT("BE_OUT"),
0071 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
0072     MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
0073 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
0074     MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
0075 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
0076     SND_SOC_NOPM, 0, 0),
0077 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
0078     &max98373_vi_control),
0079 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
0080     &max98373_spkfb_control),
0081 SND_SOC_DAPM_SIGGEN("VMON"),
0082 SND_SOC_DAPM_SIGGEN("IMON"),
0083 SND_SOC_DAPM_SIGGEN("FBMON"),
0084 };
0085
0086 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
0087 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
0088     0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
0089     9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
0090 );
0091 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
0092     0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
0093 );
0094 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
0095     0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
0096     2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
0097 );
0098 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
0099     0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
0100 );
0101 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
0102     0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
0103     2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
0104     5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
0105     7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
0106     10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
0107     14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
0108 );
0109 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
0110     0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
0111 );
0112
0113 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
0114     0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
0115 );
0116
0117 static const char * const max98373_output_voltage_lvl_text[] = {
0118     "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
0119     "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
0120 };
0121
0122 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
0123                 MAX98373_R203E_AMP_PATH_GAIN, 0,
0124                 max98373_output_voltage_lvl_text);
0125
0126 static const char * const max98373_dht_attack_rate_text[] = {
0127     "17.5us", "35us", "70us", "140us",
0128     "280us", "560us", "1120us", "2240us"
0129 };
0130
0131 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
0132                 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
0133                 max98373_dht_attack_rate_text);
0134
0135 static const char * const max98373_dht_release_rate_text[] = {
0136     "45ms", "225ms", "450ms", "1150ms",
0137     "2250ms", "3100ms", "4500ms", "6750ms"
0138 };
0139
0140 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
0141                 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
0142                 max98373_dht_release_rate_text);
0143
0144 static const char * const max98373_limiter_attack_rate_text[] = {
0145     "10us", "20us", "40us", "80us",
0146     "160us", "320us", "640us", "1.28ms",
0147     "2.56ms", "5.12ms", "10.24ms", "20.48ms",
0148     "40.96ms", "81.92ms", "16.384ms", "32.768ms"
0149 };
0150
0151 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
0152                 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
0153                 max98373_limiter_attack_rate_text);
0154
0155 static const char * const max98373_limiter_release_rate_text[] = {
0156     "40us", "80us", "160us", "320us",
0157     "640us", "1.28ms", "2.56ms", "5.120ms",
0158     "10.24ms", "20.48ms", "40.96ms", "81.92ms",
0159     "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
0160 };
0161
0162 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
0163                 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
0164                 max98373_limiter_release_rate_text);
0165
0166 static const char * const max98373_ADC_samplerate_text[] = {
0167     "333kHz", "192kHz", "64kHz", "48kHz"
0168 };
0169
0170 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
0171                 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
0172                 max98373_ADC_samplerate_text);
0173
0174 static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
0175                  struct snd_ctl_elem_value *ucontrol)
0176 {
0177     struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
0178     struct soc_mixer_control *mc =
0179         (struct soc_mixer_control *)kcontrol->private_value;
0180     struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0181     int i;
0182
0183     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0184         /*
0185          * Register values will be cached before suspend. The cached value
0186          * will be a valid value and userspace will happy with that.
0187          */
0188         for (i = 0; i < max98373->cache_num; i++) {
0189             if (mc->reg == max98373->cache[i].reg) {
0190                 ucontrol->value.integer.value[0] = max98373->cache[i].val;
0191                 return 0;
0192             }
0193         }
0194     }
0195
0196     return snd_soc_get_volsw(kcontrol, ucontrol);
0197 }
0198
0199 static const struct snd_kcontrol_new max98373_snd_controls[] = {
0200 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
0201     MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
0202 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
0203     MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
0204 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
0205     MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
0206 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
0207     MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
0208 /* Speaker Amplifier Overcurrent Automatic Restart Enable */
0209 SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0210     MAX98373_OVC_AUTORESTART_SHIFT, 1, 0),
0211 /* Thermal Shutdown Automatic Restart Enable */
0212 SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0213     MAX98373_THERM_AUTORESTART_SHIFT, 1, 0),
0214 /* Clock Monitor Automatic Restart Enable */
0215 SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0216     MAX98373_CMON_AUTORESTART_SHIFT, 1, 0),
0217 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0218     MAX98373_CLOCK_MON_SHIFT, 1, 0),
0219 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
0220     MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
0221 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
0222     MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
0223 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
0224     0, 0x7F, 1, max98373_digital_tlv),
0225 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
0226     MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
0227 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
0228     MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
0229 SOC_ENUM("Output Voltage", max98373_out_volt_enum),
0230 /* Dynamic Headroom Tracking */
0231 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
0232     MAX98373_DHT_EN_SHIFT, 1, 0),
0233 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
0234     MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
0235 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
0236     MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
0237 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
0238     MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
0239 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
0240     MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
0241 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
0242 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
0243 /* ADC configuration */
0244 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
0245 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
0246     MAX98373_FLT_EN_SHIFT, 1, 0),
0247 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
0248     MAX98373_FLT_EN_SHIFT, 1, 0),
0249 SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
0250     max98373_feedback_get, NULL),
0251 SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
0252     max98373_feedback_get, NULL),
0253 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
0254     0, 0x3, 0),
0255 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
0256     0, 0x3, 0),
0257 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
0258 /* Brownout Detection Engine */
0259 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
0260 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
0261     MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
0262 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
0263     MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
0264 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
0265 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
0266 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
0267 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
0268 SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
0269     max98373_feedback_get, NULL),
0270 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
0271 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
0272 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
0273 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
0274 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
0275 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
0276     0, 0x3C, 1, max98373_bde_gain_tlv),
0277 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
0278     0, 0x3C, 1, max98373_bde_gain_tlv),
0279 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
0280     0, 0x3C, 1, max98373_bde_gain_tlv),
0281 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
0282     0, 0x3C, 1, max98373_bde_gain_tlv),
0283 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
0284     0, 0x3C, 1, max98373_bde_gain_tlv),
0285 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
0286     0, 0x3C, 1, max98373_bde_gain_tlv),
0287 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
0288     0, 0x3C, 1, max98373_bde_gain_tlv),
0289 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
0290     0, 0x3C, 1, max98373_bde_gain_tlv),
0291 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
0292     0, 0xF, 1, max98373_limiter_thresh_tlv),
0293 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
0294     0, 0xF, 1, max98373_limiter_thresh_tlv),
0295 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
0296     0, 0xF, 1, max98373_limiter_thresh_tlv),
0297 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
0298     0, 0xF, 1, max98373_limiter_thresh_tlv),
0299 /* Limiter */
0300 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
0301     MAX98373_LIMITER_EN_SHIFT, 1, 0),
0302 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
0303     MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
0304 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
0305     MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
0306 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
0307 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
0308 };
0309
0310 static const struct snd_soc_dapm_route max98373_audio_map[] = {
0311     /* Plabyack */
0312     {"DAI Sel Mux", "Left", "Amp Enable"},
0313     {"DAI Sel Mux", "Right", "Amp Enable"},
0314     {"DAI Sel Mux", "LeftRight", "Amp Enable"},
0315     {"BE_OUT", NULL, "DAI Sel Mux"},
0316     /* Capture */
0317     { "VI Sense", "Switch", "VMON" },
0318     { "VI Sense", "Switch", "IMON" },
0319     { "SpkFB Sense", "Switch", "FBMON" },
0320     { "Voltage Sense", NULL, "VI Sense" },
0321     { "Current Sense", NULL, "VI Sense" },
0322     { "Speaker FB Sense", NULL, "SpkFB Sense" },
0323 };
0324
0325 void max98373_reset(struct max98373_priv *max98373, struct device *dev)
0326 {
0327     int ret, reg, count;
0328
0329     /* Software Reset */
0330     ret = regmap_update_bits(max98373->regmap,
0331         MAX98373_R2000_SW_RESET,
0332         MAX98373_SOFT_RESET,
0333         MAX98373_SOFT_RESET);
0334     if (ret)
0335         dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
0336
0337     count = 0;
0338     while (count < 3) {
0339         usleep_range(10000, 11000);
0340         /* Software Reset Verification */
0341         ret = regmap_read(max98373->regmap,
0342             MAX98373_R21FF_REV_ID, &reg);
0343         if (!ret) {
0344             dev_info(dev, "Reset completed (retry:%d)\n", count);
0345             return;
0346         }
0347         count++;
0348     }
0349     dev_err(dev, "Reset failed. (ret:%d)\n", ret);
0350 }
0351 EXPORT_SYMBOL_GPL(max98373_reset);
0352
0353 static int max98373_probe(struct snd_soc_component *component)
0354 {
0355     struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0356
0357     /* Software Reset */
0358     max98373_reset(max98373, component->dev);
0359
0360     /* IV default slot configuration */
0361     regmap_write(max98373->regmap,
0362         MAX98373_R2020_PCM_TX_HIZ_EN_1,
0363         0xFF);
0364     regmap_write(max98373->regmap,
0365         MAX98373_R2021_PCM_TX_HIZ_EN_2,
0366         0xFF);
0367     /* L/R mix configuration */
0368     regmap_write(max98373->regmap,
0369         MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0370         0x80);
0371     regmap_write(max98373->regmap,
0372         MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0373         0x1);
0374     /* Enable DC blocker */
0375     regmap_write(max98373->regmap,
0376         MAX98373_R203F_AMP_DSP_CFG,
0377         0x3);
0378     /* Enable IMON VMON DC blocker */
0379     regmap_write(max98373->regmap,
0380         MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0381         0x7);
0382     /* voltage, current slot configuration */
0383     regmap_write(max98373->regmap,
0384         MAX98373_R2022_PCM_TX_SRC_1,
0385         (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
0386         max98373->v_slot) & 0xFF);
0387     if (max98373->v_slot < 8)
0388         regmap_update_bits(max98373->regmap,
0389             MAX98373_R2020_PCM_TX_HIZ_EN_1,
0390             1 << max98373->v_slot, 0);
0391     else
0392         regmap_update_bits(max98373->regmap,
0393             MAX98373_R2021_PCM_TX_HIZ_EN_2,
0394             1 << (max98373->v_slot - 8), 0);
0395
0396     if (max98373->i_slot < 8)
0397         regmap_update_bits(max98373->regmap,
0398             MAX98373_R2020_PCM_TX_HIZ_EN_1,
0399             1 << max98373->i_slot, 0);
0400     else
0401         regmap_update_bits(max98373->regmap,
0402             MAX98373_R2021_PCM_TX_HIZ_EN_2,
0403             1 << (max98373->i_slot - 8), 0);
0404
0405     /* enable auto restart function by default */
0406     regmap_write(max98373->regmap,
0407         MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
0408         0xF);
0409
0410     /* speaker feedback slot configuration */
0411     regmap_write(max98373->regmap,
0412         MAX98373_R2023_PCM_TX_SRC_2,
0413         max98373->spkfb_slot & 0xFF);
0414
0415     /* Set interleave mode */
0416     if (max98373->interleave_mode)
0417         regmap_update_bits(max98373->regmap,
0418             MAX98373_R2024_PCM_DATA_FMT_CFG,
0419             MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
0420             MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
0421
0422     /* Speaker enable */
0423     regmap_update_bits(max98373->regmap,
0424         MAX98373_R2043_AMP_EN,
0425         MAX98373_SPK_EN_MASK, 1);
0426
0427     return 0;
0428 }
0429
0430 const struct snd_soc_component_driver soc_codec_dev_max98373 = {
0431     .probe          = max98373_probe,
0432     .controls       = max98373_snd_controls,
0433     .num_controls       = ARRAY_SIZE(max98373_snd_controls),
0434     .dapm_widgets       = max98373_dapm_widgets,
0435     .num_dapm_widgets   = ARRAY_SIZE(max98373_dapm_widgets),
0436     .dapm_routes        = max98373_audio_map,
0437     .num_dapm_routes    = ARRAY_SIZE(max98373_audio_map),
0438     .use_pmdown_time    = 1,
0439     .endianness     = 1,
0440 };
0441 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
0442
0443 static int max98373_sdw_probe(struct snd_soc_component *component)
0444 {
0445     int ret;
0446
0447     ret = pm_runtime_resume(component->dev);
0448     if (ret < 0 && ret != -EACCES)
0449         return ret;
0450
0451     return 0;
0452 }
0453
0454 const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
0455     .probe          = max98373_sdw_probe,
0456     .controls       = max98373_snd_controls,
0457     .num_controls       = ARRAY_SIZE(max98373_snd_controls),
0458     .dapm_widgets       = max98373_dapm_widgets,
0459     .num_dapm_widgets   = ARRAY_SIZE(max98373_dapm_widgets),
0460     .dapm_routes        = max98373_audio_map,
0461     .num_dapm_routes    = ARRAY_SIZE(max98373_audio_map),
0462     .use_pmdown_time    = 1,
0463     .endianness     = 1,
0464 };
0465 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
0466
0467 void max98373_slot_config(struct device *dev,
0468               struct max98373_priv *max98373)
0469 {
0470     int value;
0471
0472     if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
0473         max98373->v_slot = value & 0xF;
0474     else
0475         max98373->v_slot = 0;
0476
0477     if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
0478         max98373->i_slot = value & 0xF;
0479     else
0480         max98373->i_slot = 1;
0481     if (dev->of_node) {
0482         max98373->reset_gpio = of_get_named_gpio(dev->of_node,
0483                         "maxim,reset-gpio", 0);
0484         if (!gpio_is_valid(max98373->reset_gpio)) {
0485             dev_err(dev, "Looking up %s property in node %s failed %d\n",
0486                 "maxim,reset-gpio", dev->of_node->full_name,
0487                 max98373->reset_gpio);
0488         } else {
0489             dev_dbg(dev, "maxim,reset-gpio=%d",
0490                 max98373->reset_gpio);
0491         }
0492     } else {
0493         /* this makes reset_gpio as invalid */
0494         max98373->reset_gpio = -1;
0495     }
0496
0497     if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
0498         max98373->spkfb_slot = value & 0xF;
0499     else
0500         max98373->spkfb_slot = 2;
0501 }
0502 EXPORT_SYMBOL_GPL(max98373_slot_config);
0503
0504 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
0505 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
0506 MODULE_LICENSE("GPL");