soc/codecs/max98373-sdw.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2020 Maxim Integrated */
0003
0004 #ifndef _MAX98373_SDW_H
0005 #define _MAX98373_SDW_H
0006
0007 #include "max98373.h"
0008
0009 /* SoundWire Slave Control Port (SCP)  */
0010 #define MAX98373_R0040_SCP_INIT_STAT_1      0x0040
0011 #define MAX98373_R0041_SCP_INIT_MASK_1      0x0041
0012 #define MAX98373_R0042_SCP_INIT_STAT_2      0x0042
0013 #define MAX98373_R0044_SCP_CTRL         0x0044
0014 #define MAX98373_R0045_SCP_SYSTEM_CTRL      0x0045
0015 #define MAX98373_R0046_SCP_DEV_NUMBER       0x0046
0016 #define MAX98373_R0050_SCP_DEV_ID_0     0x0050
0017 #define MAX98373_R0051_SCP_DEV_ID_1     0x0051
0018 #define MAX98373_R0052_SCP_DEV_ID_2     0x0052
0019 #define MAX98373_R0053_SCP_DEV_ID_3     0x0053
0020 #define MAX98373_R0054_SCP_DEV_ID_4     0x0054
0021 #define MAX98373_R0055_SCP_DEV_ID_5     0x0055
0022 #define MAX98373_R0060_SCP_FRAME_CTLR       0x0060
0023 #define MAX98373_R0070_SCP_FRAME_CTLR       0x0070
0024
0025 /* SoundWire Device Data Port (DP)  */
0026 /* Data Port 1 Registers */
0027 #define MAX98373_R0100_DP1_INIT_STAT        0x0100
0028 #define MAX98373_R0101_DP1_INIT_MASK        0x0101
0029 #define MAX98373_R0102_DP1_PORT_CTRL        0x0102
0030 #define MAX98373_R0103_DP1_BLOCK_CTRL_1     0x0103
0031 #define MAX98373_R0104_DP1_PREPARE_STATUS   0x0104
0032 #define MAX98373_R0105_DP1_PREPARE_CTRL     0x0105
0033 /* Data Port 1 Bank 0 Registers */
0034 #define MAX98373_R0120_DP1_CHANNEL_EN       0x0120
0035 #define MAX98373_R0122_DP1_SAMPLE_CTRL1     0x0122
0036 #define MAX98373_R0123_DP1_SAMPLE_CTRL2     0x0123
0037 #define MAX98373_R0124_DP1_OFFSET_CTRL1     0x0124
0038 #define MAX98373_R0125_DP1_OFFSET_CTRL2     0x0125
0039 #define MAX98373_R0126_DP1_HCTRL        0x0126
0040 #define MAX98373_R0127_DP1_BLOCK_CTRL3      0x0127
0041 /* Data Port 1 Bank 1 Registers */
0042 #define MAX98373_R0130_DP1_CHANNEL_EN       0x0130
0043 #define MAX98373_R0132_DP1_SAMPLE_CTRL1     0x0132
0044 #define MAX98373_R0133_DP1_SAMPLE_CTRL2     0x0133
0045 #define MAX98373_R0134_DP1_OFFSET_CTRL1     0x0134
0046 #define MAX98373_R0135_DP1_OFFSET_CTRL2     0x0135
0047 #define MAX98373_R0136_DP1_HCTRL        0x0136
0048 #define MAX98373_R0137_DP1_BLOCK_CTRL3      0x0137
0049 /* Data Port 3 Registers */
0050 #define MAX98373_R0300_DP3_INIT_STAT        0x0300
0051 #define MAX98373_R0301_DP3_INIT_MASK        0x0301
0052 #define MAX98373_R0302_DP3_PORT_CTRL        0x0302
0053 #define MAX98373_R0303_DP3_BLOCK_CTRL_1     0x0303
0054 #define MAX98373_R0304_DP3_PREPARE_STATUS   0x0304
0055 #define MAX98373_R0305_DP3_PREPARE_CTRL     0x0305
0056 /* Data Port 3 Bank 0 Registers */
0057 #define MAX98373_R0320_DP3_CHANNEL_EN       0x0320
0058 #define MAX98373_R0322_DP3_SAMPLE_CTRL1     0x0322
0059 #define MAX98373_R0323_DP3_SAMPLE_CTRL2     0x0323
0060 #define MAX98373_R0324_DP3_OFFSET_CTRL1     0x0324
0061 #define MAX98373_R0325_DP3_OFFSET_CTRL2     0x0325
0062 #define MAX98373_R0326_DP3_HCTRL        0x0326
0063 #define MAX98373_R0327_DP3_BLOCK_CTRL3      0x0327
0064 /* Data Port 3 Bank 1 Registers */
0065 #define MAX98373_R0330_DP3_CHANNEL_EN       0x0330
0066 #define MAX98373_R0332_DP3_SAMPLE_CTRL1     0x0332
0067 #define MAX98373_R0333_DP3_SAMPLE_CTRL2     0x0333
0068 #define MAX98373_R0334_DP3_OFFSET_CTRL1     0x0334
0069 #define MAX98373_R0335_DP3_OFFSET_CTRL2     0x0335
0070 #define MAX98373_R0336_DP3_HCTRL        0x0336
0071 #define MAX98373_R0337_DP3_BLOCK_CTRL3      0x0337
0072 #endif