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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (c) 2020, Maxim Integrated
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/delay.h>
0006 #include <linux/module.h>
0007 #include <linux/mod_devicetable.h>
0008 #include <linux/pm_runtime.h>
0009 #include <linux/regmap.h>
0010 #include <linux/slab.h>
0011 #include <sound/pcm.h>
0012 #include <sound/pcm_params.h>
0013 #include <sound/soc.h>
0014 #include <sound/tlv.h>
0015 #include <linux/of.h>
0016 #include <linux/soundwire/sdw.h>
0017 #include <linux/soundwire/sdw_type.h>
0018 #include <linux/soundwire/sdw_registers.h>
0019 #include "max98373.h"
0020 #include "max98373-sdw.h"
0021 
0022 struct sdw_stream_data {
0023     struct sdw_stream_runtime *sdw_stream;
0024 };
0025 
0026 static const u32 max98373_sdw_cache_reg[] = {
0027     MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
0028     MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
0029     MAX98373_R20B6_BDE_CUR_STATE_READBACK,
0030 };
0031 
0032 static struct reg_default max98373_reg[] = {
0033     {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
0034     {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
0035     {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
0036     {MAX98373_R0044_SCP_CTRL, 0x00},
0037     {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
0038     {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
0039     {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
0040     {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
0041     {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
0042     {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
0043     {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
0044     {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
0045     {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
0046     {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
0047     {MAX98373_R0100_DP1_INIT_STAT, 0x00},
0048     {MAX98373_R0101_DP1_INIT_MASK, 0x00},
0049     {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
0050     {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
0051     {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
0052     {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
0053     {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
0054     {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
0055     {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
0056     {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
0057     {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
0058     {MAX98373_R0126_DP1_HCTRL, 0x00},
0059     {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
0060     {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
0061     {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
0062     {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
0063     {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
0064     {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
0065     {MAX98373_R0136_DP1_HCTRL, 0x0136},
0066     {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
0067     {MAX98373_R0300_DP3_INIT_STAT, 0x00},
0068     {MAX98373_R0301_DP3_INIT_MASK, 0x00},
0069     {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
0070     {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
0071     {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
0072     {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
0073     {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
0074     {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
0075     {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
0076     {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
0077     {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
0078     {MAX98373_R0326_DP3_HCTRL, 0x00},
0079     {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
0080     {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
0081     {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
0082     {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
0083     {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
0084     {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
0085     {MAX98373_R0336_DP3_HCTRL, 0x00},
0086     {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
0087     {MAX98373_R2000_SW_RESET, 0x00},
0088     {MAX98373_R2001_INT_RAW1, 0x00},
0089     {MAX98373_R2002_INT_RAW2, 0x00},
0090     {MAX98373_R2003_INT_RAW3, 0x00},
0091     {MAX98373_R2004_INT_STATE1, 0x00},
0092     {MAX98373_R2005_INT_STATE2, 0x00},
0093     {MAX98373_R2006_INT_STATE3, 0x00},
0094     {MAX98373_R2007_INT_FLAG1, 0x00},
0095     {MAX98373_R2008_INT_FLAG2, 0x00},
0096     {MAX98373_R2009_INT_FLAG3, 0x00},
0097     {MAX98373_R200A_INT_EN1, 0x00},
0098     {MAX98373_R200B_INT_EN2, 0x00},
0099     {MAX98373_R200C_INT_EN3, 0x00},
0100     {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
0101     {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
0102     {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
0103     {MAX98373_R2010_IRQ_CTRL, 0x00},
0104     {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
0105     {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
0106     {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
0107     {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
0108     {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
0109     {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
0110     {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
0111     {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
0112     {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
0113     {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
0114     {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
0115     {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
0116     {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
0117     {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
0118     {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
0119     {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
0120     {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
0121     {MAX98373_R202B_PCM_RX_EN, 0x00},
0122     {MAX98373_R202C_PCM_TX_EN, 0x00},
0123     {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
0124     {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
0125     {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
0126     {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
0127     {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
0128     {MAX98373_R2034_ICC_TX_CNTL, 0x00},
0129     {MAX98373_R2035_ICC_TX_EN, 0x00},
0130     {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
0131     {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
0132     {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
0133     {MAX98373_R203F_AMP_DSP_CFG, 0x02},
0134     {MAX98373_R2040_TONE_GEN_CFG, 0x00},
0135     {MAX98373_R2041_AMP_CFG, 0x03},
0136     {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
0137     {MAX98373_R2043_AMP_EN, 0x00},
0138     {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
0139     {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
0140     {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
0141     {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
0142     {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
0143     {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
0144     {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
0145     {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
0146     {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
0147     {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
0148     {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
0149     {MAX98373_R2097_BDE_L1_THRESH, 0x00},
0150     {MAX98373_R2098_BDE_L2_THRESH, 0x00},
0151     {MAX98373_R2099_BDE_L3_THRESH, 0x00},
0152     {MAX98373_R209A_BDE_L4_THRESH, 0x00},
0153     {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
0154     {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
0155     {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
0156     {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
0157     {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
0158     {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
0159     {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
0160     {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
0161     {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
0162     {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
0163     {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
0164     {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
0165     {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
0166     {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
0167     {MAX98373_R20B5_BDE_EN, 0x00},
0168     {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
0169     {MAX98373_R20D1_DHT_CFG, 0x01},
0170     {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
0171     {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
0172     {MAX98373_R20D4_DHT_EN, 0x00},
0173     {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
0174     {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
0175     {MAX98373_R20E2_LIMITER_EN, 0x00},
0176     {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
0177     {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
0178     {MAX98373_R21FF_REV_ID, 0x42},
0179 };
0180 
0181 static bool max98373_readable_register(struct device *dev, unsigned int reg)
0182 {
0183     switch (reg) {
0184     case MAX98373_R21FF_REV_ID:
0185     case MAX98373_R2010_IRQ_CTRL:
0186     /* SoundWire Control Port Registers */
0187     case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
0188     /* Soundwire Data Port 1 Registers */
0189     case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
0190     /* Soundwire Data Port 3 Registers */
0191     case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
0192     case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
0193     case MAX98373_R2014_THERM_WARN_THRESH
0194         ... MAX98373_R2018_THERM_FOLDBACK_EN:
0195     case MAX98373_R201E_PIN_DRIVE_STRENGTH
0196         ... MAX98373_R2036_SOUNDWIRE_CTRL:
0197     case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
0198     case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
0199         ... MAX98373_R2047_IV_SENSE_ADC_EN:
0200     case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
0201         ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
0202     case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
0203     case MAX98373_R2097_BDE_L1_THRESH
0204         ... MAX98373_R209B_BDE_THRESH_HYST:
0205     case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
0206     case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
0207     case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
0208     case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
0209     case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
0210         ... MAX98373_R20FF_GLOBAL_SHDN:
0211         return true;
0212     default:
0213         return false;
0214     }
0215 };
0216 
0217 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
0218 {
0219     switch (reg) {
0220     case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
0221     case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
0222     case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
0223     case MAX98373_R20FF_GLOBAL_SHDN:
0224     case MAX98373_R21FF_REV_ID:
0225     /* SoundWire Control Port Registers */
0226     case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
0227     /* Soundwire Data Port 1 Registers */
0228     case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
0229     /* Soundwire Data Port 3 Registers */
0230     case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
0231     case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
0232         return true;
0233     default:
0234         return false;
0235     }
0236 }
0237 
0238 static const struct regmap_config max98373_sdw_regmap = {
0239     .reg_bits = 32,
0240     .val_bits = 8,
0241     .max_register = MAX98373_R21FF_REV_ID,
0242     .reg_defaults  = max98373_reg,
0243     .num_reg_defaults = ARRAY_SIZE(max98373_reg),
0244     .readable_reg = max98373_readable_register,
0245     .volatile_reg = max98373_volatile_reg,
0246     .cache_type = REGCACHE_RBTREE,
0247     .use_single_read = true,
0248     .use_single_write = true,
0249 };
0250 
0251 /* Power management functions and structure */
0252 static __maybe_unused int max98373_suspend(struct device *dev)
0253 {
0254     struct max98373_priv *max98373 = dev_get_drvdata(dev);
0255     int i;
0256 
0257     /* cache feedback register values before suspend */
0258     for (i = 0; i < max98373->cache_num; i++)
0259         regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
0260 
0261     regcache_cache_only(max98373->regmap, true);
0262 
0263     return 0;
0264 }
0265 
0266 #define MAX98373_PROBE_TIMEOUT 5000
0267 
0268 static __maybe_unused int max98373_resume(struct device *dev)
0269 {
0270     struct sdw_slave *slave = dev_to_sdw_dev(dev);
0271     struct max98373_priv *max98373 = dev_get_drvdata(dev);
0272     unsigned long time;
0273 
0274     if (!max98373->first_hw_init)
0275         return 0;
0276 
0277     if (!slave->unattach_request)
0278         goto regmap_sync;
0279 
0280     time = wait_for_completion_timeout(&slave->initialization_complete,
0281                        msecs_to_jiffies(MAX98373_PROBE_TIMEOUT));
0282     if (!time) {
0283         dev_err(dev, "Initialization not complete, timed out\n");
0284         return -ETIMEDOUT;
0285     }
0286 
0287 regmap_sync:
0288     slave->unattach_request = 0;
0289     regcache_cache_only(max98373->regmap, false);
0290     regcache_sync(max98373->regmap);
0291 
0292     return 0;
0293 }
0294 
0295 static const struct dev_pm_ops max98373_pm = {
0296     SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
0297     SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
0298 };
0299 
0300 static int max98373_read_prop(struct sdw_slave *slave)
0301 {
0302     struct sdw_slave_prop *prop = &slave->prop;
0303     int nval, i;
0304     u32 bit;
0305     unsigned long addr;
0306     struct sdw_dpn_prop *dpn;
0307 
0308     prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
0309 
0310     /* BITMAP: 00001000  Dataport 3 is active */
0311     prop->source_ports = BIT(3);
0312     /* BITMAP: 00000010  Dataport 1 is active */
0313     prop->sink_ports = BIT(1);
0314     prop->paging_support = true;
0315     prop->clk_stop_timeout = 20;
0316 
0317     nval = hweight32(prop->source_ports);
0318     prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
0319                       sizeof(*prop->src_dpn_prop),
0320                       GFP_KERNEL);
0321     if (!prop->src_dpn_prop)
0322         return -ENOMEM;
0323 
0324     i = 0;
0325     dpn = prop->src_dpn_prop;
0326     addr = prop->source_ports;
0327     for_each_set_bit(bit, &addr, 32) {
0328         dpn[i].num = bit;
0329         dpn[i].type = SDW_DPN_FULL;
0330         dpn[i].simple_ch_prep_sm = true;
0331         dpn[i].ch_prep_timeout = 10;
0332         i++;
0333     }
0334 
0335     /* do this again for sink now */
0336     nval = hweight32(prop->sink_ports);
0337     prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
0338                        sizeof(*prop->sink_dpn_prop),
0339                        GFP_KERNEL);
0340     if (!prop->sink_dpn_prop)
0341         return -ENOMEM;
0342 
0343     i = 0;
0344     dpn = prop->sink_dpn_prop;
0345     addr = prop->sink_ports;
0346     for_each_set_bit(bit, &addr, 32) {
0347         dpn[i].num = bit;
0348         dpn[i].type = SDW_DPN_FULL;
0349         dpn[i].simple_ch_prep_sm = true;
0350         dpn[i].ch_prep_timeout = 10;
0351         i++;
0352     }
0353 
0354     /* set the timeout values */
0355     prop->clk_stop_timeout = 20;
0356 
0357     return 0;
0358 }
0359 
0360 static int max98373_io_init(struct sdw_slave *slave)
0361 {
0362     struct device *dev = &slave->dev;
0363     struct max98373_priv *max98373 = dev_get_drvdata(dev);
0364 
0365     if (max98373->first_hw_init) {
0366         regcache_cache_only(max98373->regmap, false);
0367         regcache_cache_bypass(max98373->regmap, true);
0368     }
0369 
0370     /*
0371      * PM runtime is only enabled when a Slave reports as Attached
0372      */
0373     if (!max98373->first_hw_init) {
0374         /* set autosuspend parameters */
0375         pm_runtime_set_autosuspend_delay(dev, 3000);
0376         pm_runtime_use_autosuspend(dev);
0377 
0378         /* update count of parent 'active' children */
0379         pm_runtime_set_active(dev);
0380 
0381         /* make sure the device does not suspend immediately */
0382         pm_runtime_mark_last_busy(dev);
0383 
0384         pm_runtime_enable(dev);
0385     }
0386 
0387     pm_runtime_get_noresume(dev);
0388 
0389     /* Software Reset */
0390     max98373_reset(max98373, dev);
0391 
0392     /* Set soundwire mode */
0393     regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
0394     /* Enable ADC */
0395     regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
0396     /* Set default Soundwire clock */
0397     regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
0398     /* Set default sampling rate for speaker and IVDAC */
0399     regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
0400     /* IV default slot configuration */
0401     regmap_write(max98373->regmap,
0402              MAX98373_R2020_PCM_TX_HIZ_EN_1,
0403              0xFF);
0404     regmap_write(max98373->regmap,
0405              MAX98373_R2021_PCM_TX_HIZ_EN_2,
0406              0xFF);
0407     /* L/R mix configuration */
0408     regmap_write(max98373->regmap,
0409              MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0410              0x80);
0411     regmap_write(max98373->regmap,
0412              MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0413              0x1);
0414     /* Enable DC blocker */
0415     regmap_write(max98373->regmap,
0416              MAX98373_R203F_AMP_DSP_CFG,
0417              0x3);
0418     /* Enable IMON VMON DC blocker */
0419     regmap_write(max98373->regmap,
0420              MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0421              0x7);
0422     /* voltage, current slot configuration */
0423     regmap_write(max98373->regmap,
0424              MAX98373_R2022_PCM_TX_SRC_1,
0425              (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
0426              max98373->v_slot) & 0xFF);
0427     if (max98373->v_slot < 8)
0428         regmap_update_bits(max98373->regmap,
0429                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
0430                    1 << max98373->v_slot, 0);
0431     else
0432         regmap_update_bits(max98373->regmap,
0433                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
0434                    1 << (max98373->v_slot - 8), 0);
0435 
0436     if (max98373->i_slot < 8)
0437         regmap_update_bits(max98373->regmap,
0438                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
0439                    1 << max98373->i_slot, 0);
0440     else
0441         regmap_update_bits(max98373->regmap,
0442                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
0443                    1 << (max98373->i_slot - 8), 0);
0444 
0445     /* speaker feedback slot configuration */
0446     regmap_write(max98373->regmap,
0447              MAX98373_R2023_PCM_TX_SRC_2,
0448              max98373->spkfb_slot & 0xFF);
0449 
0450     /* Set interleave mode */
0451     if (max98373->interleave_mode)
0452         regmap_update_bits(max98373->regmap,
0453                    MAX98373_R2024_PCM_DATA_FMT_CFG,
0454                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
0455                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
0456 
0457     /* Speaker enable */
0458     regmap_update_bits(max98373->regmap,
0459                MAX98373_R2043_AMP_EN,
0460                MAX98373_SPK_EN_MASK, 1);
0461 
0462     regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
0463     regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
0464 
0465     if (max98373->first_hw_init) {
0466         regcache_cache_bypass(max98373->regmap, false);
0467         regcache_mark_dirty(max98373->regmap);
0468     }
0469 
0470     max98373->first_hw_init = true;
0471     max98373->hw_init = true;
0472 
0473     pm_runtime_mark_last_busy(dev);
0474     pm_runtime_put_autosuspend(dev);
0475 
0476     return 0;
0477 }
0478 
0479 static int max98373_clock_calculate(struct sdw_slave *slave,
0480                     unsigned int clk_freq)
0481 {
0482     int x, y;
0483     static const int max98373_clk_family[] = {
0484         7680000, 8400000, 9600000, 11289600,
0485         12000000, 12288000, 13000000
0486     };
0487 
0488     for (x = 0; x < 4; x++)
0489         for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
0490             if (clk_freq == (max98373_clk_family[y] >> x))
0491                 return (x << 3) + y;
0492 
0493     /* Set default clock (12.288 Mhz) if the value is not in the list */
0494     dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
0495         clk_freq);
0496     return 0x5;
0497 }
0498 
0499 static int max98373_clock_config(struct sdw_slave *slave,
0500                  struct sdw_bus_params *params)
0501 {
0502     struct device *dev = &slave->dev;
0503     struct max98373_priv *max98373 = dev_get_drvdata(dev);
0504     unsigned int clk_freq, value;
0505 
0506     clk_freq = (params->curr_dr_freq >> 1);
0507 
0508     /*
0509      *  Select the proper value for the register based on the
0510      *  requested clock. If the value is not in the list,
0511      *  use reasonable default - 12.288 Mhz
0512      */
0513     value = max98373_clock_calculate(slave, clk_freq);
0514 
0515     /* SWCLK */
0516     regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
0517 
0518     /* The default Sampling Rate value for IV is 48KHz*/
0519     regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
0520 
0521     return 0;
0522 }
0523 
0524 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
0525 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
0526 
0527 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
0528                       struct snd_pcm_hw_params *params,
0529                       struct snd_soc_dai *dai)
0530 {
0531     struct snd_soc_component *component = dai->component;
0532     struct max98373_priv *max98373 =
0533         snd_soc_component_get_drvdata(component);
0534 
0535     struct sdw_stream_config stream_config;
0536     struct sdw_port_config port_config;
0537     enum sdw_data_direction direction;
0538     struct sdw_stream_data *stream;
0539     int ret, chan_sz, sampling_rate;
0540 
0541     stream = snd_soc_dai_get_dma_data(dai, substream);
0542 
0543     if (!stream)
0544         return -EINVAL;
0545 
0546     if (!max98373->slave)
0547         return -EINVAL;
0548 
0549     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0550         direction = SDW_DATA_DIR_RX;
0551         port_config.num = 1;
0552     } else {
0553         direction = SDW_DATA_DIR_TX;
0554         port_config.num = 3;
0555     }
0556 
0557     stream_config.frame_rate = params_rate(params);
0558     stream_config.bps = snd_pcm_format_width(params_format(params));
0559     stream_config.direction = direction;
0560 
0561     if (max98373->slot && direction == SDW_DATA_DIR_RX) {
0562         stream_config.ch_count = max98373->slot;
0563         port_config.ch_mask = max98373->rx_mask;
0564     } else {
0565         /* only IV are supported by capture */
0566         if (direction == SDW_DATA_DIR_TX)
0567             stream_config.ch_count = 2;
0568         else
0569             stream_config.ch_count = params_channels(params);
0570 
0571         port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
0572     }
0573 
0574     ret = sdw_stream_add_slave(max98373->slave, &stream_config,
0575                    &port_config, 1, stream->sdw_stream);
0576     if (ret) {
0577         dev_err(dai->dev, "Unable to configure port\n");
0578         return ret;
0579     }
0580 
0581     if (params_channels(params) > 16) {
0582         dev_err(component->dev, "Unsupported channels %d\n",
0583             params_channels(params));
0584         return -EINVAL;
0585     }
0586 
0587     /* Channel size configuration */
0588     switch (snd_pcm_format_width(params_format(params))) {
0589     case 16:
0590         chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
0591         break;
0592     case 24:
0593         chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
0594         break;
0595     case 32:
0596         chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
0597         break;
0598     default:
0599         dev_err(component->dev, "Channel size unsupported %d\n",
0600             params_format(params));
0601         return -EINVAL;
0602     }
0603 
0604     max98373->ch_size = snd_pcm_format_width(params_format(params));
0605 
0606     regmap_update_bits(max98373->regmap,
0607                MAX98373_R2024_PCM_DATA_FMT_CFG,
0608                MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0609 
0610     dev_dbg(component->dev, "Format supported %d", params_format(params));
0611 
0612     /* Sampling rate configuration */
0613     switch (params_rate(params)) {
0614     case 8000:
0615         sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
0616         break;
0617     case 11025:
0618         sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
0619         break;
0620     case 12000:
0621         sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
0622         break;
0623     case 16000:
0624         sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
0625         break;
0626     case 22050:
0627         sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
0628         break;
0629     case 24000:
0630         sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
0631         break;
0632     case 32000:
0633         sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
0634         break;
0635     case 44100:
0636         sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
0637         break;
0638     case 48000:
0639         sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
0640         break;
0641     case 88200:
0642         sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
0643         break;
0644     case 96000:
0645         sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
0646         break;
0647     default:
0648         dev_err(component->dev, "Rate %d is not supported\n",
0649             params_rate(params));
0650         return -EINVAL;
0651     }
0652 
0653     /* set correct sampling frequency */
0654     regmap_update_bits(max98373->regmap,
0655                MAX98373_R2028_PCM_SR_SETUP_2,
0656                MAX98373_PCM_SR_SET2_SR_MASK,
0657                sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
0658 
0659     /* set sampling rate of IV */
0660     regmap_update_bits(max98373->regmap,
0661                MAX98373_R2028_PCM_SR_SETUP_2,
0662                MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
0663                sampling_rate);
0664 
0665     return 0;
0666 }
0667 
0668 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
0669                 struct snd_soc_dai *dai)
0670 {
0671     struct snd_soc_component *component = dai->component;
0672     struct max98373_priv *max98373 =
0673         snd_soc_component_get_drvdata(component);
0674     struct sdw_stream_data *stream =
0675         snd_soc_dai_get_dma_data(dai, substream);
0676 
0677     if (!max98373->slave)
0678         return -EINVAL;
0679 
0680     sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
0681     return 0;
0682 }
0683 
0684 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
0685                    void *sdw_stream, int direction)
0686 {
0687     struct sdw_stream_data *stream;
0688 
0689     if (!sdw_stream)
0690         return 0;
0691 
0692     stream = kzalloc(sizeof(*stream), GFP_KERNEL);
0693     if (!stream)
0694         return -ENOMEM;
0695 
0696     stream->sdw_stream = sdw_stream;
0697 
0698     /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
0699     if (direction == SNDRV_PCM_STREAM_PLAYBACK)
0700         dai->playback_dma_data = stream;
0701     else
0702         dai->capture_dma_data = stream;
0703 
0704     return 0;
0705 }
0706 
0707 static void max98373_shutdown(struct snd_pcm_substream *substream,
0708                   struct snd_soc_dai *dai)
0709 {
0710     struct sdw_stream_data *stream;
0711 
0712     stream = snd_soc_dai_get_dma_data(dai, substream);
0713     snd_soc_dai_set_dma_data(dai, substream, NULL);
0714     kfree(stream);
0715 }
0716 
0717 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
0718                      unsigned int tx_mask,
0719                      unsigned int rx_mask,
0720                      int slots, int slot_width)
0721 {
0722     struct snd_soc_component *component = dai->component;
0723     struct max98373_priv *max98373 =
0724         snd_soc_component_get_drvdata(component);
0725 
0726     /* tx_mask is unused since it's irrelevant for I/V feedback */
0727     if (tx_mask)
0728         return -EINVAL;
0729 
0730     if (!rx_mask && !slots && !slot_width)
0731         max98373->tdm_mode = false;
0732     else
0733         max98373->tdm_mode = true;
0734 
0735     max98373->rx_mask = rx_mask;
0736     max98373->slot = slots;
0737 
0738     return 0;
0739 }
0740 
0741 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
0742     .hw_params = max98373_sdw_dai_hw_params,
0743     .hw_free = max98373_pcm_hw_free,
0744     .set_stream = max98373_set_sdw_stream,
0745     .shutdown = max98373_shutdown,
0746     .set_tdm_slot = max98373_sdw_set_tdm_slot,
0747 };
0748 
0749 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
0750     {
0751         .name = "max98373-aif1",
0752         .playback = {
0753             .stream_name = "HiFi Playback",
0754             .channels_min = 1,
0755             .channels_max = 2,
0756             .rates = MAX98373_RATES,
0757             .formats = MAX98373_FORMATS,
0758         },
0759         .capture = {
0760             .stream_name = "HiFi Capture",
0761             .channels_min = 1,
0762             .channels_max = 2,
0763             .rates = MAX98373_RATES,
0764             .formats = MAX98373_FORMATS,
0765         },
0766         .ops = &max98373_dai_sdw_ops,
0767     }
0768 };
0769 
0770 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
0771 {
0772     struct max98373_priv *max98373;
0773     int ret;
0774     int i;
0775     struct device *dev = &slave->dev;
0776 
0777     /*  Allocate and assign private driver data structure  */
0778     max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
0779     if (!max98373)
0780         return -ENOMEM;
0781 
0782     dev_set_drvdata(dev, max98373);
0783     max98373->regmap = regmap;
0784     max98373->slave = slave;
0785 
0786     max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
0787     max98373->cache = devm_kcalloc(dev, max98373->cache_num,
0788                        sizeof(*max98373->cache),
0789                        GFP_KERNEL);
0790     if (!max98373->cache)
0791         return -ENOMEM;
0792 
0793     for (i = 0; i < max98373->cache_num; i++)
0794         max98373->cache[i].reg = max98373_sdw_cache_reg[i];
0795 
0796     /* Read voltage and slot configuration */
0797     max98373_slot_config(dev, max98373);
0798 
0799     max98373->hw_init = false;
0800     max98373->first_hw_init = false;
0801 
0802     /* codec registration  */
0803     ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
0804                           max98373_sdw_dai,
0805                           ARRAY_SIZE(max98373_sdw_dai));
0806     if (ret < 0)
0807         dev_err(dev, "Failed to register codec: %d\n", ret);
0808 
0809     return ret;
0810 }
0811 
0812 static int max98373_update_status(struct sdw_slave *slave,
0813                   enum sdw_slave_status status)
0814 {
0815     struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
0816 
0817     if (status == SDW_SLAVE_UNATTACHED)
0818         max98373->hw_init = false;
0819 
0820     /*
0821      * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
0822      */
0823     if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
0824         return 0;
0825 
0826     /* perform I/O transfers required for Slave initialization */
0827     return max98373_io_init(slave);
0828 }
0829 
0830 static int max98373_bus_config(struct sdw_slave *slave,
0831                    struct sdw_bus_params *params)
0832 {
0833     int ret;
0834 
0835     ret = max98373_clock_config(slave, params);
0836     if (ret < 0)
0837         dev_err(&slave->dev, "Invalid clk config");
0838 
0839     return ret;
0840 }
0841 
0842 /*
0843  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
0844  * port_prep are not defined for now
0845  */
0846 static struct sdw_slave_ops max98373_slave_ops = {
0847     .read_prop = max98373_read_prop,
0848     .update_status = max98373_update_status,
0849     .bus_config = max98373_bus_config,
0850 };
0851 
0852 static int max98373_sdw_probe(struct sdw_slave *slave,
0853                   const struct sdw_device_id *id)
0854 {
0855     struct regmap *regmap;
0856 
0857     /* Regmap Initialization */
0858     regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
0859     if (IS_ERR(regmap))
0860         return PTR_ERR(regmap);
0861 
0862     return max98373_init(slave, regmap);
0863 }
0864 
0865 static int max98373_sdw_remove(struct sdw_slave *slave)
0866 {
0867     struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
0868 
0869     if (max98373->first_hw_init)
0870         pm_runtime_disable(&slave->dev);
0871 
0872     return 0;
0873 }
0874 
0875 #if defined(CONFIG_OF)
0876 static const struct of_device_id max98373_of_match[] = {
0877     { .compatible = "maxim,max98373", },
0878     {},
0879 };
0880 MODULE_DEVICE_TABLE(of, max98373_of_match);
0881 #endif
0882 
0883 #ifdef CONFIG_ACPI
0884 static const struct acpi_device_id max98373_acpi_match[] = {
0885     { "MX98373", 0 },
0886     {},
0887 };
0888 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
0889 #endif
0890 
0891 static const struct sdw_device_id max98373_id[] = {
0892     SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
0893     {},
0894 };
0895 MODULE_DEVICE_TABLE(sdw, max98373_id);
0896 
0897 static struct sdw_driver max98373_sdw_driver = {
0898     .driver = {
0899         .name = "max98373",
0900         .owner = THIS_MODULE,
0901         .of_match_table = of_match_ptr(max98373_of_match),
0902         .acpi_match_table = ACPI_PTR(max98373_acpi_match),
0903         .pm = &max98373_pm,
0904     },
0905     .probe = max98373_sdw_probe,
0906     .remove = max98373_sdw_remove,
0907     .ops = &max98373_slave_ops,
0908     .id_table = max98373_id,
0909 };
0910 
0911 module_sdw_driver(max98373_sdw_driver);
0912 
0913 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
0914 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
0915 MODULE_LICENSE("GPL v2");
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