0001
0002
0003
0004 #include <linux/acpi.h>
0005 #include <linux/delay.h>
0006 #include <linux/gpio.h>
0007 #include <linux/i2c.h>
0008 #include <linux/module.h>
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/of.h>
0011 #include <linux/of_gpio.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014 #include <linux/slab.h>
0015 #include <linux/cdev.h>
0016 #include <sound/pcm.h>
0017 #include <sound/pcm_params.h>
0018 #include <sound/soc.h>
0019 #include <sound/tlv.h>
0020 #include "max98373.h"
0021
0022 static const u32 max98373_i2c_cache_reg[] = {
0023 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
0024 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
0025 MAX98373_R20B6_BDE_CUR_STATE_READBACK,
0026 };
0027
0028 static struct reg_default max98373_reg[] = {
0029 {MAX98373_R2000_SW_RESET, 0x00},
0030 {MAX98373_R2001_INT_RAW1, 0x00},
0031 {MAX98373_R2002_INT_RAW2, 0x00},
0032 {MAX98373_R2003_INT_RAW3, 0x00},
0033 {MAX98373_R2004_INT_STATE1, 0x00},
0034 {MAX98373_R2005_INT_STATE2, 0x00},
0035 {MAX98373_R2006_INT_STATE3, 0x00},
0036 {MAX98373_R2007_INT_FLAG1, 0x00},
0037 {MAX98373_R2008_INT_FLAG2, 0x00},
0038 {MAX98373_R2009_INT_FLAG3, 0x00},
0039 {MAX98373_R200A_INT_EN1, 0x00},
0040 {MAX98373_R200B_INT_EN2, 0x00},
0041 {MAX98373_R200C_INT_EN3, 0x00},
0042 {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
0043 {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
0044 {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
0045 {MAX98373_R2010_IRQ_CTRL, 0x00},
0046 {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
0047 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
0048 {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
0049 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
0050 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
0051 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
0052 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
0053 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
0054 {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
0055 {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
0056 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
0057 {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
0058 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
0059 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
0060 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
0061 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
0062 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
0063 {MAX98373_R202B_PCM_RX_EN, 0x00},
0064 {MAX98373_R202C_PCM_TX_EN, 0x00},
0065 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
0066 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
0067 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
0068 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
0069 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
0070 {MAX98373_R2034_ICC_TX_CNTL, 0x00},
0071 {MAX98373_R2035_ICC_TX_EN, 0x00},
0072 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
0073 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
0074 {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
0075 {MAX98373_R203F_AMP_DSP_CFG, 0x02},
0076 {MAX98373_R2040_TONE_GEN_CFG, 0x00},
0077 {MAX98373_R2041_AMP_CFG, 0x03},
0078 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
0079 {MAX98373_R2043_AMP_EN, 0x00},
0080 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
0081 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
0082 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
0083 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
0084 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
0085 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
0086 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
0087 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
0088 {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
0089 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
0090 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
0091 {MAX98373_R2097_BDE_L1_THRESH, 0x00},
0092 {MAX98373_R2098_BDE_L2_THRESH, 0x00},
0093 {MAX98373_R2099_BDE_L3_THRESH, 0x00},
0094 {MAX98373_R209A_BDE_L4_THRESH, 0x00},
0095 {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
0096 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
0097 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
0098 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
0099 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
0100 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
0101 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
0102 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
0103 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
0104 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
0105 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
0106 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
0107 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
0108 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
0109 {MAX98373_R20B5_BDE_EN, 0x00},
0110 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
0111 {MAX98373_R20D1_DHT_CFG, 0x01},
0112 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
0113 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
0114 {MAX98373_R20D4_DHT_EN, 0x00},
0115 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
0116 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
0117 {MAX98373_R20E2_LIMITER_EN, 0x00},
0118 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
0119 {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
0120 {MAX98373_R21FF_REV_ID, 0x42},
0121 };
0122
0123 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0124 {
0125 struct snd_soc_component *component = codec_dai->component;
0126 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0127 unsigned int format = 0;
0128 unsigned int invert = 0;
0129
0130 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
0131
0132 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0133 case SND_SOC_DAIFMT_NB_NF:
0134 break;
0135 case SND_SOC_DAIFMT_IB_NF:
0136 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
0137 break;
0138 default:
0139 dev_err(component->dev, "DAI invert mode unsupported\n");
0140 return -EINVAL;
0141 }
0142
0143 regmap_update_bits(max98373->regmap,
0144 MAX98373_R2026_PCM_CLOCK_RATIO,
0145 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
0146 invert);
0147
0148
0149 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0150 case SND_SOC_DAIFMT_I2S:
0151 format = MAX98373_PCM_FORMAT_I2S;
0152 break;
0153 case SND_SOC_DAIFMT_LEFT_J:
0154 format = MAX98373_PCM_FORMAT_LJ;
0155 break;
0156 case SND_SOC_DAIFMT_DSP_A:
0157 format = MAX98373_PCM_FORMAT_TDM_MODE1;
0158 break;
0159 case SND_SOC_DAIFMT_DSP_B:
0160 format = MAX98373_PCM_FORMAT_TDM_MODE0;
0161 break;
0162 default:
0163 return -EINVAL;
0164 }
0165
0166 regmap_update_bits(max98373->regmap,
0167 MAX98373_R2024_PCM_DATA_FMT_CFG,
0168 MAX98373_PCM_MODE_CFG_FORMAT_MASK,
0169 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
0170
0171 return 0;
0172 }
0173
0174
0175 static const int bclk_sel_table[] = {
0176 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
0177 };
0178
0179 static int max98373_get_bclk_sel(int bclk)
0180 {
0181 int i;
0182
0183 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
0184 if (bclk_sel_table[i] == bclk)
0185 return i + 2;
0186 }
0187 return 0;
0188 }
0189
0190 static int max98373_set_clock(struct snd_soc_component *component,
0191 struct snd_pcm_hw_params *params)
0192 {
0193 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0194
0195 int blr_clk_ratio = params_channels(params) * max98373->ch_size;
0196 int value;
0197
0198 if (!max98373->tdm_mode) {
0199
0200 value = max98373_get_bclk_sel(blr_clk_ratio);
0201 if (!value) {
0202 dev_err(component->dev, "format unsupported %d\n",
0203 params_format(params));
0204 return -EINVAL;
0205 }
0206
0207 regmap_update_bits(max98373->regmap,
0208 MAX98373_R2026_PCM_CLOCK_RATIO,
0209 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
0210 value);
0211 }
0212 return 0;
0213 }
0214
0215 static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
0216 struct snd_pcm_hw_params *params,
0217 struct snd_soc_dai *dai)
0218 {
0219 struct snd_soc_component *component = dai->component;
0220 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0221 unsigned int sampling_rate = 0;
0222 unsigned int chan_sz = 0;
0223
0224
0225 switch (snd_pcm_format_width(params_format(params))) {
0226 case 16:
0227 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
0228 break;
0229 case 24:
0230 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
0231 break;
0232 case 32:
0233 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
0234 break;
0235 default:
0236 dev_err(component->dev, "format unsupported %d\n",
0237 params_format(params));
0238 goto err;
0239 }
0240
0241 max98373->ch_size = snd_pcm_format_width(params_format(params));
0242
0243 regmap_update_bits(max98373->regmap,
0244 MAX98373_R2024_PCM_DATA_FMT_CFG,
0245 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0246
0247 dev_dbg(component->dev, "format supported %d",
0248 params_format(params));
0249
0250
0251 switch (params_rate(params)) {
0252 case 8000:
0253 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
0254 break;
0255 case 11025:
0256 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
0257 break;
0258 case 12000:
0259 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
0260 break;
0261 case 16000:
0262 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
0263 break;
0264 case 22050:
0265 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
0266 break;
0267 case 24000:
0268 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
0269 break;
0270 case 32000:
0271 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
0272 break;
0273 case 44100:
0274 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
0275 break;
0276 case 48000:
0277 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
0278 break;
0279 case 88200:
0280 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
0281 break;
0282 case 96000:
0283 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
0284 break;
0285 default:
0286 dev_err(component->dev, "rate %d not supported\n",
0287 params_rate(params));
0288 goto err;
0289 }
0290
0291
0292 regmap_update_bits(max98373->regmap,
0293 MAX98373_R2027_PCM_SR_SETUP_1,
0294 MAX98373_PCM_SR_SET1_SR_MASK,
0295 sampling_rate);
0296 regmap_update_bits(max98373->regmap,
0297 MAX98373_R2028_PCM_SR_SETUP_2,
0298 MAX98373_PCM_SR_SET2_SR_MASK,
0299 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
0300
0301
0302 if (max98373->interleave_mode &&
0303 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
0304 regmap_update_bits(max98373->regmap,
0305 MAX98373_R2028_PCM_SR_SETUP_2,
0306 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
0307 sampling_rate - 3);
0308 else
0309 regmap_update_bits(max98373->regmap,
0310 MAX98373_R2028_PCM_SR_SETUP_2,
0311 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
0312 sampling_rate);
0313
0314 return max98373_set_clock(component, params);
0315 err:
0316 return -EINVAL;
0317 }
0318
0319 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
0320 unsigned int tx_mask, unsigned int rx_mask,
0321 int slots, int slot_width)
0322 {
0323 struct snd_soc_component *component = dai->component;
0324 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
0325 int bsel = 0;
0326 unsigned int chan_sz = 0;
0327 unsigned int mask;
0328 int x, slot_found;
0329
0330 if (!tx_mask && !rx_mask && !slots && !slot_width)
0331 max98373->tdm_mode = false;
0332 else
0333 max98373->tdm_mode = true;
0334
0335
0336 bsel = max98373_get_bclk_sel(slots * slot_width);
0337 if (bsel == 0) {
0338 dev_err(component->dev, "BCLK %d not supported\n",
0339 slots * slot_width);
0340 return -EINVAL;
0341 }
0342
0343 regmap_update_bits(max98373->regmap,
0344 MAX98373_R2026_PCM_CLOCK_RATIO,
0345 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
0346 bsel);
0347
0348
0349 switch (slot_width) {
0350 case 16:
0351 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
0352 break;
0353 case 24:
0354 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
0355 break;
0356 case 32:
0357 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
0358 break;
0359 default:
0360 dev_err(component->dev, "format unsupported %d\n",
0361 slot_width);
0362 return -EINVAL;
0363 }
0364
0365 regmap_update_bits(max98373->regmap,
0366 MAX98373_R2024_PCM_DATA_FMT_CFG,
0367 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
0368
0369
0370 slot_found = 0;
0371 mask = rx_mask;
0372 for (x = 0 ; x < 16 ; x++, mask >>= 1) {
0373 if (mask & 0x1) {
0374 if (slot_found == 0)
0375 regmap_update_bits(max98373->regmap,
0376 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0377 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
0378 else
0379 regmap_write(max98373->regmap,
0380 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0381 x);
0382 slot_found++;
0383 if (slot_found > 1)
0384 break;
0385 }
0386 }
0387
0388
0389 regmap_write(max98373->regmap,
0390 MAX98373_R2020_PCM_TX_HIZ_EN_1,
0391 ~tx_mask & 0xFF);
0392 regmap_write(max98373->regmap,
0393 MAX98373_R2021_PCM_TX_HIZ_EN_2,
0394 (~tx_mask & 0xFF00) >> 8);
0395
0396 return 0;
0397 }
0398
0399 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
0400
0401 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0402 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0403
0404 static const struct snd_soc_dai_ops max98373_dai_ops = {
0405 .set_fmt = max98373_dai_set_fmt,
0406 .hw_params = max98373_dai_hw_params,
0407 .set_tdm_slot = max98373_dai_tdm_slot,
0408 };
0409
0410 static bool max98373_readable_register(struct device *dev, unsigned int reg)
0411 {
0412 switch (reg) {
0413 case MAX98373_R2000_SW_RESET:
0414 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
0415 case MAX98373_R2010_IRQ_CTRL:
0416 case MAX98373_R2014_THERM_WARN_THRESH
0417 ... MAX98373_R2018_THERM_FOLDBACK_EN:
0418 case MAX98373_R201E_PIN_DRIVE_STRENGTH
0419 ... MAX98373_R2036_SOUNDWIRE_CTRL:
0420 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
0421 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
0422 ... MAX98373_R2047_IV_SENSE_ADC_EN:
0423 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
0424 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
0425 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
0426 case MAX98373_R2097_BDE_L1_THRESH
0427 ... MAX98373_R209B_BDE_THRESH_HYST:
0428 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
0429 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
0430 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
0431 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
0432 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
0433 ... MAX98373_R20FF_GLOBAL_SHDN:
0434 case MAX98373_R21FF_REV_ID:
0435 return true;
0436 default:
0437 return false;
0438 }
0439 };
0440
0441 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
0442 {
0443 switch (reg) {
0444 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
0445 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
0446 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
0447 case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
0448 case MAX98373_R20FF_GLOBAL_SHDN:
0449 case MAX98373_R21FF_REV_ID:
0450 return true;
0451 default:
0452 return false;
0453 }
0454 }
0455
0456 static struct snd_soc_dai_driver max98373_dai[] = {
0457 {
0458 .name = "max98373-aif1",
0459 .playback = {
0460 .stream_name = "HiFi Playback",
0461 .channels_min = 1,
0462 .channels_max = 2,
0463 .rates = MAX98373_RATES,
0464 .formats = MAX98373_FORMATS,
0465 },
0466 .capture = {
0467 .stream_name = "HiFi Capture",
0468 .channels_min = 1,
0469 .channels_max = 2,
0470 .rates = MAX98373_RATES,
0471 .formats = MAX98373_FORMATS,
0472 },
0473 .ops = &max98373_dai_ops,
0474 }
0475 };
0476
0477 #ifdef CONFIG_PM_SLEEP
0478 static int max98373_suspend(struct device *dev)
0479 {
0480 struct max98373_priv *max98373 = dev_get_drvdata(dev);
0481 int i;
0482
0483
0484 for (i = 0; i < max98373->cache_num; i++)
0485 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
0486
0487 regcache_cache_only(max98373->regmap, true);
0488 regcache_mark_dirty(max98373->regmap);
0489 return 0;
0490 }
0491
0492 static int max98373_resume(struct device *dev)
0493 {
0494 struct max98373_priv *max98373 = dev_get_drvdata(dev);
0495
0496 regcache_cache_only(max98373->regmap, false);
0497 max98373_reset(max98373, dev);
0498 regcache_sync(max98373->regmap);
0499 return 0;
0500 }
0501 #endif
0502
0503 static const struct dev_pm_ops max98373_pm = {
0504 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
0505 };
0506
0507 static const struct regmap_config max98373_regmap = {
0508 .reg_bits = 16,
0509 .val_bits = 8,
0510 .max_register = MAX98373_R21FF_REV_ID,
0511 .reg_defaults = max98373_reg,
0512 .num_reg_defaults = ARRAY_SIZE(max98373_reg),
0513 .readable_reg = max98373_readable_register,
0514 .volatile_reg = max98373_volatile_reg,
0515 .cache_type = REGCACHE_RBTREE,
0516 };
0517
0518 static int max98373_i2c_probe(struct i2c_client *i2c)
0519 {
0520 int ret = 0;
0521 int reg = 0;
0522 int i;
0523 struct max98373_priv *max98373 = NULL;
0524
0525 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
0526
0527 if (!max98373) {
0528 ret = -ENOMEM;
0529 return ret;
0530 }
0531 i2c_set_clientdata(i2c, max98373);
0532
0533
0534 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
0535 max98373->interleave_mode = true;
0536 else
0537 max98373->interleave_mode = false;
0538
0539
0540 max98373->regmap = devm_regmap_init_i2c(i2c, &max98373_regmap);
0541 if (IS_ERR(max98373->regmap)) {
0542 ret = PTR_ERR(max98373->regmap);
0543 dev_err(&i2c->dev,
0544 "Failed to allocate regmap: %d\n", ret);
0545 return ret;
0546 }
0547
0548 max98373->cache_num = ARRAY_SIZE(max98373_i2c_cache_reg);
0549 max98373->cache = devm_kcalloc(&i2c->dev, max98373->cache_num,
0550 sizeof(*max98373->cache),
0551 GFP_KERNEL);
0552
0553 for (i = 0; i < max98373->cache_num; i++)
0554 max98373->cache[i].reg = max98373_i2c_cache_reg[i];
0555
0556
0557 max98373_slot_config(&i2c->dev, max98373);
0558
0559
0560 if (gpio_is_valid(max98373->reset_gpio)) {
0561 ret = devm_gpio_request(&i2c->dev, max98373->reset_gpio,
0562 "MAX98373_RESET");
0563 if (ret) {
0564 dev_err(&i2c->dev, "%s: Failed to request gpio %d\n",
0565 __func__, max98373->reset_gpio);
0566 return -EINVAL;
0567 }
0568 gpio_direction_output(max98373->reset_gpio, 0);
0569 msleep(50);
0570 gpio_direction_output(max98373->reset_gpio, 1);
0571 msleep(20);
0572 }
0573
0574
0575 ret = regmap_read(max98373->regmap,
0576 MAX98373_R21FF_REV_ID, ®);
0577 if (ret < 0) {
0578 dev_err(&i2c->dev,
0579 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
0580 return ret;
0581 }
0582 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
0583
0584
0585 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
0586 max98373_dai, ARRAY_SIZE(max98373_dai));
0587 if (ret < 0)
0588 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
0589
0590 return ret;
0591 }
0592
0593 static const struct i2c_device_id max98373_i2c_id[] = {
0594 { "max98373", 0},
0595 { },
0596 };
0597
0598 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
0599
0600 #if defined(CONFIG_OF)
0601 static const struct of_device_id max98373_of_match[] = {
0602 { .compatible = "maxim,max98373", },
0603 { }
0604 };
0605 MODULE_DEVICE_TABLE(of, max98373_of_match);
0606 #endif
0607
0608 #ifdef CONFIG_ACPI
0609 static const struct acpi_device_id max98373_acpi_match[] = {
0610 { "MX98373", 0 },
0611 {},
0612 };
0613 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
0614 #endif
0615
0616 static struct i2c_driver max98373_i2c_driver = {
0617 .driver = {
0618 .name = "max98373",
0619 .of_match_table = of_match_ptr(max98373_of_match),
0620 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
0621 .pm = &max98373_pm,
0622 },
0623 .probe_new = max98373_i2c_probe,
0624 .id_table = max98373_i2c_id,
0625 };
0626
0627 module_i2c_driver(max98373_i2c_driver)
0628
0629 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
0630 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
0631 MODULE_LICENSE("GPL");
