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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * max98095.c -- MAX98095 ALSA SoC Audio driver
0004  *
0005  * Copyright 2011 Maxim Integrated Products
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/moduleparam.h>
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/clk.h>
0016 #include <linux/mutex.h>
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/soc.h>
0021 #include <sound/initval.h>
0022 #include <sound/tlv.h>
0023 #include <linux/slab.h>
0024 #include <asm/div64.h>
0025 #include <sound/max98095.h>
0026 #include <sound/jack.h>
0027 #include "max98095.h"
0028 
0029 enum max98095_type {
0030     MAX98095,
0031 };
0032 
0033 struct max98095_cdata {
0034     unsigned int rate;
0035     unsigned int fmt;
0036     int eq_sel;
0037     int bq_sel;
0038 };
0039 
0040 struct max98095_priv {
0041     struct regmap *regmap;
0042     enum max98095_type devtype;
0043     struct max98095_pdata *pdata;
0044     struct clk *mclk;
0045     unsigned int sysclk;
0046     struct max98095_cdata dai[3];
0047     const char **eq_texts;
0048     const char **bq_texts;
0049     struct soc_enum eq_enum;
0050     struct soc_enum bq_enum;
0051     int eq_textcnt;
0052     int bq_textcnt;
0053     u8 lin_state;
0054     unsigned int mic1pre;
0055     unsigned int mic2pre;
0056     struct snd_soc_jack *headphone_jack;
0057     struct snd_soc_jack *mic_jack;
0058     struct mutex lock;
0059 };
0060 
0061 static const struct reg_default max98095_reg_def[] = {
0062     {  0xf, 0x00 }, /* 0F */
0063     { 0x10, 0x00 }, /* 10 */
0064     { 0x11, 0x00 }, /* 11 */
0065     { 0x12, 0x00 }, /* 12 */
0066     { 0x13, 0x00 }, /* 13 */
0067     { 0x14, 0x00 }, /* 14 */
0068     { 0x15, 0x00 }, /* 15 */
0069     { 0x16, 0x00 }, /* 16 */
0070     { 0x17, 0x00 }, /* 17 */
0071     { 0x18, 0x00 }, /* 18 */
0072     { 0x19, 0x00 }, /* 19 */
0073     { 0x1a, 0x00 }, /* 1A */
0074     { 0x1b, 0x00 }, /* 1B */
0075     { 0x1c, 0x00 }, /* 1C */
0076     { 0x1d, 0x00 }, /* 1D */
0077     { 0x1e, 0x00 }, /* 1E */
0078     { 0x1f, 0x00 }, /* 1F */
0079     { 0x20, 0x00 }, /* 20 */
0080     { 0x21, 0x00 }, /* 21 */
0081     { 0x22, 0x00 }, /* 22 */
0082     { 0x23, 0x00 }, /* 23 */
0083     { 0x24, 0x00 }, /* 24 */
0084     { 0x25, 0x00 }, /* 25 */
0085     { 0x26, 0x00 }, /* 26 */
0086     { 0x27, 0x00 }, /* 27 */
0087     { 0x28, 0x00 }, /* 28 */
0088     { 0x29, 0x00 }, /* 29 */
0089     { 0x2a, 0x00 }, /* 2A */
0090     { 0x2b, 0x00 }, /* 2B */
0091     { 0x2c, 0x00 }, /* 2C */
0092     { 0x2d, 0x00 }, /* 2D */
0093     { 0x2e, 0x00 }, /* 2E */
0094     { 0x2f, 0x00 }, /* 2F */
0095     { 0x30, 0x00 }, /* 30 */
0096     { 0x31, 0x00 }, /* 31 */
0097     { 0x32, 0x00 }, /* 32 */
0098     { 0x33, 0x00 }, /* 33 */
0099     { 0x34, 0x00 }, /* 34 */
0100     { 0x35, 0x00 }, /* 35 */
0101     { 0x36, 0x00 }, /* 36 */
0102     { 0x37, 0x00 }, /* 37 */
0103     { 0x38, 0x00 }, /* 38 */
0104     { 0x39, 0x00 }, /* 39 */
0105     { 0x3a, 0x00 }, /* 3A */
0106     { 0x3b, 0x00 }, /* 3B */
0107     { 0x3c, 0x00 }, /* 3C */
0108     { 0x3d, 0x00 }, /* 3D */
0109     { 0x3e, 0x00 }, /* 3E */
0110     { 0x3f, 0x00 }, /* 3F */
0111     { 0x40, 0x00 }, /* 40 */
0112     { 0x41, 0x00 }, /* 41 */
0113     { 0x42, 0x00 }, /* 42 */
0114     { 0x43, 0x00 }, /* 43 */
0115     { 0x44, 0x00 }, /* 44 */
0116     { 0x45, 0x00 }, /* 45 */
0117     { 0x46, 0x00 }, /* 46 */
0118     { 0x47, 0x00 }, /* 47 */
0119     { 0x48, 0x00 }, /* 48 */
0120     { 0x49, 0x00 }, /* 49 */
0121     { 0x4a, 0x00 }, /* 4A */
0122     { 0x4b, 0x00 }, /* 4B */
0123     { 0x4c, 0x00 }, /* 4C */
0124     { 0x4d, 0x00 }, /* 4D */
0125     { 0x4e, 0x00 }, /* 4E */
0126     { 0x4f, 0x00 }, /* 4F */
0127     { 0x50, 0x00 }, /* 50 */
0128     { 0x51, 0x00 }, /* 51 */
0129     { 0x52, 0x00 }, /* 52 */
0130     { 0x53, 0x00 }, /* 53 */
0131     { 0x54, 0x00 }, /* 54 */
0132     { 0x55, 0x00 }, /* 55 */
0133     { 0x56, 0x00 }, /* 56 */
0134     { 0x57, 0x00 }, /* 57 */
0135     { 0x58, 0x00 }, /* 58 */
0136     { 0x59, 0x00 }, /* 59 */
0137     { 0x5a, 0x00 }, /* 5A */
0138     { 0x5b, 0x00 }, /* 5B */
0139     { 0x5c, 0x00 }, /* 5C */
0140     { 0x5d, 0x00 }, /* 5D */
0141     { 0x5e, 0x00 }, /* 5E */
0142     { 0x5f, 0x00 }, /* 5F */
0143     { 0x60, 0x00 }, /* 60 */
0144     { 0x61, 0x00 }, /* 61 */
0145     { 0x62, 0x00 }, /* 62 */
0146     { 0x63, 0x00 }, /* 63 */
0147     { 0x64, 0x00 }, /* 64 */
0148     { 0x65, 0x00 }, /* 65 */
0149     { 0x66, 0x00 }, /* 66 */
0150     { 0x67, 0x00 }, /* 67 */
0151     { 0x68, 0x00 }, /* 68 */
0152     { 0x69, 0x00 }, /* 69 */
0153     { 0x6a, 0x00 }, /* 6A */
0154     { 0x6b, 0x00 }, /* 6B */
0155     { 0x6c, 0x00 }, /* 6C */
0156     { 0x6d, 0x00 }, /* 6D */
0157     { 0x6e, 0x00 }, /* 6E */
0158     { 0x6f, 0x00 }, /* 6F */
0159     { 0x70, 0x00 }, /* 70 */
0160     { 0x71, 0x00 }, /* 71 */
0161     { 0x72, 0x00 }, /* 72 */
0162     { 0x73, 0x00 }, /* 73 */
0163     { 0x74, 0x00 }, /* 74 */
0164     { 0x75, 0x00 }, /* 75 */
0165     { 0x76, 0x00 }, /* 76 */
0166     { 0x77, 0x00 }, /* 77 */
0167     { 0x78, 0x00 }, /* 78 */
0168     { 0x79, 0x00 }, /* 79 */
0169     { 0x7a, 0x00 }, /* 7A */
0170     { 0x7b, 0x00 }, /* 7B */
0171     { 0x7c, 0x00 }, /* 7C */
0172     { 0x7d, 0x00 }, /* 7D */
0173     { 0x7e, 0x00 }, /* 7E */
0174     { 0x7f, 0x00 }, /* 7F */
0175     { 0x80, 0x00 }, /* 80 */
0176     { 0x81, 0x00 }, /* 81 */
0177     { 0x82, 0x00 }, /* 82 */
0178     { 0x83, 0x00 }, /* 83 */
0179     { 0x84, 0x00 }, /* 84 */
0180     { 0x85, 0x00 }, /* 85 */
0181     { 0x86, 0x00 }, /* 86 */
0182     { 0x87, 0x00 }, /* 87 */
0183     { 0x88, 0x00 }, /* 88 */
0184     { 0x89, 0x00 }, /* 89 */
0185     { 0x8a, 0x00 }, /* 8A */
0186     { 0x8b, 0x00 }, /* 8B */
0187     { 0x8c, 0x00 }, /* 8C */
0188     { 0x8d, 0x00 }, /* 8D */
0189     { 0x8e, 0x00 }, /* 8E */
0190     { 0x8f, 0x00 }, /* 8F */
0191     { 0x90, 0x00 }, /* 90 */
0192     { 0x91, 0x00 }, /* 91 */
0193     { 0x92, 0x30 }, /* 92 */
0194     { 0x93, 0xF0 }, /* 93 */
0195     { 0x94, 0x00 }, /* 94 */
0196     { 0x95, 0x00 }, /* 95 */
0197     { 0x96, 0x3F }, /* 96 */
0198     { 0x97, 0x00 }, /* 97 */
0199     { 0xff, 0x00 }, /* FF */
0200 };
0201 
0202 static bool max98095_readable(struct device *dev, unsigned int reg)
0203 {
0204     switch (reg) {
0205     case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
0206     case M98095_0FF_REV_ID:
0207         return true;
0208     default:
0209         return false;
0210     }
0211 }
0212 
0213 static bool max98095_writeable(struct device *dev, unsigned int reg)
0214 {
0215     switch (reg) {
0216     case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
0217         return true;
0218     default:
0219         return false;
0220     }
0221 }
0222 
0223 static bool max98095_volatile(struct device *dev, unsigned int reg)
0224 {
0225     switch (reg) {
0226     case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
0227     case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
0228         return true;
0229     default:
0230         return false;
0231     }
0232 }
0233 
0234 static const struct regmap_config max98095_regmap = {
0235     .reg_bits = 8,
0236     .val_bits = 8,
0237 
0238     .reg_defaults = max98095_reg_def,
0239     .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
0240     .max_register = M98095_0FF_REV_ID,
0241     .cache_type = REGCACHE_RBTREE,
0242 
0243     .readable_reg = max98095_readable,
0244     .writeable_reg = max98095_writeable,
0245     .volatile_reg = max98095_volatile,
0246 };
0247 
0248 /*
0249  * Load equalizer DSP coefficient configurations registers
0250  */
0251 static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
0252             unsigned int band, u16 *coefs)
0253 {
0254     unsigned int eq_reg;
0255     unsigned int i;
0256 
0257     if (WARN_ON(band > 4) ||
0258         WARN_ON(dai > 1))
0259         return;
0260 
0261     /* Load the base register address */
0262     eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
0263 
0264     /* Add the band address offset, note adjustment for word address */
0265     eq_reg += band * (M98095_COEFS_PER_BAND << 1);
0266 
0267     /* Step through the registers and coefs */
0268     for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
0269         snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
0270         snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
0271     }
0272 }
0273 
0274 /*
0275  * Load biquad filter coefficient configurations registers
0276  */
0277 static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
0278             unsigned int band, u16 *coefs)
0279 {
0280     unsigned int bq_reg;
0281     unsigned int i;
0282 
0283     if (WARN_ON(band > 1) ||
0284         WARN_ON(dai > 1))
0285         return;
0286 
0287     /* Load the base register address */
0288     bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
0289 
0290     /* Add the band address offset, note adjustment for word address */
0291     bq_reg += band * (M98095_COEFS_PER_BAND << 1);
0292 
0293     /* Step through the registers and coefs */
0294     for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
0295         snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
0296         snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
0297     }
0298 }
0299 
0300 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
0301 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
0302                 M98095_02E_DAI1_FILTERS, 7,
0303                 max98095_fltr_mode);
0304 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
0305                 M98095_038_DAI2_FILTERS, 7,
0306                 max98095_fltr_mode);
0307 
0308 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
0309 
0310 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
0311                 M98095_087_CFG_MIC, 0,
0312                 max98095_extmic_text);
0313 
0314 static const struct snd_kcontrol_new max98095_extmic_mux =
0315     SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
0316 
0317 static const char * const max98095_linein_text[] = { "INA", "INB" };
0318 
0319 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
0320                 M98095_086_CFG_LINE, 6,
0321                 max98095_linein_text);
0322 
0323 static const struct snd_kcontrol_new max98095_linein_mux =
0324     SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
0325 
0326 static const char * const max98095_line_mode_text[] = {
0327     "Stereo", "Differential"};
0328 
0329 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
0330                 M98095_086_CFG_LINE, 7,
0331                 max98095_line_mode_text);
0332 
0333 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
0334                 M98095_086_CFG_LINE, 4,
0335                 max98095_line_mode_text);
0336 
0337 static const char * const max98095_dai_fltr[] = {
0338     "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
0339     "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
0340 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
0341                 M98095_02E_DAI1_FILTERS, 0,
0342                 max98095_dai_fltr);
0343 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
0344                 M98095_038_DAI2_FILTERS, 0,
0345                 max98095_dai_fltr);
0346 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
0347                 M98095_042_DAI3_FILTERS, 0,
0348                 max98095_dai_fltr);
0349 
0350 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
0351                 struct snd_ctl_elem_value *ucontrol)
0352 {
0353     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0354     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0355     unsigned int sel = ucontrol->value.integer.value[0];
0356 
0357     max98095->mic1pre = sel;
0358     snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
0359         (1+sel)<<M98095_MICPRE_SHIFT);
0360 
0361     return 0;
0362 }
0363 
0364 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
0365                 struct snd_ctl_elem_value *ucontrol)
0366 {
0367     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0368     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0369 
0370     ucontrol->value.integer.value[0] = max98095->mic1pre;
0371     return 0;
0372 }
0373 
0374 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
0375                 struct snd_ctl_elem_value *ucontrol)
0376 {
0377     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0378     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0379     unsigned int sel = ucontrol->value.integer.value[0];
0380 
0381     max98095->mic2pre = sel;
0382     snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
0383         (1+sel)<<M98095_MICPRE_SHIFT);
0384 
0385     return 0;
0386 }
0387 
0388 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
0389                 struct snd_ctl_elem_value *ucontrol)
0390 {
0391     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0392     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0393 
0394     ucontrol->value.integer.value[0] = max98095->mic2pre;
0395     return 0;
0396 }
0397 
0398 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
0399     0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
0400     2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
0401 );
0402 
0403 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
0404 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
0405 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
0406 
0407 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
0408     0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
0409     7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
0410     15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
0411     22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
0412     28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
0413 );
0414 
0415 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
0416     0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
0417     11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
0418     19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
0419     28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
0420 );
0421 
0422 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
0423     0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
0424     7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
0425     15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0426     22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
0427     28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
0428 );
0429 
0430 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
0431     0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
0432     3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
0433     4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
0434 );
0435 
0436 static const struct snd_kcontrol_new max98095_snd_controls[] = {
0437 
0438     SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
0439         M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
0440 
0441     SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
0442         M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
0443 
0444     SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
0445         0, 31, 0, max98095_rcv_lout_tlv),
0446 
0447     SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
0448         M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
0449 
0450     SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
0451         M98095_065_LVL_HP_R, 7, 1, 1),
0452 
0453     SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
0454         M98095_068_LVL_SPK_R, 7, 1, 1),
0455 
0456     SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
0457 
0458     SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
0459         M98095_063_LVL_LINEOUT2, 7, 1, 1),
0460 
0461     SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
0462         max98095_mic_tlv),
0463 
0464     SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
0465         max98095_mic_tlv),
0466 
0467     SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
0468             M98095_05F_LVL_MIC1, 5, 2, 0,
0469             max98095_mic1pre_get, max98095_mic1pre_set,
0470             max98095_micboost_tlv),
0471     SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
0472             M98095_060_LVL_MIC2, 5, 2, 0,
0473             max98095_mic2pre_get, max98095_mic2pre_set,
0474             max98095_micboost_tlv),
0475 
0476     SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
0477         max98095_lin_tlv),
0478 
0479     SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
0480         max98095_adc_tlv),
0481     SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
0482         max98095_adc_tlv),
0483 
0484     SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
0485         max98095_adcboost_tlv),
0486     SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
0487         max98095_adcboost_tlv),
0488 
0489     SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
0490     SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
0491 
0492     SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
0493     SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
0494 
0495     SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
0496     SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
0497     SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
0498     SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
0499     SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
0500 
0501     SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
0502     SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
0503 };
0504 
0505 /* Left speaker mixer switch */
0506 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
0507     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
0508     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
0509     SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
0510     SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
0511     SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
0512     SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
0513     SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
0514     SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
0515 };
0516 
0517 /* Right speaker mixer switch */
0518 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
0519     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
0520     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
0521     SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
0522     SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
0523     SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
0524     SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
0525     SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
0526     SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
0527 };
0528 
0529 /* Left headphone mixer switch */
0530 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
0531     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
0532     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
0533     SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
0534     SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
0535     SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
0536     SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
0537 };
0538 
0539 /* Right headphone mixer switch */
0540 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
0541     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
0542     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
0543     SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
0544     SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
0545     SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
0546     SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
0547 };
0548 
0549 /* Receiver earpiece mixer switch */
0550 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
0551     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
0552     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
0553     SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
0554     SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
0555     SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
0556     SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
0557 };
0558 
0559 /* Left lineout mixer switch */
0560 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
0561     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
0562     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
0563     SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
0564     SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
0565     SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
0566     SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
0567 };
0568 
0569 /* Right lineout mixer switch */
0570 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
0571     SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
0572     SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
0573     SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
0574     SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
0575     SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
0576     SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
0577 };
0578 
0579 /* Left ADC mixer switch */
0580 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
0581     SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
0582     SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
0583     SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
0584     SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
0585 };
0586 
0587 /* Right ADC mixer switch */
0588 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
0589     SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
0590     SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
0591     SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
0592     SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
0593 };
0594 
0595 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
0596                  struct snd_kcontrol *kcontrol, int event)
0597 {
0598     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0599     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0600 
0601     switch (event) {
0602     case SND_SOC_DAPM_POST_PMU:
0603         if (w->reg == M98095_05F_LVL_MIC1) {
0604             snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
0605                 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
0606         } else {
0607             snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
0608                 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
0609         }
0610         break;
0611     case SND_SOC_DAPM_POST_PMD:
0612         snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
0613         break;
0614     default:
0615         return -EINVAL;
0616     }
0617 
0618     return 0;
0619 }
0620 
0621 /*
0622  * The line inputs are stereo inputs with the left and right
0623  * channels sharing a common PGA power control signal.
0624  */
0625 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
0626                  int event, u8 channel)
0627 {
0628     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0629     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0630     u8 *state;
0631 
0632     if (WARN_ON(!(channel == 1 || channel == 2)))
0633         return -EINVAL;
0634 
0635     state = &max98095->lin_state;
0636 
0637     switch (event) {
0638     case SND_SOC_DAPM_POST_PMU:
0639         *state |= channel;
0640         snd_soc_component_update_bits(component, w->reg,
0641             (1 << w->shift), (1 << w->shift));
0642         break;
0643     case SND_SOC_DAPM_POST_PMD:
0644         *state &= ~channel;
0645         if (*state == 0) {
0646             snd_soc_component_update_bits(component, w->reg,
0647                 (1 << w->shift), 0);
0648         }
0649         break;
0650     default:
0651         return -EINVAL;
0652     }
0653 
0654     return 0;
0655 }
0656 
0657 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
0658                    struct snd_kcontrol *k, int event)
0659 {
0660     return max98095_line_pga(w, event, 1);
0661 }
0662 
0663 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
0664                    struct snd_kcontrol *k, int event)
0665 {
0666     return max98095_line_pga(w, event, 2);
0667 }
0668 
0669 /*
0670  * The stereo line out mixer outputs to two stereo line outs.
0671  * The 2nd pair has a separate set of enables.
0672  */
0673 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
0674                  struct snd_kcontrol *kcontrol, int event)
0675 {
0676     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0677 
0678     switch (event) {
0679     case SND_SOC_DAPM_POST_PMU:
0680         snd_soc_component_update_bits(component, w->reg,
0681             (1 << (w->shift+2)), (1 << (w->shift+2)));
0682         break;
0683     case SND_SOC_DAPM_POST_PMD:
0684         snd_soc_component_update_bits(component, w->reg,
0685             (1 << (w->shift+2)), 0);
0686         break;
0687     default:
0688         return -EINVAL;
0689     }
0690 
0691     return 0;
0692 }
0693 
0694 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
0695 
0696     SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
0697     SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
0698 
0699     SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
0700         M98095_091_PWR_EN_OUT, 0, 0),
0701     SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
0702         M98095_091_PWR_EN_OUT, 1, 0),
0703     SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
0704         M98095_091_PWR_EN_OUT, 2, 0),
0705     SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
0706         M98095_091_PWR_EN_OUT, 2, 0),
0707 
0708     SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
0709         6, 0, NULL, 0),
0710     SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
0711         7, 0, NULL, 0),
0712 
0713     SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
0714         4, 0, NULL, 0),
0715     SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
0716         5, 0, NULL, 0),
0717 
0718     SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
0719         3, 0, NULL, 0),
0720 
0721     SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
0722         0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
0723     SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
0724         1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
0725 
0726     SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
0727         &max98095_extmic_mux),
0728 
0729     SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
0730         &max98095_linein_mux),
0731 
0732     SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
0733         &max98095_left_hp_mixer_controls[0],
0734         ARRAY_SIZE(max98095_left_hp_mixer_controls)),
0735 
0736     SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
0737         &max98095_right_hp_mixer_controls[0],
0738         ARRAY_SIZE(max98095_right_hp_mixer_controls)),
0739 
0740     SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
0741         &max98095_left_speaker_mixer_controls[0],
0742         ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
0743 
0744     SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
0745         &max98095_right_speaker_mixer_controls[0],
0746         ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
0747 
0748     SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
0749       &max98095_mono_rcv_mixer_controls[0],
0750         ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
0751 
0752     SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
0753         &max98095_left_lineout_mixer_controls[0],
0754         ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
0755 
0756     SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
0757         &max98095_right_lineout_mixer_controls[0],
0758         ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
0759 
0760     SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
0761         &max98095_left_ADC_mixer_controls[0],
0762         ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
0763 
0764     SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
0765         &max98095_right_ADC_mixer_controls[0],
0766         ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
0767 
0768     SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
0769         5, 0, NULL, 0, max98095_mic_event,
0770         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0771 
0772     SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
0773         5, 0, NULL, 0, max98095_mic_event,
0774         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0775 
0776     SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
0777         7, 0, NULL, 0, max98095_pga_in1_event,
0778         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0779 
0780     SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
0781         7, 0, NULL, 0, max98095_pga_in2_event,
0782         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0783 
0784     SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
0785     SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
0786 
0787     SND_SOC_DAPM_OUTPUT("HPL"),
0788     SND_SOC_DAPM_OUTPUT("HPR"),
0789     SND_SOC_DAPM_OUTPUT("SPKL"),
0790     SND_SOC_DAPM_OUTPUT("SPKR"),
0791     SND_SOC_DAPM_OUTPUT("RCV"),
0792     SND_SOC_DAPM_OUTPUT("OUT1"),
0793     SND_SOC_DAPM_OUTPUT("OUT2"),
0794     SND_SOC_DAPM_OUTPUT("OUT3"),
0795     SND_SOC_DAPM_OUTPUT("OUT4"),
0796 
0797     SND_SOC_DAPM_INPUT("MIC1"),
0798     SND_SOC_DAPM_INPUT("MIC2"),
0799     SND_SOC_DAPM_INPUT("INA1"),
0800     SND_SOC_DAPM_INPUT("INA2"),
0801     SND_SOC_DAPM_INPUT("INB1"),
0802     SND_SOC_DAPM_INPUT("INB2"),
0803 };
0804 
0805 static const struct snd_soc_dapm_route max98095_audio_map[] = {
0806     /* Left headphone output mixer */
0807     {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
0808     {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
0809     {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
0810     {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
0811     {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
0812     {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
0813 
0814     /* Right headphone output mixer */
0815     {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
0816     {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
0817     {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
0818     {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
0819     {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
0820     {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
0821 
0822     /* Left speaker output mixer */
0823     {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
0824     {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
0825     {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
0826     {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
0827     {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
0828     {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
0829     {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
0830     {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
0831 
0832     /* Right speaker output mixer */
0833     {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
0834     {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
0835     {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
0836     {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
0837     {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
0838     {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
0839     {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
0840     {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
0841 
0842     /* Earpiece/Receiver output mixer */
0843     {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
0844     {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
0845     {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
0846     {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
0847     {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
0848     {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
0849 
0850     /* Left Lineout output mixer */
0851     {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
0852     {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
0853     {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
0854     {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
0855     {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
0856     {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
0857 
0858     /* Right lineout output mixer */
0859     {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
0860     {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
0861     {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
0862     {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
0863     {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
0864     {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
0865 
0866     {"HP Left Out", NULL, "Left Headphone Mixer"},
0867     {"HP Right Out", NULL, "Right Headphone Mixer"},
0868     {"SPK Left Out", NULL, "Left Speaker Mixer"},
0869     {"SPK Right Out", NULL, "Right Speaker Mixer"},
0870     {"RCV Mono Out", NULL, "Receiver Mixer"},
0871     {"LINE Left Out", NULL, "Left Lineout Mixer"},
0872     {"LINE Right Out", NULL, "Right Lineout Mixer"},
0873 
0874     {"HPL", NULL, "HP Left Out"},
0875     {"HPR", NULL, "HP Right Out"},
0876     {"SPKL", NULL, "SPK Left Out"},
0877     {"SPKR", NULL, "SPK Right Out"},
0878     {"RCV", NULL, "RCV Mono Out"},
0879     {"OUT1", NULL, "LINE Left Out"},
0880     {"OUT2", NULL, "LINE Right Out"},
0881     {"OUT3", NULL, "LINE Left Out"},
0882     {"OUT4", NULL, "LINE Right Out"},
0883 
0884     /* Left ADC input mixer */
0885     {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
0886     {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
0887     {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
0888     {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
0889 
0890     /* Right ADC input mixer */
0891     {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
0892     {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
0893     {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
0894     {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
0895 
0896     /* Inputs */
0897     {"ADCL", NULL, "Left ADC Mixer"},
0898     {"ADCR", NULL, "Right ADC Mixer"},
0899 
0900     {"IN1 Input", NULL, "INA1"},
0901     {"IN2 Input", NULL, "INA2"},
0902 
0903     {"MIC1 Input", NULL, "MIC1"},
0904     {"MIC2 Input", NULL, "MIC2"},
0905 };
0906 
0907 /* codec mclk clock divider coefficients */
0908 static const struct {
0909     u32 rate;
0910     u8  sr;
0911 } rate_table[] = {
0912     {8000,  0x01},
0913     {11025, 0x02},
0914     {16000, 0x03},
0915     {22050, 0x04},
0916     {24000, 0x05},
0917     {32000, 0x06},
0918     {44100, 0x07},
0919     {48000, 0x08},
0920     {88200, 0x09},
0921     {96000, 0x0A},
0922 };
0923 
0924 static int rate_value(int rate, u8 *value)
0925 {
0926     int i;
0927 
0928     for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
0929         if (rate_table[i].rate >= rate) {
0930             *value = rate_table[i].sr;
0931             return 0;
0932         }
0933     }
0934     *value = rate_table[0].sr;
0935     return -EINVAL;
0936 }
0937 
0938 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
0939                    struct snd_pcm_hw_params *params,
0940                    struct snd_soc_dai *dai)
0941 {
0942     struct snd_soc_component *component = dai->component;
0943     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
0944     struct max98095_cdata *cdata;
0945     unsigned long long ni;
0946     unsigned int rate;
0947     u8 regval;
0948 
0949     cdata = &max98095->dai[0];
0950 
0951     rate = params_rate(params);
0952 
0953     switch (params_width(params)) {
0954     case 16:
0955         snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
0956             M98095_DAI_WS, 0);
0957         break;
0958     case 24:
0959         snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
0960             M98095_DAI_WS, M98095_DAI_WS);
0961         break;
0962     default:
0963         return -EINVAL;
0964     }
0965 
0966     if (rate_value(rate, &regval))
0967         return -EINVAL;
0968 
0969     snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
0970         M98095_CLKMODE_MASK, regval);
0971     cdata->rate = rate;
0972 
0973     /* Configure NI when operating as master */
0974     if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
0975         if (max98095->sysclk == 0) {
0976             dev_err(component->dev, "Invalid system clock frequency\n");
0977             return -EINVAL;
0978         }
0979         ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
0980                 * (unsigned long long int)rate;
0981         do_div(ni, (unsigned long long int)max98095->sysclk);
0982         snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
0983             (ni >> 8) & 0x7F);
0984         snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
0985             ni & 0xFF);
0986     }
0987 
0988     /* Update sample rate mode */
0989     if (rate < 50000)
0990         snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
0991             M98095_DAI_DHF, 0);
0992     else
0993         snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
0994             M98095_DAI_DHF, M98095_DAI_DHF);
0995 
0996     return 0;
0997 }
0998 
0999 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1000                    struct snd_pcm_hw_params *params,
1001                    struct snd_soc_dai *dai)
1002 {
1003     struct snd_soc_component *component = dai->component;
1004     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1005     struct max98095_cdata *cdata;
1006     unsigned long long ni;
1007     unsigned int rate;
1008     u8 regval;
1009 
1010     cdata = &max98095->dai[1];
1011 
1012     rate = params_rate(params);
1013 
1014     switch (params_width(params)) {
1015     case 16:
1016         snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1017             M98095_DAI_WS, 0);
1018         break;
1019     case 24:
1020         snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1021             M98095_DAI_WS, M98095_DAI_WS);
1022         break;
1023     default:
1024         return -EINVAL;
1025     }
1026 
1027     if (rate_value(rate, &regval))
1028         return -EINVAL;
1029 
1030     snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
1031         M98095_CLKMODE_MASK, regval);
1032     cdata->rate = rate;
1033 
1034     /* Configure NI when operating as master */
1035     if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1036         if (max98095->sysclk == 0) {
1037             dev_err(component->dev, "Invalid system clock frequency\n");
1038             return -EINVAL;
1039         }
1040         ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1041                 * (unsigned long long int)rate;
1042         do_div(ni, (unsigned long long int)max98095->sysclk);
1043         snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1044             (ni >> 8) & 0x7F);
1045         snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1046             ni & 0xFF);
1047     }
1048 
1049     /* Update sample rate mode */
1050     if (rate < 50000)
1051         snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1052             M98095_DAI_DHF, 0);
1053     else
1054         snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
1055             M98095_DAI_DHF, M98095_DAI_DHF);
1056 
1057     return 0;
1058 }
1059 
1060 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1061                    struct snd_pcm_hw_params *params,
1062                    struct snd_soc_dai *dai)
1063 {
1064     struct snd_soc_component *component = dai->component;
1065     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1066     struct max98095_cdata *cdata;
1067     unsigned long long ni;
1068     unsigned int rate;
1069     u8 regval;
1070 
1071     cdata = &max98095->dai[2];
1072 
1073     rate = params_rate(params);
1074 
1075     switch (params_width(params)) {
1076     case 16:
1077         snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1078             M98095_DAI_WS, 0);
1079         break;
1080     case 24:
1081         snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1082             M98095_DAI_WS, M98095_DAI_WS);
1083         break;
1084     default:
1085         return -EINVAL;
1086     }
1087 
1088     if (rate_value(rate, &regval))
1089         return -EINVAL;
1090 
1091     snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
1092         M98095_CLKMODE_MASK, regval);
1093     cdata->rate = rate;
1094 
1095     /* Configure NI when operating as master */
1096     if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1097         if (max98095->sysclk == 0) {
1098             dev_err(component->dev, "Invalid system clock frequency\n");
1099             return -EINVAL;
1100         }
1101         ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1102                 * (unsigned long long int)rate;
1103         do_div(ni, (unsigned long long int)max98095->sysclk);
1104         snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1105             (ni >> 8) & 0x7F);
1106         snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1107             ni & 0xFF);
1108     }
1109 
1110     /* Update sample rate mode */
1111     if (rate < 50000)
1112         snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1113             M98095_DAI_DHF, 0);
1114     else
1115         snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
1116             M98095_DAI_DHF, M98095_DAI_DHF);
1117 
1118     return 0;
1119 }
1120 
1121 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1122                    int clk_id, unsigned int freq, int dir)
1123 {
1124     struct snd_soc_component *component = dai->component;
1125     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1126 
1127     /* Requested clock frequency is already setup */
1128     if (freq == max98095->sysclk)
1129         return 0;
1130 
1131     if (!IS_ERR(max98095->mclk)) {
1132         freq = clk_round_rate(max98095->mclk, freq);
1133         clk_set_rate(max98095->mclk, freq);
1134     }
1135 
1136     /* Setup clocks for slave mode, and using the PLL
1137      * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1138      *         0x02 (when master clk is 20MHz to 40MHz)..
1139      *         0x03 (when master clk is 40MHz to 60MHz)..
1140      */
1141     if ((freq >= 10000000) && (freq < 20000000)) {
1142         snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
1143     } else if ((freq >= 20000000) && (freq < 40000000)) {
1144         snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
1145     } else if ((freq >= 40000000) && (freq < 60000000)) {
1146         snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
1147     } else {
1148         dev_err(component->dev, "Invalid master clock frequency\n");
1149         return -EINVAL;
1150     }
1151 
1152     dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1153 
1154     max98095->sysclk = freq;
1155     return 0;
1156 }
1157 
1158 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1159                  unsigned int fmt)
1160 {
1161     struct snd_soc_component *component = codec_dai->component;
1162     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1163     struct max98095_cdata *cdata;
1164     u8 regval = 0;
1165 
1166     cdata = &max98095->dai[0];
1167 
1168     if (fmt != cdata->fmt) {
1169         cdata->fmt = fmt;
1170 
1171         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1172         case SND_SOC_DAIFMT_CBC_CFC:
1173             /* Consumer mode PLL */
1174             snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
1175                 0x80);
1176             snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
1177                 0x00);
1178             break;
1179         case SND_SOC_DAIFMT_CBP_CFP:
1180             /* Set to provider mode */
1181             regval |= M98095_DAI_MAS;
1182             break;
1183         default:
1184             dev_err(component->dev, "Clock mode unsupported");
1185             return -EINVAL;
1186         }
1187 
1188         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1189         case SND_SOC_DAIFMT_I2S:
1190             regval |= M98095_DAI_DLY;
1191             break;
1192         case SND_SOC_DAIFMT_LEFT_J:
1193             break;
1194         default:
1195             return -EINVAL;
1196         }
1197 
1198         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1199         case SND_SOC_DAIFMT_NB_NF:
1200             break;
1201         case SND_SOC_DAIFMT_NB_IF:
1202             regval |= M98095_DAI_WCI;
1203             break;
1204         case SND_SOC_DAIFMT_IB_NF:
1205             regval |= M98095_DAI_BCI;
1206             break;
1207         case SND_SOC_DAIFMT_IB_IF:
1208             regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1209             break;
1210         default:
1211             return -EINVAL;
1212         }
1213 
1214         snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
1215             M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1216             M98095_DAI_WCI, regval);
1217 
1218         snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1219     }
1220 
1221     return 0;
1222 }
1223 
1224 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1225                  unsigned int fmt)
1226 {
1227     struct snd_soc_component *component = codec_dai->component;
1228     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1229     struct max98095_cdata *cdata;
1230     u8 regval = 0;
1231 
1232     cdata = &max98095->dai[1];
1233 
1234     if (fmt != cdata->fmt) {
1235         cdata->fmt = fmt;
1236 
1237         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1238         case SND_SOC_DAIFMT_CBC_CFC:
1239             /* Consumer mode PLL */
1240             snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
1241                 0x80);
1242             snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
1243                 0x00);
1244             break;
1245         case SND_SOC_DAIFMT_CBP_CFP:
1246             /* Set to provider mode */
1247             regval |= M98095_DAI_MAS;
1248             break;
1249         default:
1250             dev_err(component->dev, "Clock mode unsupported");
1251             return -EINVAL;
1252         }
1253 
1254         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1255         case SND_SOC_DAIFMT_I2S:
1256             regval |= M98095_DAI_DLY;
1257             break;
1258         case SND_SOC_DAIFMT_LEFT_J:
1259             break;
1260         default:
1261             return -EINVAL;
1262         }
1263 
1264         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1265         case SND_SOC_DAIFMT_NB_NF:
1266             break;
1267         case SND_SOC_DAIFMT_NB_IF:
1268             regval |= M98095_DAI_WCI;
1269             break;
1270         case SND_SOC_DAIFMT_IB_NF:
1271             regval |= M98095_DAI_BCI;
1272             break;
1273         case SND_SOC_DAIFMT_IB_IF:
1274             regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1275             break;
1276         default:
1277             return -EINVAL;
1278         }
1279 
1280         snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
1281             M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1282             M98095_DAI_WCI, regval);
1283 
1284         snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
1285             M98095_DAI_BSEL64);
1286     }
1287 
1288     return 0;
1289 }
1290 
1291 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1292                  unsigned int fmt)
1293 {
1294     struct snd_soc_component *component = codec_dai->component;
1295     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1296     struct max98095_cdata *cdata;
1297     u8 regval = 0;
1298 
1299     cdata = &max98095->dai[2];
1300 
1301     if (fmt != cdata->fmt) {
1302         cdata->fmt = fmt;
1303 
1304         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1305         case SND_SOC_DAIFMT_CBC_CFC:
1306             /* Consumer mode PLL */
1307             snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
1308                 0x80);
1309             snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
1310                 0x00);
1311             break;
1312         case SND_SOC_DAIFMT_CBP_CFP:
1313             /* Set to provider mode */
1314             regval |= M98095_DAI_MAS;
1315             break;
1316         default:
1317             dev_err(component->dev, "Clock mode unsupported");
1318             return -EINVAL;
1319         }
1320 
1321         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1322         case SND_SOC_DAIFMT_I2S:
1323             regval |= M98095_DAI_DLY;
1324             break;
1325         case SND_SOC_DAIFMT_LEFT_J:
1326             break;
1327         default:
1328             return -EINVAL;
1329         }
1330 
1331         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1332         case SND_SOC_DAIFMT_NB_NF:
1333             break;
1334         case SND_SOC_DAIFMT_NB_IF:
1335             regval |= M98095_DAI_WCI;
1336             break;
1337         case SND_SOC_DAIFMT_IB_NF:
1338             regval |= M98095_DAI_BCI;
1339             break;
1340         case SND_SOC_DAIFMT_IB_IF:
1341             regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1342             break;
1343         default:
1344             return -EINVAL;
1345         }
1346 
1347         snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
1348             M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1349             M98095_DAI_WCI, regval);
1350 
1351         snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
1352             M98095_DAI_BSEL64);
1353     }
1354 
1355     return 0;
1356 }
1357 
1358 static int max98095_set_bias_level(struct snd_soc_component *component,
1359                    enum snd_soc_bias_level level)
1360 {
1361     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1362     int ret;
1363 
1364     switch (level) {
1365     case SND_SOC_BIAS_ON:
1366         break;
1367 
1368     case SND_SOC_BIAS_PREPARE:
1369         /*
1370          * SND_SOC_BIAS_PREPARE is called while preparing for a
1371          * transition to ON or away from ON. If current bias_level
1372          * is SND_SOC_BIAS_ON, then it is preparing for a transition
1373          * away from ON. Disable the clock in that case, otherwise
1374          * enable it.
1375          */
1376         if (IS_ERR(max98095->mclk))
1377             break;
1378 
1379         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1380             clk_disable_unprepare(max98095->mclk);
1381         } else {
1382             ret = clk_prepare_enable(max98095->mclk);
1383             if (ret)
1384                 return ret;
1385         }
1386         break;
1387 
1388     case SND_SOC_BIAS_STANDBY:
1389         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1390             ret = regcache_sync(max98095->regmap);
1391 
1392             if (ret != 0) {
1393                 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1394                 return ret;
1395             }
1396         }
1397 
1398         snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1399                 M98095_MBEN, M98095_MBEN);
1400         break;
1401 
1402     case SND_SOC_BIAS_OFF:
1403         snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
1404                 M98095_MBEN, 0);
1405         regcache_mark_dirty(max98095->regmap);
1406         break;
1407     }
1408     return 0;
1409 }
1410 
1411 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1412 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1413 
1414 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1415     .set_sysclk = max98095_dai_set_sysclk,
1416     .set_fmt = max98095_dai1_set_fmt,
1417     .hw_params = max98095_dai1_hw_params,
1418 };
1419 
1420 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1421     .set_sysclk = max98095_dai_set_sysclk,
1422     .set_fmt = max98095_dai2_set_fmt,
1423     .hw_params = max98095_dai2_hw_params,
1424 };
1425 
1426 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1427     .set_sysclk = max98095_dai_set_sysclk,
1428     .set_fmt = max98095_dai3_set_fmt,
1429     .hw_params = max98095_dai3_hw_params,
1430 };
1431 
1432 static struct snd_soc_dai_driver max98095_dai[] = {
1433 {
1434     .name = "HiFi",
1435     .playback = {
1436         .stream_name = "HiFi Playback",
1437         .channels_min = 1,
1438         .channels_max = 2,
1439         .rates = MAX98095_RATES,
1440         .formats = MAX98095_FORMATS,
1441     },
1442     .capture = {
1443         .stream_name = "HiFi Capture",
1444         .channels_min = 1,
1445         .channels_max = 2,
1446         .rates = MAX98095_RATES,
1447         .formats = MAX98095_FORMATS,
1448     },
1449      .ops = &max98095_dai1_ops,
1450 },
1451 {
1452     .name = "Aux",
1453     .playback = {
1454         .stream_name = "Aux Playback",
1455         .channels_min = 1,
1456         .channels_max = 1,
1457         .rates = MAX98095_RATES,
1458         .formats = MAX98095_FORMATS,
1459     },
1460     .ops = &max98095_dai2_ops,
1461 },
1462 {
1463     .name = "Voice",
1464     .playback = {
1465         .stream_name = "Voice Playback",
1466         .channels_min = 1,
1467         .channels_max = 1,
1468         .rates = MAX98095_RATES,
1469         .formats = MAX98095_FORMATS,
1470     },
1471     .ops = &max98095_dai3_ops,
1472 }
1473 
1474 };
1475 
1476 static int max98095_get_eq_channel(const char *name)
1477 {
1478     if (strcmp(name, "EQ1 Mode") == 0)
1479         return 0;
1480     if (strcmp(name, "EQ2 Mode") == 0)
1481         return 1;
1482     return -EINVAL;
1483 }
1484 
1485 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1486                  struct snd_ctl_elem_value *ucontrol)
1487 {
1488     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1489     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1490     struct max98095_pdata *pdata = max98095->pdata;
1491     int channel = max98095_get_eq_channel(kcontrol->id.name);
1492     struct max98095_cdata *cdata;
1493     unsigned int sel = ucontrol->value.enumerated.item[0];
1494     struct max98095_eq_cfg *coef_set;
1495     int fs, best, best_val, i;
1496     int regmask, regsave;
1497 
1498     if (WARN_ON(channel > 1))
1499         return -EINVAL;
1500 
1501     if (!pdata || !max98095->eq_textcnt)
1502         return 0;
1503 
1504     if (sel >= pdata->eq_cfgcnt)
1505         return -EINVAL;
1506 
1507     cdata = &max98095->dai[channel];
1508     cdata->eq_sel = sel;
1509     fs = cdata->rate;
1510 
1511     /* Find the selected configuration with nearest sample rate */
1512     best = 0;
1513     best_val = INT_MAX;
1514     for (i = 0; i < pdata->eq_cfgcnt; i++) {
1515         if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1516             abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1517             best = i;
1518             best_val = abs(pdata->eq_cfg[i].rate - fs);
1519         }
1520     }
1521 
1522     dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1523         pdata->eq_cfg[best].name,
1524         pdata->eq_cfg[best].rate, fs);
1525 
1526     coef_set = &pdata->eq_cfg[best];
1527 
1528     regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1529 
1530     /* Disable filter while configuring, and save current on/off state */
1531     regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1532     snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1533 
1534     mutex_lock(&max98095->lock);
1535     snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1536     m98095_eq_band(component, channel, 0, coef_set->band1);
1537     m98095_eq_band(component, channel, 1, coef_set->band2);
1538     m98095_eq_band(component, channel, 2, coef_set->band3);
1539     m98095_eq_band(component, channel, 3, coef_set->band4);
1540     m98095_eq_band(component, channel, 4, coef_set->band5);
1541     snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1542     mutex_unlock(&max98095->lock);
1543 
1544     /* Restore the original on/off state */
1545     snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1546     return 0;
1547 }
1548 
1549 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1550                  struct snd_ctl_elem_value *ucontrol)
1551 {
1552     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1553     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1554     int channel = max98095_get_eq_channel(kcontrol->id.name);
1555     struct max98095_cdata *cdata;
1556 
1557     cdata = &max98095->dai[channel];
1558     ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1559 
1560     return 0;
1561 }
1562 
1563 static void max98095_handle_eq_pdata(struct snd_soc_component *component)
1564 {
1565     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1566     struct max98095_pdata *pdata = max98095->pdata;
1567     struct max98095_eq_cfg *cfg;
1568     unsigned int cfgcnt;
1569     int i, j;
1570     const char **t;
1571     int ret;
1572 
1573     struct snd_kcontrol_new controls[] = {
1574         SOC_ENUM_EXT("EQ1 Mode",
1575             max98095->eq_enum,
1576             max98095_get_eq_enum,
1577             max98095_put_eq_enum),
1578         SOC_ENUM_EXT("EQ2 Mode",
1579             max98095->eq_enum,
1580             max98095_get_eq_enum,
1581             max98095_put_eq_enum),
1582     };
1583 
1584     cfg = pdata->eq_cfg;
1585     cfgcnt = pdata->eq_cfgcnt;
1586 
1587     /* Setup an array of texts for the equalizer enum.
1588      * This is based on Mark Brown's equalizer driver code.
1589      */
1590     max98095->eq_textcnt = 0;
1591     max98095->eq_texts = NULL;
1592     for (i = 0; i < cfgcnt; i++) {
1593         for (j = 0; j < max98095->eq_textcnt; j++) {
1594             if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1595                 break;
1596         }
1597 
1598         if (j != max98095->eq_textcnt)
1599             continue;
1600 
1601         /* Expand the array */
1602         t = krealloc(max98095->eq_texts,
1603                  sizeof(char *) * (max98095->eq_textcnt + 1),
1604                  GFP_KERNEL);
1605         if (t == NULL)
1606             continue;
1607 
1608         /* Store the new entry */
1609         t[max98095->eq_textcnt] = cfg[i].name;
1610         max98095->eq_textcnt++;
1611         max98095->eq_texts = t;
1612     }
1613 
1614     /* Now point the soc_enum to .texts array items */
1615     max98095->eq_enum.texts = max98095->eq_texts;
1616     max98095->eq_enum.items = max98095->eq_textcnt;
1617 
1618     ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1619     if (ret != 0)
1620         dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1621 }
1622 
1623 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1624 
1625 static int max98095_get_bq_channel(struct snd_soc_component *component,
1626                    const char *name)
1627 {
1628     int ret;
1629 
1630     ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
1631     if (ret < 0)
1632         dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
1633     return ret;
1634 }
1635 
1636 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1637                  struct snd_ctl_elem_value *ucontrol)
1638 {
1639     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1640     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1641     struct max98095_pdata *pdata = max98095->pdata;
1642     int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1643     struct max98095_cdata *cdata;
1644     unsigned int sel = ucontrol->value.enumerated.item[0];
1645     struct max98095_biquad_cfg *coef_set;
1646     int fs, best, best_val, i;
1647     int regmask, regsave;
1648 
1649     if (channel < 0)
1650         return channel;
1651 
1652     if (!pdata || !max98095->bq_textcnt)
1653         return 0;
1654 
1655     if (sel >= pdata->bq_cfgcnt)
1656         return -EINVAL;
1657 
1658     cdata = &max98095->dai[channel];
1659     cdata->bq_sel = sel;
1660     fs = cdata->rate;
1661 
1662     /* Find the selected configuration with nearest sample rate */
1663     best = 0;
1664     best_val = INT_MAX;
1665     for (i = 0; i < pdata->bq_cfgcnt; i++) {
1666         if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1667             abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1668             best = i;
1669             best_val = abs(pdata->bq_cfg[i].rate - fs);
1670         }
1671     }
1672 
1673     dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1674         pdata->bq_cfg[best].name,
1675         pdata->bq_cfg[best].rate, fs);
1676 
1677     coef_set = &pdata->bq_cfg[best];
1678 
1679     regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1680 
1681     /* Disable filter while configuring, and save current on/off state */
1682     regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
1683     snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
1684 
1685     mutex_lock(&max98095->lock);
1686     snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1687     m98095_biquad_band(component, channel, 0, coef_set->band1);
1688     m98095_biquad_band(component, channel, 1, coef_set->band2);
1689     snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
1690     mutex_unlock(&max98095->lock);
1691 
1692     /* Restore the original on/off state */
1693     snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
1694     return 0;
1695 }
1696 
1697 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1698                  struct snd_ctl_elem_value *ucontrol)
1699 {
1700     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1701     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1702     int channel = max98095_get_bq_channel(component, kcontrol->id.name);
1703     struct max98095_cdata *cdata;
1704 
1705     if (channel < 0)
1706         return channel;
1707 
1708     cdata = &max98095->dai[channel];
1709     ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1710 
1711     return 0;
1712 }
1713 
1714 static void max98095_handle_bq_pdata(struct snd_soc_component *component)
1715 {
1716     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1717     struct max98095_pdata *pdata = max98095->pdata;
1718     struct max98095_biquad_cfg *cfg;
1719     unsigned int cfgcnt;
1720     int i, j;
1721     const char **t;
1722     int ret;
1723 
1724     struct snd_kcontrol_new controls[] = {
1725         SOC_ENUM_EXT((char *)bq_mode_name[0],
1726             max98095->bq_enum,
1727             max98095_get_bq_enum,
1728             max98095_put_bq_enum),
1729         SOC_ENUM_EXT((char *)bq_mode_name[1],
1730             max98095->bq_enum,
1731             max98095_get_bq_enum,
1732             max98095_put_bq_enum),
1733     };
1734     BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
1735 
1736     cfg = pdata->bq_cfg;
1737     cfgcnt = pdata->bq_cfgcnt;
1738 
1739     /* Setup an array of texts for the biquad enum.
1740      * This is based on Mark Brown's equalizer driver code.
1741      */
1742     max98095->bq_textcnt = 0;
1743     max98095->bq_texts = NULL;
1744     for (i = 0; i < cfgcnt; i++) {
1745         for (j = 0; j < max98095->bq_textcnt; j++) {
1746             if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1747                 break;
1748         }
1749 
1750         if (j != max98095->bq_textcnt)
1751             continue;
1752 
1753         /* Expand the array */
1754         t = krealloc(max98095->bq_texts,
1755                  sizeof(char *) * (max98095->bq_textcnt + 1),
1756                  GFP_KERNEL);
1757         if (t == NULL)
1758             continue;
1759 
1760         /* Store the new entry */
1761         t[max98095->bq_textcnt] = cfg[i].name;
1762         max98095->bq_textcnt++;
1763         max98095->bq_texts = t;
1764     }
1765 
1766     /* Now point the soc_enum to .texts array items */
1767     max98095->bq_enum.texts = max98095->bq_texts;
1768     max98095->bq_enum.items = max98095->bq_textcnt;
1769 
1770     ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1771     if (ret != 0)
1772         dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
1773 }
1774 
1775 static void max98095_handle_pdata(struct snd_soc_component *component)
1776 {
1777     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1778     struct max98095_pdata *pdata = max98095->pdata;
1779     u8 regval = 0;
1780 
1781     if (!pdata) {
1782         dev_dbg(component->dev, "No platform data\n");
1783         return;
1784     }
1785 
1786     /* Configure mic for analog/digital mic mode */
1787     if (pdata->digmic_left_mode)
1788         regval |= M98095_DIGMIC_L;
1789 
1790     if (pdata->digmic_right_mode)
1791         regval |= M98095_DIGMIC_R;
1792 
1793     snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
1794 
1795     /* Configure equalizers */
1796     if (pdata->eq_cfgcnt)
1797         max98095_handle_eq_pdata(component);
1798 
1799     /* Configure bi-quad filters */
1800     if (pdata->bq_cfgcnt)
1801         max98095_handle_bq_pdata(component);
1802 }
1803 
1804 static irqreturn_t max98095_report_jack(int irq, void *data)
1805 {
1806     struct snd_soc_component *component = data;
1807     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1808     unsigned int value;
1809     int hp_report = 0;
1810     int mic_report = 0;
1811 
1812     /* Read the Jack Status Register */
1813     value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
1814 
1815     /* If ddone is not set, then detection isn't finished yet */
1816     if ((value & M98095_DDONE) == 0)
1817         return IRQ_NONE;
1818 
1819     /* if hp, check its bit, and if set, clear it */
1820     if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
1821         max98095->headphone_jack)
1822         hp_report |= SND_JACK_HEADPHONE;
1823 
1824     /* if mic, check its bit, and if set, clear it */
1825     if ((value & M98095_MIC_IN) && max98095->mic_jack)
1826         mic_report |= SND_JACK_MICROPHONE;
1827 
1828     if (max98095->headphone_jack == max98095->mic_jack) {
1829         snd_soc_jack_report(max98095->headphone_jack,
1830                     hp_report | mic_report,
1831                     SND_JACK_HEADSET);
1832     } else {
1833         if (max98095->headphone_jack)
1834             snd_soc_jack_report(max98095->headphone_jack,
1835                     hp_report, SND_JACK_HEADPHONE);
1836         if (max98095->mic_jack)
1837             snd_soc_jack_report(max98095->mic_jack,
1838                     mic_report, SND_JACK_MICROPHONE);
1839     }
1840 
1841     return IRQ_HANDLED;
1842 }
1843 
1844 static int max98095_jack_detect_enable(struct snd_soc_component *component)
1845 {
1846     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1847     int ret = 0;
1848     int detect_enable = M98095_JDEN;
1849     unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
1850 
1851     if (max98095->pdata->jack_detect_pin5en)
1852         detect_enable |= M98095_PIN5EN;
1853 
1854     if (max98095->pdata->jack_detect_delay)
1855         slew = max98095->pdata->jack_detect_delay;
1856 
1857     ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
1858     if (ret < 0) {
1859         dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1860         return ret;
1861     }
1862 
1863     /* configure auto detection to be enabled */
1864     ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
1865     if (ret < 0) {
1866         dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1867         return ret;
1868     }
1869 
1870     return ret;
1871 }
1872 
1873 static int max98095_jack_detect_disable(struct snd_soc_component *component)
1874 {
1875     int ret = 0;
1876 
1877     /* configure auto detection to be disabled */
1878     ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
1879     if (ret < 0) {
1880         dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
1881         return ret;
1882     }
1883 
1884     return ret;
1885 }
1886 
1887 int max98095_jack_detect(struct snd_soc_component *component,
1888     struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
1889 {
1890     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1891     struct i2c_client *client = to_i2c_client(component->dev);
1892     int ret = 0;
1893 
1894     max98095->headphone_jack = hp_jack;
1895     max98095->mic_jack = mic_jack;
1896 
1897     /* only progress if we have at least 1 jack pointer */
1898     if (!hp_jack && !mic_jack)
1899         return -EINVAL;
1900 
1901     max98095_jack_detect_enable(component);
1902 
1903     /* enable interrupts for headphone jack detection */
1904     ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
1905         M98095_IDDONE, M98095_IDDONE);
1906     if (ret < 0) {
1907         dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
1908         return ret;
1909     }
1910 
1911     max98095_report_jack(client->irq, component);
1912     return 0;
1913 }
1914 EXPORT_SYMBOL_GPL(max98095_jack_detect);
1915 
1916 #ifdef CONFIG_PM
1917 static int max98095_suspend(struct snd_soc_component *component)
1918 {
1919     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1920 
1921     if (max98095->headphone_jack || max98095->mic_jack)
1922         max98095_jack_detect_disable(component);
1923 
1924     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1925 
1926     return 0;
1927 }
1928 
1929 static int max98095_resume(struct snd_soc_component *component)
1930 {
1931     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1932     struct i2c_client *client = to_i2c_client(component->dev);
1933 
1934     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1935 
1936     if (max98095->headphone_jack || max98095->mic_jack) {
1937         max98095_jack_detect_enable(component);
1938         max98095_report_jack(client->irq, component);
1939     }
1940 
1941     return 0;
1942 }
1943 #else
1944 #define max98095_suspend NULL
1945 #define max98095_resume NULL
1946 #endif
1947 
1948 static int max98095_reset(struct snd_soc_component *component)
1949 {
1950     int i, ret;
1951 
1952     /* Gracefully reset the DSP core and the codec hardware
1953      * in a proper sequence */
1954     ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
1955     if (ret < 0) {
1956         dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
1957         return ret;
1958     }
1959 
1960     ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
1961     if (ret < 0) {
1962         dev_err(component->dev, "Failed to reset component: %d\n", ret);
1963         return ret;
1964     }
1965 
1966     /* Reset to hardware default for registers, as there is not
1967      * a soft reset hardware control register */
1968     for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1969         ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
1970         if (ret < 0) {
1971             dev_err(component->dev, "Failed to reset: %d\n", ret);
1972             return ret;
1973         }
1974     }
1975 
1976     return ret;
1977 }
1978 
1979 static int max98095_probe(struct snd_soc_component *component)
1980 {
1981     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
1982     struct max98095_cdata *cdata;
1983     struct i2c_client *client;
1984     int ret = 0;
1985 
1986     max98095->mclk = devm_clk_get(component->dev, "mclk");
1987     if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
1988         return -EPROBE_DEFER;
1989 
1990     /* reset the codec, the DSP core, and disable all interrupts */
1991     max98095_reset(component);
1992 
1993     client = to_i2c_client(component->dev);
1994 
1995     /* initialize private data */
1996 
1997     max98095->sysclk = (unsigned)-1;
1998     max98095->eq_textcnt = 0;
1999     max98095->bq_textcnt = 0;
2000 
2001     cdata = &max98095->dai[0];
2002     cdata->rate = (unsigned)-1;
2003     cdata->fmt  = (unsigned)-1;
2004     cdata->eq_sel = 0;
2005     cdata->bq_sel = 0;
2006 
2007     cdata = &max98095->dai[1];
2008     cdata->rate = (unsigned)-1;
2009     cdata->fmt  = (unsigned)-1;
2010     cdata->eq_sel = 0;
2011     cdata->bq_sel = 0;
2012 
2013     cdata = &max98095->dai[2];
2014     cdata->rate = (unsigned)-1;
2015     cdata->fmt  = (unsigned)-1;
2016     cdata->eq_sel = 0;
2017     cdata->bq_sel = 0;
2018 
2019     max98095->lin_state = 0;
2020     max98095->mic1pre = 0;
2021     max98095->mic2pre = 0;
2022 
2023     if (client->irq) {
2024         /* register an audio interrupt */
2025         ret = request_threaded_irq(client->irq, NULL,
2026             max98095_report_jack,
2027             IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
2028             IRQF_ONESHOT, "max98095", component);
2029         if (ret) {
2030             dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
2031             goto err_access;
2032         }
2033     }
2034 
2035     ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
2036     if (ret < 0) {
2037         dev_err(component->dev, "Failure reading hardware revision: %d\n",
2038             ret);
2039         goto err_irq;
2040     }
2041     dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2042 
2043     snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
2044 
2045     snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
2046         M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2047 
2048     snd_soc_component_write(component, M98095_049_MIX_DAC_M,
2049         M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2050 
2051     snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2052     snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2053     snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
2054 
2055     snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
2056         M98095_S1NORMAL|M98095_SDATA);
2057 
2058     snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
2059         M98095_S2NORMAL|M98095_SDATA);
2060 
2061     snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
2062         M98095_S3NORMAL|M98095_SDATA);
2063 
2064     max98095_handle_pdata(component);
2065 
2066     /* take the codec out of the shut down */
2067     snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
2068         M98095_SHDNRUN);
2069 
2070     return 0;
2071 
2072 err_irq:
2073     if (client->irq)
2074         free_irq(client->irq, component);
2075 err_access:
2076     return ret;
2077 }
2078 
2079 static void max98095_remove(struct snd_soc_component *component)
2080 {
2081     struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
2082     struct i2c_client *client = to_i2c_client(component->dev);
2083 
2084     if (max98095->headphone_jack || max98095->mic_jack)
2085         max98095_jack_detect_disable(component);
2086 
2087     if (client->irq)
2088         free_irq(client->irq, component);
2089 }
2090 
2091 static const struct snd_soc_component_driver soc_component_dev_max98095 = {
2092     .probe          = max98095_probe,
2093     .remove         = max98095_remove,
2094     .suspend        = max98095_suspend,
2095     .resume         = max98095_resume,
2096     .set_bias_level     = max98095_set_bias_level,
2097     .controls       = max98095_snd_controls,
2098     .num_controls       = ARRAY_SIZE(max98095_snd_controls),
2099     .dapm_widgets       = max98095_dapm_widgets,
2100     .num_dapm_widgets   = ARRAY_SIZE(max98095_dapm_widgets),
2101     .dapm_routes        = max98095_audio_map,
2102     .num_dapm_routes    = ARRAY_SIZE(max98095_audio_map),
2103     .idle_bias_on       = 1,
2104     .use_pmdown_time    = 1,
2105     .endianness     = 1,
2106 };
2107 
2108 static const struct i2c_device_id max98095_i2c_id[] = {
2109     { "max98095", MAX98095 },
2110     { }
2111 };
2112 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2113 
2114 static int max98095_i2c_probe(struct i2c_client *i2c)
2115 {
2116     struct max98095_priv *max98095;
2117     int ret;
2118     const struct i2c_device_id *id;
2119 
2120     max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2121                 GFP_KERNEL);
2122     if (max98095 == NULL)
2123         return -ENOMEM;
2124 
2125     mutex_init(&max98095->lock);
2126 
2127     max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2128     if (IS_ERR(max98095->regmap)) {
2129         ret = PTR_ERR(max98095->regmap);
2130         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2131         return ret;
2132     }
2133 
2134     id = i2c_match_id(max98095_i2c_id, i2c);
2135     max98095->devtype = id->driver_data;
2136     i2c_set_clientdata(i2c, max98095);
2137     max98095->pdata = i2c->dev.platform_data;
2138 
2139     ret = devm_snd_soc_register_component(&i2c->dev,
2140                      &soc_component_dev_max98095,
2141                      max98095_dai, ARRAY_SIZE(max98095_dai));
2142     return ret;
2143 }
2144 
2145 #ifdef CONFIG_OF
2146 static const struct of_device_id max98095_of_match[] = {
2147     { .compatible = "maxim,max98095", },
2148     { }
2149 };
2150 MODULE_DEVICE_TABLE(of, max98095_of_match);
2151 #endif
2152 
2153 static struct i2c_driver max98095_i2c_driver = {
2154     .driver = {
2155         .name = "max98095",
2156         .of_match_table = of_match_ptr(max98095_of_match),
2157     },
2158     .probe_new = max98095_i2c_probe,
2159     .id_table = max98095_i2c_id,
2160 };
2161 
2162 module_i2c_driver(max98095_i2c_driver);
2163 
2164 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2165 MODULE_AUTHOR("Peter Hsiang");
2166 MODULE_LICENSE("GPL");
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