soc/codecs/max98090.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * max98090.c -- MAX98090 ALSA SoC Audio driver
0004  *
0005  * Copyright 2011-2012 Maxim Integrated Products
0006  */
0007
0008 #include <linux/delay.h>
0009 #include <linux/i2c.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/pm.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/regmap.h>
0015 #include <linux/slab.h>
0016 #include <linux/acpi.h>
0017 #include <linux/clk.h>
0018 #include <sound/jack.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022 #include <sound/tlv.h>
0023 #include <sound/max98090.h>
0024 #include "max98090.h"
0025
0026 /* Allows for sparsely populated register maps */
0027 static const struct reg_default max98090_reg[] = {
0028     { 0x00, 0x00 }, /* 00 Software Reset */
0029     { 0x03, 0x04 }, /* 03 Interrupt Masks */
0030     { 0x04, 0x00 }, /* 04 System Clock Quick */
0031     { 0x05, 0x00 }, /* 05 Sample Rate Quick */
0032     { 0x06, 0x00 }, /* 06 DAI Interface Quick */
0033     { 0x07, 0x00 }, /* 07 DAC Path Quick */
0034     { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
0035     { 0x09, 0x00 }, /* 09 Line to ADC Quick */
0036     { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
0037     { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
0038     { 0x0C, 0x00 }, /* 0C Reserved */
0039     { 0x0D, 0x00 }, /* 0D Input Config */
0040     { 0x0E, 0x1B }, /* 0E Line Input Level */
0041     { 0x0F, 0x00 }, /* 0F Line Config */
0042
0043     { 0x10, 0x14 }, /* 10 Mic1 Input Level */
0044     { 0x11, 0x14 }, /* 11 Mic2 Input Level */
0045     { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
0046     { 0x13, 0x00 }, /* 13 Digital Mic Config */
0047     { 0x14, 0x00 }, /* 14 Digital Mic Mode */
0048     { 0x15, 0x00 }, /* 15 Left ADC Mixer */
0049     { 0x16, 0x00 }, /* 16 Right ADC Mixer */
0050     { 0x17, 0x03 }, /* 17 Left ADC Level */
0051     { 0x18, 0x03 }, /* 18 Right ADC Level */
0052     { 0x19, 0x00 }, /* 19 ADC Biquad Level */
0053     { 0x1A, 0x00 }, /* 1A ADC Sidetone */
0054     { 0x1B, 0x00 }, /* 1B System Clock */
0055     { 0x1C, 0x00 }, /* 1C Clock Mode */
0056     { 0x1D, 0x00 }, /* 1D Any Clock 1 */
0057     { 0x1E, 0x00 }, /* 1E Any Clock 2 */
0058     { 0x1F, 0x00 }, /* 1F Any Clock 3 */
0059
0060     { 0x20, 0x00 }, /* 20 Any Clock 4 */
0061     { 0x21, 0x00 }, /* 21 Master Mode */
0062     { 0x22, 0x00 }, /* 22 Interface Format */
0063     { 0x23, 0x00 }, /* 23 TDM Format 1*/
0064     { 0x24, 0x00 }, /* 24 TDM Format 2*/
0065     { 0x25, 0x00 }, /* 25 I/O Configuration */
0066     { 0x26, 0x80 }, /* 26 Filter Config */
0067     { 0x27, 0x00 }, /* 27 DAI Playback Level */
0068     { 0x28, 0x00 }, /* 28 EQ Playback Level */
0069     { 0x29, 0x00 }, /* 29 Left HP Mixer */
0070     { 0x2A, 0x00 }, /* 2A Right HP Mixer */
0071     { 0x2B, 0x00 }, /* 2B HP Control */
0072     { 0x2C, 0x1A }, /* 2C Left HP Volume */
0073     { 0x2D, 0x1A }, /* 2D Right HP Volume */
0074     { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
0075     { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
0076
0077     { 0x30, 0x00 }, /* 30 Spk Control */
0078     { 0x31, 0x2C }, /* 31 Left Spk Volume */
0079     { 0x32, 0x2C }, /* 32 Right Spk Volume */
0080     { 0x33, 0x00 }, /* 33 ALC Timing */
0081     { 0x34, 0x00 }, /* 34 ALC Compressor */
0082     { 0x35, 0x00 }, /* 35 ALC Expander */
0083     { 0x36, 0x00 }, /* 36 ALC Gain */
0084     { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
0085     { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
0086     { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
0087     { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
0088     { 0x3B, 0x00 }, /* 3B Line OutR Control */
0089     { 0x3C, 0x15 }, /* 3C Line OutR Volume */
0090     { 0x3D, 0x00 }, /* 3D Jack Detect */
0091     { 0x3E, 0x00 }, /* 3E Input Enable */
0092     { 0x3F, 0x00 }, /* 3F Output Enable */
0093
0094     { 0x40, 0x00 }, /* 40 Level Control */
0095     { 0x41, 0x00 }, /* 41 DSP Filter Enable */
0096     { 0x42, 0x00 }, /* 42 Bias Control */
0097     { 0x43, 0x00 }, /* 43 DAC Control */
0098     { 0x44, 0x06 }, /* 44 ADC Control */
0099     { 0x45, 0x00 }, /* 45 Device Shutdown */
0100     { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
0101     { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
0102     { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
0103     { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
0104     { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
0105     { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
0106     { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
0107     { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
0108     { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
0109     { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
0110
0111     { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
0112     { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
0113     { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
0114     { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
0115     { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
0116     { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
0117     { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
0118     { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
0119     { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
0120     { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
0121     { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
0122     { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
0123     { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
0124     { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
0125     { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
0126     { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
0127
0128     { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
0129     { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
0130     { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
0131     { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
0132     { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
0133     { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
0134     { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
0135     { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
0136     { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
0137     { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
0138     { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
0139     { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
0140     { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
0141     { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
0142     { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
0143     { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
0144
0145     { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
0146     { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
0147     { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
0148     { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
0149     { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
0150     { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
0151     { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
0152     { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
0153     { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
0154     { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
0155     { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
0156     { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
0157     { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
0158     { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
0159     { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
0160     { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
0161
0162     { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
0163     { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
0164     { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
0165     { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
0166     { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
0167     { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
0168     { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
0169     { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
0170     { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
0171     { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
0172     { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
0173     { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
0174     { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
0175     { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
0176     { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
0177     { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
0178
0179     { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
0180     { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
0181     { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
0182     { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
0183     { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
0184     { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
0185     { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
0186     { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
0187     { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
0188     { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
0189     { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
0190     { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
0191     { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
0192     { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
0193     { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
0194     { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
0195
0196     { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
0197     { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
0198     { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
0199     { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
0200     { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
0201     { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
0202     { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
0203     { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
0204     { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
0205     { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
0206     { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
0207     { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
0208     { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
0209     { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
0210     { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
0211     { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
0212
0213     { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
0214     { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
0215     { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
0216     { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
0217     { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
0218     { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
0219     { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
0220     { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
0221     { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
0222     { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
0223     { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
0224     { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
0225     { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
0226     { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
0227     { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
0228     { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
0229
0230     { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
0231     { 0xC1, 0x00 }, /* C1 Record TDM Slot */
0232     { 0xC2, 0x00 }, /* C2 Sample Rate */
0233     { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
0234     { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
0235     { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
0236     { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
0237     { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
0238     { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
0239     { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
0240     { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
0241     { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
0242     { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
0243     { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
0244     { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
0245     { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
0246
0247     { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
0248     { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
0249 };
0250
0251 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
0252 {
0253     switch (reg) {
0254     case M98090_REG_SOFTWARE_RESET:
0255     case M98090_REG_DEVICE_STATUS:
0256     case M98090_REG_JACK_STATUS:
0257     case M98090_REG_REVISION_ID:
0258         return true;
0259     default:
0260         return false;
0261     }
0262 }
0263
0264 static bool max98090_readable_register(struct device *dev, unsigned int reg)
0265 {
0266     switch (reg) {
0267     case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
0268     case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
0269     case M98090_REG_REVISION_ID:
0270         return true;
0271     default:
0272         return false;
0273     }
0274 }
0275
0276 static int max98090_reset(struct max98090_priv *max98090)
0277 {
0278     int ret;
0279
0280     /* Reset the codec by writing to this write-only reset register */
0281     ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
0282         M98090_SWRESET_MASK);
0283     if (ret < 0) {
0284         dev_err(max98090->component->dev,
0285             "Failed to reset codec: %d\n", ret);
0286         return ret;
0287     }
0288
0289     msleep(20);
0290     return ret;
0291 }
0292
0293 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
0294     0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
0295     2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
0296 );
0297
0298 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
0299
0300 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
0301     -600, 600, 0);
0302
0303 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
0304     0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
0305     4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
0306 );
0307
0308 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
0309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
0310
0311 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
0312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
0313
0314 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
0315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
0316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
0317 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
0318
0319 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
0320     0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
0321     2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
0322 );
0323
0324 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
0325     0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
0326     7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
0327     15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
0328     22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
0329     28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
0330 );
0331
0332 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
0333     0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
0334     5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
0335     11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0336     15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
0337     30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
0338 );
0339
0340 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
0341     0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
0342     7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
0343     15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0344     22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
0345     28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
0346 );
0347
0348 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
0349                 struct snd_ctl_elem_value *ucontrol)
0350 {
0351     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0352     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
0353     struct soc_mixer_control *mc =
0354         (struct soc_mixer_control *)kcontrol->private_value;
0355     unsigned int mask = (1 << fls(mc->max)) - 1;
0356     unsigned int val = snd_soc_component_read(component, mc->reg);
0357     unsigned int *select;
0358
0359     switch (mc->reg) {
0360     case M98090_REG_MIC1_INPUT_LEVEL:
0361         select = &(max98090->pa1en);
0362         break;
0363     case M98090_REG_MIC2_INPUT_LEVEL:
0364         select = &(max98090->pa2en);
0365         break;
0366     case M98090_REG_ADC_SIDETONE:
0367         select = &(max98090->sidetone);
0368         break;
0369     default:
0370         return -EINVAL;
0371     }
0372
0373     val = (val >> mc->shift) & mask;
0374
0375     if (val >= 1) {
0376         /* If on, return the volume */
0377         val = val - 1;
0378         *select = val;
0379     } else {
0380         /* If off, return last stored value */
0381         val = *select;
0382     }
0383
0384     ucontrol->value.integer.value[0] = val;
0385     return 0;
0386 }
0387
0388 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
0389                 struct snd_ctl_elem_value *ucontrol)
0390 {
0391     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0392     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
0393     struct soc_mixer_control *mc =
0394         (struct soc_mixer_control *)kcontrol->private_value;
0395     unsigned int mask = (1 << fls(mc->max)) - 1;
0396     int sel_unchecked = ucontrol->value.integer.value[0];
0397     unsigned int sel;
0398     unsigned int val = snd_soc_component_read(component, mc->reg);
0399     unsigned int *select;
0400     int change;
0401
0402     switch (mc->reg) {
0403     case M98090_REG_MIC1_INPUT_LEVEL:
0404         select = &(max98090->pa1en);
0405         break;
0406     case M98090_REG_MIC2_INPUT_LEVEL:
0407         select = &(max98090->pa2en);
0408         break;
0409     case M98090_REG_ADC_SIDETONE:
0410         select = &(max98090->sidetone);
0411         break;
0412     default:
0413         return -EINVAL;
0414     }
0415
0416     val = (val >> mc->shift) & mask;
0417
0418     if (sel_unchecked < 0 || sel_unchecked > mc->max)
0419         return -EINVAL;
0420     sel = sel_unchecked;
0421
0422     change = *select != sel;
0423     *select = sel;
0424
0425     /* Setting a volume is only valid if it is already On */
0426     if (val >= 1) {
0427         sel = sel + 1;
0428     } else {
0429         /* Write what was already there */
0430         sel = val;
0431     }
0432
0433     snd_soc_component_update_bits(component, mc->reg,
0434         mask << mc->shift,
0435         sel << mc->shift);
0436
0437     return change;
0438 }
0439
0440 static const char *max98090_perf_pwr_text[] =
0441     { "High Performance", "Low Power" };
0442 static const char *max98090_pwr_perf_text[] =
0443     { "Low Power", "High Performance" };
0444
0445 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
0446                 M98090_REG_BIAS_CONTROL,
0447                 M98090_VCM_MODE_SHIFT,
0448                 max98090_pwr_perf_text);
0449
0450 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
0451
0452 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
0453                 M98090_REG_ADC_CONTROL,
0454                 M98090_OSR128_SHIFT,
0455                 max98090_osr128_text);
0456
0457 static const char *max98090_mode_text[] = { "Voice", "Music" };
0458
0459 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
0460                 M98090_REG_FILTER_CONFIG,
0461                 M98090_MODE_SHIFT,
0462                 max98090_mode_text);
0463
0464 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
0465                 M98090_REG_FILTER_CONFIG,
0466                 M98090_FLT_DMIC34MODE_SHIFT,
0467                 max98090_mode_text);
0468
0469 static const char *max98090_drcatk_text[] =
0470     { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
0471
0472 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
0473                 M98090_REG_DRC_TIMING,
0474                 M98090_DRCATK_SHIFT,
0475                 max98090_drcatk_text);
0476
0477 static const char *max98090_drcrls_text[] =
0478     { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
0479
0480 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
0481                 M98090_REG_DRC_TIMING,
0482                 M98090_DRCRLS_SHIFT,
0483                 max98090_drcrls_text);
0484
0485 static const char *max98090_alccmp_text[] =
0486     { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
0487
0488 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
0489                 M98090_REG_DRC_COMPRESSOR,
0490                 M98090_DRCCMP_SHIFT,
0491                 max98090_alccmp_text);
0492
0493 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
0494
0495 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
0496                 M98090_REG_DRC_EXPANDER,
0497                 M98090_DRCEXP_SHIFT,
0498                 max98090_drcexp_text);
0499
0500 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
0501                 M98090_REG_DAC_CONTROL,
0502                 M98090_PERFMODE_SHIFT,
0503                 max98090_perf_pwr_text);
0504
0505 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
0506                 M98090_REG_DAC_CONTROL,
0507                 M98090_DACHP_SHIFT,
0508                 max98090_pwr_perf_text);
0509
0510 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
0511                 M98090_REG_ADC_CONTROL,
0512                 M98090_ADCHP_SHIFT,
0513                 max98090_pwr_perf_text);
0514
0515 static const struct snd_kcontrol_new max98090_snd_controls[] = {
0516     SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
0517
0518     SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
0519         M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
0520
0521     SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
0522         M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
0523         M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
0524         max98090_put_enab_tlv, max98090_micboost_tlv),
0525
0526     SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
0527         M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
0528         M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
0529         max98090_put_enab_tlv, max98090_micboost_tlv),
0530
0531     SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
0532         M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
0533         max98090_mic_tlv),
0534
0535     SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
0536         M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
0537         max98090_mic_tlv),
0538
0539     SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
0540         M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
0541         M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
0542
0543     SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
0544         M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
0545         M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
0546
0547     SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
0548         M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
0549         max98090_line_tlv),
0550
0551     SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
0552         M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
0553         max98090_line_tlv),
0554
0555     SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
0556         M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
0557     SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
0558         M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
0559
0560     SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
0561         M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
0562         max98090_avg_tlv),
0563     SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
0564         M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
0565         max98090_avg_tlv),
0566
0567     SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
0568         M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
0569         max98090_av_tlv),
0570     SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
0571         M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
0572         max98090_av_tlv),
0573
0574     SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
0575     SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
0576         M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
0577     SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
0578
0579     SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
0580         M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
0581     SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
0582         M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
0583     SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
0584         M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
0585     SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
0586         M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
0587     SOC_ENUM("Filter Mode", max98090_mode_enum),
0588     SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
0589         M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
0590     SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
0591         M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
0592     SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
0593         M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
0594     SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
0595         M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
0596         M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
0597         max98090_put_enab_tlv, max98090_sdg_tlv),
0598     SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
0599         M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
0600         max98090_dvg_tlv),
0601     SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
0602         M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
0603         max98090_dv_tlv),
0604     SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
0605     SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
0606         M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
0607     SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
0608         M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
0609     SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
0610         M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
0611     SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
0612         M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
0613         1),
0614     SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
0615         M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
0616         max98090_dv_tlv),
0617
0618     SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
0619         M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
0620     SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
0621     SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
0622     SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
0623         M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
0624         max98090_alcmakeup_tlv),
0625     SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
0626     SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
0627     SOC_SINGLE_TLV("ALC Compression Threshold Volume",
0628         M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
0629         M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
0630     SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
0631         M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
0632         M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
0633
0634     SOC_ENUM("DAC HP Playback Performance Mode",
0635         max98090_dac_perfmode_enum),
0636     SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
0637
0638     SOC_SINGLE_TLV("Headphone Left Mixer Volume",
0639         M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
0640         M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
0641     SOC_SINGLE_TLV("Headphone Right Mixer Volume",
0642         M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
0643         M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
0644
0645     SOC_SINGLE_TLV("Speaker Left Mixer Volume",
0646         M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
0647         M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
0648     SOC_SINGLE_TLV("Speaker Right Mixer Volume",
0649         M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
0650         M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
0651
0652     SOC_SINGLE_TLV("Receiver Left Mixer Volume",
0653         M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
0654         M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
0655     SOC_SINGLE_TLV("Receiver Right Mixer Volume",
0656         M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
0657         M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
0658
0659     SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
0660         M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
0661         M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
0662
0663     SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
0664         M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
0665         M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
0666         0, max98090_spk_tlv),
0667
0668     SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
0669         M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
0670         M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
0671
0672     SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
0673         M98090_HPLM_SHIFT, 1, 1),
0674     SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
0675         M98090_HPRM_SHIFT, 1, 1),
0676
0677     SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
0678         M98090_SPLM_SHIFT, 1, 1),
0679     SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
0680         M98090_SPRM_SHIFT, 1, 1),
0681
0682     SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
0683         M98090_RCVLM_SHIFT, 1, 1),
0684     SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
0685         M98090_RCVRM_SHIFT, 1, 1),
0686
0687     SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
0688         M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
0689     SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
0690         M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
0691     SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
0692         M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
0693
0694     SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
0695     SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
0696         M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
0697 };
0698
0699 static const struct snd_kcontrol_new max98091_snd_controls[] = {
0700
0701     SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
0702         M98090_DMIC34_ZEROPAD_SHIFT,
0703         M98090_DMIC34_ZEROPAD_NUM - 1, 0),
0704
0705     SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
0706     SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
0707         M98090_FLT_DMIC34HPF_SHIFT,
0708         M98090_FLT_DMIC34HPF_NUM - 1, 0),
0709
0710     SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
0711         M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
0712         max98090_avg_tlv),
0713     SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
0714         M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
0715         max98090_avg_tlv),
0716
0717     SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
0718         M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
0719         max98090_av_tlv),
0720     SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
0721         M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
0722         max98090_av_tlv),
0723
0724     SND_SOC_BYTES("DMIC34 Biquad Coefficients",
0725         M98090_REG_DMIC34_BIQUAD_BASE, 15),
0726     SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
0727         M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
0728
0729     SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
0730         M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
0731         M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
0732 };
0733
0734 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
0735                  struct snd_kcontrol *kcontrol, int event)
0736 {
0737     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0738     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
0739
0740     unsigned int val = snd_soc_component_read(component, w->reg);
0741
0742     if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
0743         val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
0744     else
0745         val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
0746
0747     if (val >= 1) {
0748         if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
0749             max98090->pa1en = val - 1; /* Update for volatile */
0750         } else {
0751             max98090->pa2en = val - 1; /* Update for volatile */
0752         }
0753     }
0754
0755     switch (event) {
0756     case SND_SOC_DAPM_POST_PMU:
0757         /* If turning on, set to most recently selected volume */
0758         if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
0759             val = max98090->pa1en + 1;
0760         else
0761             val = max98090->pa2en + 1;
0762         break;
0763     case SND_SOC_DAPM_POST_PMD:
0764         /* If turning off, turn off */
0765         val = 0;
0766         break;
0767     default:
0768         return -EINVAL;
0769     }
0770
0771     if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
0772         snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
0773             val << M98090_MIC_PA1EN_SHIFT);
0774     else
0775         snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
0776             val << M98090_MIC_PA2EN_SHIFT);
0777
0778     return 0;
0779 }
0780
0781 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
0782                  struct snd_kcontrol *kcontrol, int event)
0783 {
0784     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0785     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
0786
0787     if (event & SND_SOC_DAPM_POST_PMU)
0788         max98090->shdn_pending = true;
0789
0790     return 0;
0791
0792 }
0793
0794 static const char *mic1_mux_text[] = { "IN12", "IN56" };
0795
0796 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
0797                 M98090_REG_INPUT_MODE,
0798                 M98090_EXTMIC1_SHIFT,
0799                 mic1_mux_text);
0800
0801 static const struct snd_kcontrol_new max98090_mic1_mux =
0802     SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
0803
0804 static const char *mic2_mux_text[] = { "IN34", "IN56" };
0805
0806 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
0807                 M98090_REG_INPUT_MODE,
0808                 M98090_EXTMIC2_SHIFT,
0809                 mic2_mux_text);
0810
0811 static const struct snd_kcontrol_new max98090_mic2_mux =
0812     SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
0813
0814 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
0815
0816 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
0817
0818 static const struct snd_kcontrol_new max98090_dmic_mux =
0819     SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
0820
0821 /* LINEA mixer switch */
0822 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
0823     SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
0824         M98090_IN1SEEN_SHIFT, 1, 0),
0825     SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
0826         M98090_IN3SEEN_SHIFT, 1, 0),
0827     SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
0828         M98090_IN5SEEN_SHIFT, 1, 0),
0829     SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
0830         M98090_IN34DIFF_SHIFT, 1, 0),
0831 };
0832
0833 /* LINEB mixer switch */
0834 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
0835     SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
0836         M98090_IN2SEEN_SHIFT, 1, 0),
0837     SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
0838         M98090_IN4SEEN_SHIFT, 1, 0),
0839     SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
0840         M98090_IN6SEEN_SHIFT, 1, 0),
0841     SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
0842         M98090_IN56DIFF_SHIFT, 1, 0),
0843 };
0844
0845 /* Left ADC mixer switch */
0846 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
0847     SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
0848         M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
0849     SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
0850         M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
0851     SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
0852         M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
0853     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
0854         M98090_MIXADL_LINEA_SHIFT, 1, 0),
0855     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
0856         M98090_MIXADL_LINEB_SHIFT, 1, 0),
0857     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
0858         M98090_MIXADL_MIC1_SHIFT, 1, 0),
0859     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
0860         M98090_MIXADL_MIC2_SHIFT, 1, 0),
0861 };
0862
0863 /* Right ADC mixer switch */
0864 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
0865     SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
0866         M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
0867     SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
0868         M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
0869     SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
0870         M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
0871     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
0872         M98090_MIXADR_LINEA_SHIFT, 1, 0),
0873     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
0874         M98090_MIXADR_LINEB_SHIFT, 1, 0),
0875     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
0876         M98090_MIXADR_MIC1_SHIFT, 1, 0),
0877     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
0878         M98090_MIXADR_MIC2_SHIFT, 1, 0),
0879 };
0880
0881 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
0882
0883 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
0884                 M98090_REG_IO_CONFIGURATION,
0885                 M98090_LTEN_SHIFT,
0886                 lten_mux_text);
0887
0888 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
0889                 M98090_REG_IO_CONFIGURATION,
0890                 M98090_LTEN_SHIFT,
0891                 lten_mux_text);
0892
0893 static const struct snd_kcontrol_new max98090_ltenl_mux =
0894     SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
0895
0896 static const struct snd_kcontrol_new max98090_ltenr_mux =
0897     SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
0898
0899 static const char *lben_mux_text[] = { "Normal", "Loopback" };
0900
0901 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
0902                 M98090_REG_IO_CONFIGURATION,
0903                 M98090_LBEN_SHIFT,
0904                 lben_mux_text);
0905
0906 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
0907                 M98090_REG_IO_CONFIGURATION,
0908                 M98090_LBEN_SHIFT,
0909                 lben_mux_text);
0910
0911 static const struct snd_kcontrol_new max98090_lbenl_mux =
0912     SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
0913
0914 static const struct snd_kcontrol_new max98090_lbenr_mux =
0915     SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
0916
0917 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
0918
0919 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
0920
0921 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
0922                 M98090_REG_ADC_SIDETONE,
0923                 M98090_DSTSL_SHIFT,
0924                 stenl_mux_text);
0925
0926 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
0927                 M98090_REG_ADC_SIDETONE,
0928                 M98090_DSTSR_SHIFT,
0929                 stenr_mux_text);
0930
0931 static const struct snd_kcontrol_new max98090_stenl_mux =
0932     SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
0933
0934 static const struct snd_kcontrol_new max98090_stenr_mux =
0935     SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
0936
0937 /* Left speaker mixer switch */
0938 static const struct
0939     snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
0940     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
0941         M98090_MIXSPL_DACL_SHIFT, 1, 0),
0942     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
0943         M98090_MIXSPL_DACR_SHIFT, 1, 0),
0944     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
0945         M98090_MIXSPL_LINEA_SHIFT, 1, 0),
0946     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
0947         M98090_MIXSPL_LINEB_SHIFT, 1, 0),
0948     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
0949         M98090_MIXSPL_MIC1_SHIFT, 1, 0),
0950     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
0951         M98090_MIXSPL_MIC2_SHIFT, 1, 0),
0952 };
0953
0954 /* Right speaker mixer switch */
0955 static const struct
0956     snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
0957     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
0958         M98090_MIXSPR_DACL_SHIFT, 1, 0),
0959     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
0960         M98090_MIXSPR_DACR_SHIFT, 1, 0),
0961     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
0962         M98090_MIXSPR_LINEA_SHIFT, 1, 0),
0963     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
0964         M98090_MIXSPR_LINEB_SHIFT, 1, 0),
0965     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
0966         M98090_MIXSPR_MIC1_SHIFT, 1, 0),
0967     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
0968         M98090_MIXSPR_MIC2_SHIFT, 1, 0),
0969 };
0970
0971 /* Left headphone mixer switch */
0972 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
0973     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
0974         M98090_MIXHPL_DACL_SHIFT, 1, 0),
0975     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
0976         M98090_MIXHPL_DACR_SHIFT, 1, 0),
0977     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
0978         M98090_MIXHPL_LINEA_SHIFT, 1, 0),
0979     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
0980         M98090_MIXHPL_LINEB_SHIFT, 1, 0),
0981     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
0982         M98090_MIXHPL_MIC1_SHIFT, 1, 0),
0983     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
0984         M98090_MIXHPL_MIC2_SHIFT, 1, 0),
0985 };
0986
0987 /* Right headphone mixer switch */
0988 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
0989     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
0990         M98090_MIXHPR_DACL_SHIFT, 1, 0),
0991     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
0992         M98090_MIXHPR_DACR_SHIFT, 1, 0),
0993     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
0994         M98090_MIXHPR_LINEA_SHIFT, 1, 0),
0995     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
0996         M98090_MIXHPR_LINEB_SHIFT, 1, 0),
0997     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
0998         M98090_MIXHPR_MIC1_SHIFT, 1, 0),
0999     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1000         M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1001 };
1002
1003 /* Left receiver mixer switch */
1004 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1005     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1006         M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1007     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1008         M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1009     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1010         M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1011     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1012         M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1013     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1014         M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1015     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1016         M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1017 };
1018
1019 /* Right receiver mixer switch */
1020 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1021     SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1022         M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1023     SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1024         M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1025     SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1026         M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1027     SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1028         M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1029     SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1030         M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1031     SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1032         M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1033 };
1034
1035 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1036
1037 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1038                 M98090_REG_LOUTR_MIXER,
1039                 M98090_LINMOD_SHIFT,
1040                 linmod_mux_text);
1041
1042 static const struct snd_kcontrol_new max98090_linmod_mux =
1043     SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1044
1045 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1046
1047 /*
1048  * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1049  */
1050 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1051                 M98090_REG_HP_CONTROL,
1052                 M98090_MIXHPLSEL_SHIFT,
1053                 mixhpsel_mux_text);
1054
1055 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1056     SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1057
1058 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1059                 M98090_REG_HP_CONTROL,
1060                 M98090_MIXHPRSEL_SHIFT,
1061                 mixhpsel_mux_text);
1062
1063 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1064     SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1065
1066 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1067     SND_SOC_DAPM_INPUT("MIC1"),
1068     SND_SOC_DAPM_INPUT("MIC2"),
1069     SND_SOC_DAPM_INPUT("DMICL"),
1070     SND_SOC_DAPM_INPUT("DMICR"),
1071     SND_SOC_DAPM_INPUT("IN1"),
1072     SND_SOC_DAPM_INPUT("IN2"),
1073     SND_SOC_DAPM_INPUT("IN3"),
1074     SND_SOC_DAPM_INPUT("IN4"),
1075     SND_SOC_DAPM_INPUT("IN5"),
1076     SND_SOC_DAPM_INPUT("IN6"),
1077     SND_SOC_DAPM_INPUT("IN12"),
1078     SND_SOC_DAPM_INPUT("IN34"),
1079     SND_SOC_DAPM_INPUT("IN56"),
1080
1081     SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1082         M98090_MBEN_SHIFT, 0, NULL, 0),
1083     SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1084         M98090_SHDNN_SHIFT, 0, NULL, 0),
1085     SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1086         M98090_SDIEN_SHIFT, 0, NULL, 0),
1087     SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1088         M98090_SDOEN_SHIFT, 0, NULL, 0),
1089     SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1090          M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1091             SND_SOC_DAPM_POST_PMU),
1092     SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1093          M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1094              SND_SOC_DAPM_POST_PMU),
1095     SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1096         M98090_AHPF_SHIFT, 0, NULL, 0),
1097
1098 /*
1099  * Note: Sysclk and misc power supplies are taken care of by SHDN
1100  */
1101
1102     SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1103         0, 0, &max98090_mic1_mux),
1104
1105     SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1106         0, 0, &max98090_mic2_mux),
1107
1108     SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1109
1110     SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1111         M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1112         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1113
1114     SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1115         M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1116         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1117
1118     SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1119         &max98090_linea_mixer_controls[0],
1120         ARRAY_SIZE(max98090_linea_mixer_controls)),
1121
1122     SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1123         &max98090_lineb_mixer_controls[0],
1124         ARRAY_SIZE(max98090_lineb_mixer_controls)),
1125
1126     SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1127         M98090_LINEAEN_SHIFT, 0, NULL, 0),
1128     SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1129         M98090_LINEBEN_SHIFT, 0, NULL, 0),
1130
1131     SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1132         &max98090_left_adc_mixer_controls[0],
1133         ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1134
1135     SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1136         &max98090_right_adc_mixer_controls[0],
1137         ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1138
1139     SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1140         M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1141         SND_SOC_DAPM_POST_PMU),
1142     SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1143         M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1144         SND_SOC_DAPM_POST_PMU),
1145
1146     SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1147         SND_SOC_NOPM, 0, 0),
1148     SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1149         SND_SOC_NOPM, 0, 0),
1150
1151     SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1152         0, 0, &max98090_lbenl_mux),
1153
1154     SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1155         0, 0, &max98090_lbenr_mux),
1156
1157     SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1158         0, 0, &max98090_ltenl_mux),
1159
1160     SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1161         0, 0, &max98090_ltenr_mux),
1162
1163     SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1164         0, 0, &max98090_stenl_mux),
1165
1166     SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1167         0, 0, &max98090_stenr_mux),
1168
1169     SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1170     SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1171
1172     SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1173         M98090_DALEN_SHIFT, 0),
1174     SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1175         M98090_DAREN_SHIFT, 0),
1176
1177     SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1178         &max98090_left_hp_mixer_controls[0],
1179         ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1180
1181     SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1182         &max98090_right_hp_mixer_controls[0],
1183         ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1184
1185     SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1186         &max98090_left_speaker_mixer_controls[0],
1187         ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1188
1189     SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1190         &max98090_right_speaker_mixer_controls[0],
1191         ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1192
1193     SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1194         &max98090_left_rcv_mixer_controls[0],
1195         ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1196
1197     SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1198         &max98090_right_rcv_mixer_controls[0],
1199         ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1200
1201     SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1202         &max98090_linmod_mux),
1203
1204     SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1205         &max98090_mixhplsel_mux),
1206
1207     SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1208         &max98090_mixhprsel_mux),
1209
1210     SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1211         M98090_HPLEN_SHIFT, 0, NULL, 0),
1212     SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1213         M98090_HPREN_SHIFT, 0, NULL, 0),
1214
1215     SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1216         M98090_SPLEN_SHIFT, 0, NULL, 0),
1217     SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1218         M98090_SPREN_SHIFT, 0, NULL, 0),
1219
1220     SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1221         M98090_RCVLEN_SHIFT, 0, NULL, 0),
1222     SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1223         M98090_RCVREN_SHIFT, 0, NULL, 0),
1224
1225     SND_SOC_DAPM_OUTPUT("HPL"),
1226     SND_SOC_DAPM_OUTPUT("HPR"),
1227     SND_SOC_DAPM_OUTPUT("SPKL"),
1228     SND_SOC_DAPM_OUTPUT("SPKR"),
1229     SND_SOC_DAPM_OUTPUT("RCVL"),
1230     SND_SOC_DAPM_OUTPUT("RCVR"),
1231 };
1232
1233 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1234     SND_SOC_DAPM_INPUT("DMIC3"),
1235     SND_SOC_DAPM_INPUT("DMIC4"),
1236
1237     SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1238          M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1239     SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1240          M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1241 };
1242
1243 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1244     {"MIC1 Input", NULL, "MIC1"},
1245     {"MIC2 Input", NULL, "MIC2"},
1246
1247     {"DMICL", NULL, "DMICL_ENA"},
1248     {"DMICL", NULL, "DMICR_ENA"},
1249     {"DMICR", NULL, "DMICL_ENA"},
1250     {"DMICR", NULL, "DMICR_ENA"},
1251     {"DMICL", NULL, "AHPF"},
1252     {"DMICR", NULL, "AHPF"},
1253
1254     /* MIC1 input mux */
1255     {"MIC1 Mux", "IN12", "IN12"},
1256     {"MIC1 Mux", "IN56", "IN56"},
1257
1258     /* MIC2 input mux */
1259     {"MIC2 Mux", "IN34", "IN34"},
1260     {"MIC2 Mux", "IN56", "IN56"},
1261
1262     {"MIC1 Input", NULL, "MIC1 Mux"},
1263     {"MIC2 Input", NULL, "MIC2 Mux"},
1264
1265     /* Left ADC input mixer */
1266     {"Left ADC Mixer", "IN12 Switch", "IN12"},
1267     {"Left ADC Mixer", "IN34 Switch", "IN34"},
1268     {"Left ADC Mixer", "IN56 Switch", "IN56"},
1269     {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1270     {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1271     {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1272     {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1273
1274     /* Right ADC input mixer */
1275     {"Right ADC Mixer", "IN12 Switch", "IN12"},
1276     {"Right ADC Mixer", "IN34 Switch", "IN34"},
1277     {"Right ADC Mixer", "IN56 Switch", "IN56"},
1278     {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1279     {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1280     {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1281     {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1282
1283     /* Line A input mixer */
1284     {"LINEA Mixer", "IN1 Switch", "IN1"},
1285     {"LINEA Mixer", "IN3 Switch", "IN3"},
1286     {"LINEA Mixer", "IN5 Switch", "IN5"},
1287     {"LINEA Mixer", "IN34 Switch", "IN34"},
1288
1289     /* Line B input mixer */
1290     {"LINEB Mixer", "IN2 Switch", "IN2"},
1291     {"LINEB Mixer", "IN4 Switch", "IN4"},
1292     {"LINEB Mixer", "IN6 Switch", "IN6"},
1293     {"LINEB Mixer", "IN56 Switch", "IN56"},
1294
1295     {"LINEA Input", NULL, "LINEA Mixer"},
1296     {"LINEB Input", NULL, "LINEB Mixer"},
1297
1298     /* Inputs */
1299     {"ADCL", NULL, "Left ADC Mixer"},
1300     {"ADCR", NULL, "Right ADC Mixer"},
1301     {"ADCL", NULL, "SHDN"},
1302     {"ADCR", NULL, "SHDN"},
1303
1304     {"DMIC Mux", "ADC", "ADCL"},
1305     {"DMIC Mux", "ADC", "ADCR"},
1306     {"DMIC Mux", "DMIC", "DMICL"},
1307     {"DMIC Mux", "DMIC", "DMICR"},
1308
1309     {"LBENL Mux", "Normal", "DMIC Mux"},
1310     {"LBENL Mux", "Loopback", "LTENL Mux"},
1311     {"LBENR Mux", "Normal", "DMIC Mux"},
1312     {"LBENR Mux", "Loopback", "LTENR Mux"},
1313
1314     {"AIFOUTL", NULL, "LBENL Mux"},
1315     {"AIFOUTR", NULL, "LBENR Mux"},
1316     {"AIFOUTL", NULL, "SHDN"},
1317     {"AIFOUTR", NULL, "SHDN"},
1318     {"AIFOUTL", NULL, "SDOEN"},
1319     {"AIFOUTR", NULL, "SDOEN"},
1320
1321     {"LTENL Mux", "Normal", "AIFINL"},
1322     {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1323     {"LTENR Mux", "Normal", "AIFINR"},
1324     {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1325
1326     {"DACL", NULL, "LTENL Mux"},
1327     {"DACR", NULL, "LTENR Mux"},
1328
1329     {"STENL Mux", "Sidetone Left", "ADCL"},
1330     {"STENL Mux", "Sidetone Left", "DMICL"},
1331     {"STENR Mux", "Sidetone Right", "ADCR"},
1332     {"STENR Mux", "Sidetone Right", "DMICR"},
1333     {"DACL", NULL, "STENL Mux"},
1334     {"DACR", NULL, "STENR Mux"},
1335
1336     {"AIFINL", NULL, "SHDN"},
1337     {"AIFINR", NULL, "SHDN"},
1338     {"AIFINL", NULL, "SDIEN"},
1339     {"AIFINR", NULL, "SDIEN"},
1340     {"DACL", NULL, "SHDN"},
1341     {"DACR", NULL, "SHDN"},
1342
1343     /* Left headphone output mixer */
1344     {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1345     {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1346     {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1347     {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1348     {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1349     {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1350
1351     /* Right headphone output mixer */
1352     {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1353     {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1354     {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1355     {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1356     {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1357     {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1358
1359     /* Left speaker output mixer */
1360     {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1361     {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1362     {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1363     {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1364     {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1365     {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1366
1367     /* Right speaker output mixer */
1368     {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1369     {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1370     {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1371     {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1372     {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1373     {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1374
1375     /* Left Receiver output mixer */
1376     {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1377     {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1378     {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1379     {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1380     {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1381     {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1382
1383     /* Right Receiver output mixer */
1384     {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1385     {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1386     {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1387     {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1388     {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1389     {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1390
1391     {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1392
1393     /*
1394      * Disable this for lowest power if bypassing
1395      * the DAC with an analog signal
1396      */
1397     {"HP Left Out", NULL, "DACL"},
1398     {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1399
1400     {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1401
1402     /*
1403      * Disable this for lowest power if bypassing
1404      * the DAC with an analog signal
1405      */
1406     {"HP Right Out", NULL, "DACR"},
1407     {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1408
1409     {"SPK Left Out", NULL, "Left Speaker Mixer"},
1410     {"SPK Right Out", NULL, "Right Speaker Mixer"},
1411     {"RCV Left Out", NULL, "Left Receiver Mixer"},
1412
1413     {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1414     {"LINMOD Mux", "Left Only",  "Left Receiver Mixer"},
1415     {"RCV Right Out", NULL, "LINMOD Mux"},
1416
1417     {"HPL", NULL, "HP Left Out"},
1418     {"HPR", NULL, "HP Right Out"},
1419     {"SPKL", NULL, "SPK Left Out"},
1420     {"SPKR", NULL, "SPK Right Out"},
1421     {"RCVL", NULL, "RCV Left Out"},
1422     {"RCVR", NULL, "RCV Right Out"},
1423 };
1424
1425 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1426     /* DMIC inputs */
1427     {"DMIC3", NULL, "DMIC3_ENA"},
1428     {"DMIC4", NULL, "DMIC4_ENA"},
1429     {"DMIC3", NULL, "AHPF"},
1430     {"DMIC4", NULL, "AHPF"},
1431 };
1432
1433 static int max98090_add_widgets(struct snd_soc_component *component)
1434 {
1435     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1436     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1437
1438     snd_soc_add_component_controls(component, max98090_snd_controls,
1439         ARRAY_SIZE(max98090_snd_controls));
1440
1441     if (max98090->devtype == MAX98091) {
1442         snd_soc_add_component_controls(component, max98091_snd_controls,
1443             ARRAY_SIZE(max98091_snd_controls));
1444     }
1445
1446     snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1447         ARRAY_SIZE(max98090_dapm_widgets));
1448
1449     snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1450         ARRAY_SIZE(max98090_dapm_routes));
1451
1452     if (max98090->devtype == MAX98091) {
1453         snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1454             ARRAY_SIZE(max98091_dapm_widgets));
1455
1456         snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1457             ARRAY_SIZE(max98091_dapm_routes));
1458     }
1459
1460     return 0;
1461 }
1462
1463 static const int pclk_rates[] = {
1464     12000000, 12000000, 13000000, 13000000,
1465     16000000, 16000000, 19200000, 19200000
1466 };
1467
1468 static const int lrclk_rates[] = {
1469     8000, 16000, 8000, 16000,
1470     8000, 16000, 8000, 16000
1471 };
1472
1473 static const int user_pclk_rates[] = {
1474     13000000, 13000000, 19200000, 19200000,
1475 };
1476
1477 static const int user_lrclk_rates[] = {
1478     44100, 48000, 44100, 48000,
1479 };
1480
1481 static const unsigned long long ni_value[] = {
1482     3528, 768, 441, 8
1483 };
1484
1485 static const unsigned long long mi_value[] = {
1486     8125, 1625, 1500, 25
1487 };
1488
1489 static void max98090_configure_bclk(struct snd_soc_component *component)
1490 {
1491     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1492     unsigned long long ni;
1493     int i;
1494
1495     if (!max98090->sysclk) {
1496         dev_err(component->dev, "No SYSCLK configured\n");
1497         return;
1498     }
1499
1500     if (!max98090->bclk || !max98090->lrclk) {
1501         dev_err(component->dev, "No audio clocks configured\n");
1502         return;
1503     }
1504
1505     /* Skip configuration when operating as slave */
1506     if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) &
1507         M98090_MAS_MASK)) {
1508         return;
1509     }
1510
1511     /* Check for supported PCLK to LRCLK ratios */
1512     for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1513         if ((pclk_rates[i] == max98090->sysclk) &&
1514             (lrclk_rates[i] == max98090->lrclk)) {
1515             dev_dbg(component->dev,
1516                 "Found supported PCLK to LRCLK rates 0x%x\n",
1517                 i + 0x8);
1518
1519             snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1520                 M98090_FREQ_MASK,
1521                 (i + 0x8) << M98090_FREQ_SHIFT);
1522             snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1523                 M98090_USE_M1_MASK, 0);
1524             return;
1525         }
1526     }
1527
1528     /* Check for user calculated MI and NI ratios */
1529     for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1530         if ((user_pclk_rates[i] == max98090->sysclk) &&
1531             (user_lrclk_rates[i] == max98090->lrclk)) {
1532             dev_dbg(component->dev,
1533                 "Found user supported PCLK to LRCLK rates\n");
1534             dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1535                 i, ni_value[i], mi_value[i]);
1536
1537             snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1538                 M98090_FREQ_MASK, 0);
1539             snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1540                 M98090_USE_M1_MASK,
1541                     1 << M98090_USE_M1_SHIFT);
1542
1543             snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1544                 (ni_value[i] >> 8) & 0x7F);
1545             snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
1546                 ni_value[i] & 0xFF);
1547             snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
1548                 (mi_value[i] >> 8) & 0x7F);
1549             snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
1550                 mi_value[i] & 0xFF);
1551
1552             return;
1553         }
1554     }
1555
1556     /*
1557      * Calculate based on MI = 65536 (not as good as either method above)
1558      */
1559     snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1560         M98090_FREQ_MASK, 0);
1561     snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1562         M98090_USE_M1_MASK, 0);
1563
1564     /*
1565      * Configure NI when operating as master
1566      * Note: There is a small, but significant audio quality improvement
1567      * by calculating ni and mi.
1568      */
1569     ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1570             * (unsigned long long int)max98090->lrclk;
1571     do_div(ni, (unsigned long long int)max98090->sysclk);
1572     dev_info(component->dev, "No better method found\n");
1573     dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1574     snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1575         (ni >> 8) & 0x7F);
1576     snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1577 }
1578
1579 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1580                  unsigned int fmt)
1581 {
1582     struct snd_soc_component *component = codec_dai->component;
1583     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1584     struct max98090_cdata *cdata;
1585     u8 regval;
1586
1587     max98090->dai_fmt = fmt;
1588     cdata = &max98090->dai[0];
1589
1590     if (fmt != cdata->fmt) {
1591         cdata->fmt = fmt;
1592
1593         regval = 0;
1594         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1595         case SND_SOC_DAIFMT_CBC_CFC:
1596             /* Set to consumer mode PLL - MAS mode off */
1597             snd_soc_component_write(component,
1598                 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1599             snd_soc_component_write(component,
1600                 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1601             snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1602                 M98090_USE_M1_MASK, 0);
1603             max98090->master = false;
1604             break;
1605         case SND_SOC_DAIFMT_CBP_CFP:
1606             /* Set to provider mode */
1607             if (max98090->tdm_slots == 4) {
1608                 /* TDM */
1609                 regval |= M98090_MAS_MASK |
1610                     M98090_BSEL_64;
1611             } else if (max98090->tdm_slots == 3) {
1612                 /* TDM */
1613                 regval |= M98090_MAS_MASK |
1614                     M98090_BSEL_48;
1615             } else {
1616                 /* Few TDM slots, or No TDM */
1617                 regval |= M98090_MAS_MASK |
1618                     M98090_BSEL_32;
1619             }
1620             max98090->master = true;
1621             break;
1622         default:
1623             dev_err(component->dev, "DAI clock mode unsupported");
1624             return -EINVAL;
1625         }
1626         snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1627
1628         regval = 0;
1629         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1630         case SND_SOC_DAIFMT_I2S:
1631             regval |= M98090_DLY_MASK;
1632             break;
1633         case SND_SOC_DAIFMT_LEFT_J:
1634             break;
1635         case SND_SOC_DAIFMT_RIGHT_J:
1636             regval |= M98090_RJ_MASK;
1637             break;
1638         case SND_SOC_DAIFMT_DSP_A:
1639             /* Not supported mode */
1640         default:
1641             dev_err(component->dev, "DAI format unsupported");
1642             return -EINVAL;
1643         }
1644
1645         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1646         case SND_SOC_DAIFMT_NB_NF:
1647             break;
1648         case SND_SOC_DAIFMT_NB_IF:
1649             regval |= M98090_WCI_MASK;
1650             break;
1651         case SND_SOC_DAIFMT_IB_NF:
1652             regval |= M98090_BCI_MASK;
1653             break;
1654         case SND_SOC_DAIFMT_IB_IF:
1655             regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1656             break;
1657         default:
1658             dev_err(component->dev, "DAI invert mode unsupported");
1659             return -EINVAL;
1660         }
1661
1662         /*
1663          * This accommodates an inverted logic in the MAX98090 chip
1664          * for Bit Clock Invert (BCI). The inverted logic is only
1665          * seen for the case of TDM mode. The remaining cases have
1666          * normal logic.
1667          */
1668         if (max98090->tdm_slots > 1)
1669             regval ^= M98090_BCI_MASK;
1670
1671         snd_soc_component_write(component,
1672             M98090_REG_INTERFACE_FORMAT, regval);
1673     }
1674
1675     return 0;
1676 }
1677
1678 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1679     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1680 {
1681     struct snd_soc_component *component = codec_dai->component;
1682     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1683     struct max98090_cdata *cdata;
1684     cdata = &max98090->dai[0];
1685
1686     if (slots < 0 || slots > 4)
1687         return -EINVAL;
1688
1689     max98090->tdm_slots = slots;
1690     max98090->tdm_width = slot_width;
1691
1692     if (max98090->tdm_slots > 1) {
1693         /* SLOTL SLOTR SLOTDLY */
1694         snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1695             0 << M98090_TDM_SLOTL_SHIFT |
1696             1 << M98090_TDM_SLOTR_SHIFT |
1697             0 << M98090_TDM_SLOTDLY_SHIFT);
1698
1699         /* FSW TDM */
1700         snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1701             M98090_TDM_MASK,
1702             M98090_TDM_MASK);
1703     }
1704
1705     /*
1706      * Normally advisable to set TDM first, but this permits either order
1707      */
1708     cdata->fmt = 0;
1709     max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1710
1711     return 0;
1712 }
1713
1714 static int max98090_set_bias_level(struct snd_soc_component *component,
1715                    enum snd_soc_bias_level level)
1716 {
1717     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1718     int ret;
1719
1720     switch (level) {
1721     case SND_SOC_BIAS_ON:
1722         break;
1723
1724     case SND_SOC_BIAS_PREPARE:
1725         /*
1726          * SND_SOC_BIAS_PREPARE is called while preparing for a
1727          * transition to ON or away from ON. If current bias_level
1728          * is SND_SOC_BIAS_ON, then it is preparing for a transition
1729          * away from ON. Disable the clock in that case, otherwise
1730          * enable it.
1731          */
1732         if (IS_ERR(max98090->mclk))
1733             break;
1734
1735         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1736             clk_disable_unprepare(max98090->mclk);
1737         } else {
1738             ret = clk_prepare_enable(max98090->mclk);
1739             if (ret)
1740                 return ret;
1741         }
1742         break;
1743
1744     case SND_SOC_BIAS_STANDBY:
1745         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1746             ret = regcache_sync(max98090->regmap);
1747             if (ret != 0) {
1748                 dev_err(component->dev,
1749                     "Failed to sync cache: %d\n", ret);
1750                 return ret;
1751             }
1752         }
1753         break;
1754
1755     case SND_SOC_BIAS_OFF:
1756         /* Set internal pull-up to lowest power mode */
1757         snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
1758             M98090_JDWK_MASK, M98090_JDWK_MASK);
1759         regcache_mark_dirty(max98090->regmap);
1760         break;
1761     }
1762     return 0;
1763 }
1764
1765 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1766
1767 static const int comp_lrclk_rates[] = {
1768     8000, 16000, 32000, 44100, 48000, 96000
1769 };
1770
1771 struct dmic_table {
1772     int pclk;
1773     struct {
1774         int freq;
1775         int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1776     } settings[6]; /* One for each dmic divisor. */
1777 };
1778
1779 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1780     {
1781         .pclk = 11289600,
1782         .settings = {
1783             { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1784             { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1785             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1786             { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1787             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1788             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1789         },
1790     },
1791     {
1792         .pclk = 12000000,
1793         .settings = {
1794             { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1795             { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1796             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1797             { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1798             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1799             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1800         }
1801     },
1802     {
1803         .pclk = 12288000,
1804         .settings = {
1805             { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1806             { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1807             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1808             { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1809             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1810             { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1811         }
1812     },
1813     {
1814         .pclk = 13000000,
1815         .settings = {
1816             { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1817             { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1818             { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1819             { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1820             { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1821             { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1822         }
1823     },
1824     {
1825         .pclk = 19200000,
1826         .settings = {
1827             { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1828             { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1829             { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1830             { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1831             { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1832             { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1833         }
1834     },
1835 };
1836
1837 static int max98090_find_divisor(int target_freq, int pclk)
1838 {
1839     int current_diff = INT_MAX;
1840     int test_diff;
1841     int divisor_index = 0;
1842     int i;
1843
1844     for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1845         test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1846         if (test_diff < current_diff) {
1847             current_diff = test_diff;
1848             divisor_index = i;
1849         }
1850     }
1851
1852     return divisor_index;
1853 }
1854
1855 static int max98090_find_closest_pclk(int pclk)
1856 {
1857     int m1;
1858     int m2;
1859     int i;
1860
1861     for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1862         if (pclk == dmic_table[i].pclk)
1863             return i;
1864         if (pclk < dmic_table[i].pclk) {
1865             if (i == 0)
1866                 return i;
1867             m1 = pclk - dmic_table[i-1].pclk;
1868             m2 = dmic_table[i].pclk - pclk;
1869             if (m1 < m2)
1870                 return i - 1;
1871             else
1872                 return i;
1873         }
1874     }
1875
1876     return -EINVAL;
1877 }
1878
1879 static int max98090_configure_dmic(struct max98090_priv *max98090,
1880                    int target_dmic_clk, int pclk, int fs)
1881 {
1882     int micclk_index;
1883     int pclk_index;
1884     int dmic_freq;
1885     int dmic_comp;
1886     int i;
1887
1888     pclk_index = max98090_find_closest_pclk(pclk);
1889     if (pclk_index < 0)
1890         return pclk_index;
1891
1892     micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1893
1894     for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1895         if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1896             break;
1897     }
1898
1899     dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1900     dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1901
1902     regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1903                M98090_MICCLK_MASK,
1904                micclk_index << M98090_MICCLK_SHIFT);
1905
1906     regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1907                M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1908                dmic_comp << M98090_DMIC_COMP_SHIFT |
1909                dmic_freq << M98090_DMIC_FREQ_SHIFT);
1910
1911     return 0;
1912 }
1913
1914 static int max98090_dai_startup(struct snd_pcm_substream *substream,
1915                 struct snd_soc_dai *dai)
1916 {
1917     struct snd_soc_component *component = dai->component;
1918     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1919     unsigned int fmt = max98090->dai_fmt;
1920
1921     /* Remove 24-bit format support if it is not in right justified mode. */
1922     if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
1923         substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1924         snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1925     }
1926     return 0;
1927 }
1928
1929 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1930                    struct snd_pcm_hw_params *params,
1931                    struct snd_soc_dai *dai)
1932 {
1933     struct snd_soc_component *component = dai->component;
1934     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1935     struct max98090_cdata *cdata;
1936
1937     cdata = &max98090->dai[0];
1938     max98090->bclk = snd_soc_params_to_bclk(params);
1939     if (params_channels(params) == 1)
1940         max98090->bclk *= 2;
1941
1942     max98090->lrclk = params_rate(params);
1943
1944     switch (params_width(params)) {
1945     case 16:
1946         snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
1947             M98090_WS_MASK, 0);
1948         break;
1949     default:
1950         return -EINVAL;
1951     }
1952
1953     if (max98090->master)
1954         max98090_configure_bclk(component);
1955
1956     cdata->rate = max98090->lrclk;
1957
1958     /* Update filter mode */
1959     if (max98090->lrclk < 24000)
1960         snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1961             M98090_MODE_MASK, 0);
1962     else
1963         snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1964             M98090_MODE_MASK, M98090_MODE_MASK);
1965
1966     /* Update sample rate mode */
1967     if (max98090->lrclk < 50000)
1968         snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1969             M98090_DHF_MASK, 0);
1970     else
1971         snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1972             M98090_DHF_MASK, M98090_DHF_MASK);
1973
1974     max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1975                 max98090->lrclk);
1976
1977     return 0;
1978 }
1979
1980 /*
1981  * PLL / Sysclk
1982  */
1983 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1984                    int clk_id, unsigned int freq, int dir)
1985 {
1986     struct snd_soc_component *component = dai->component;
1987     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1988
1989     /* Requested clock frequency is already setup */
1990     if (freq == max98090->sysclk)
1991         return 0;
1992
1993     if (!IS_ERR(max98090->mclk)) {
1994         freq = clk_round_rate(max98090->mclk, freq);
1995         clk_set_rate(max98090->mclk, freq);
1996     }
1997
1998     /* Setup clocks for slave mode, and using the PLL
1999      * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2000      *       0x02 (when master clk is 20MHz to 40MHz)..
2001      *       0x03 (when master clk is 40MHz to 60MHz)..
2002      */
2003     if ((freq >= 10000000) && (freq <= 20000000)) {
2004         snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2005             M98090_PSCLK_DIV1);
2006         max98090->pclk = freq;
2007     } else if ((freq > 20000000) && (freq <= 40000000)) {
2008         snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2009             M98090_PSCLK_DIV2);
2010         max98090->pclk = freq >> 1;
2011     } else if ((freq > 40000000) && (freq <= 60000000)) {
2012         snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2013             M98090_PSCLK_DIV4);
2014         max98090->pclk = freq >> 2;
2015     } else {
2016         dev_err(component->dev, "Invalid master clock frequency\n");
2017         return -EINVAL;
2018     }
2019
2020     max98090->sysclk = freq;
2021
2022     return 0;
2023 }
2024
2025 static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute,
2026                  int direction)
2027 {
2028     struct snd_soc_component *component = codec_dai->component;
2029     int regval;
2030
2031     regval = mute ? M98090_DVM_MASK : 0;
2032     snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
2033         M98090_DVM_MASK, regval);
2034
2035     return 0;
2036 }
2037
2038 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2039                 struct snd_soc_dai *dai)
2040 {
2041     struct snd_soc_component *component = dai->component;
2042     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2043
2044     switch (cmd) {
2045     case SNDRV_PCM_TRIGGER_START:
2046     case SNDRV_PCM_TRIGGER_RESUME:
2047     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2048         if (!max98090->master && snd_soc_dai_active(dai) == 1)
2049             queue_delayed_work(system_power_efficient_wq,
2050                        &max98090->pll_det_enable_work,
2051                        msecs_to_jiffies(10));
2052         break;
2053     case SNDRV_PCM_TRIGGER_STOP:
2054     case SNDRV_PCM_TRIGGER_SUSPEND:
2055     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2056         if (!max98090->master && snd_soc_dai_active(dai) == 1)
2057             schedule_work(&max98090->pll_det_disable_work);
2058         break;
2059     default:
2060         break;
2061     }
2062
2063     return 0;
2064 }
2065
2066 static void max98090_pll_det_enable_work(struct work_struct *work)
2067 {
2068     struct max98090_priv *max98090 =
2069         container_of(work, struct max98090_priv,
2070                  pll_det_enable_work.work);
2071     struct snd_soc_component *component = max98090->component;
2072     unsigned int status, mask;
2073
2074     /*
2075      * Clear status register in order to clear possibly already occurred
2076      * PLL unlock. If PLL hasn't still locked, the status will be set
2077      * again and PLL unlock interrupt will occur.
2078      * Note this will clear all status bits
2079      */
2080     regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2081
2082     /*
2083      * Queue jack work in case jack state has just changed but handler
2084      * hasn't run yet
2085      */
2086     regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2087     status &= mask;
2088     if (status & M98090_JDET_MASK)
2089         queue_delayed_work(system_power_efficient_wq,
2090                    &max98090->jack_work,
2091                    msecs_to_jiffies(100));
2092
2093     /* Enable PLL unlock interrupt */
2094     snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2095                 M98090_IULK_MASK,
2096                 1 << M98090_IULK_SHIFT);
2097 }
2098
2099 static void max98090_pll_det_disable_work(struct work_struct *work)
2100 {
2101     struct max98090_priv *max98090 =
2102         container_of(work, struct max98090_priv, pll_det_disable_work);
2103     struct snd_soc_component *component = max98090->component;
2104
2105     cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2106
2107     /* Disable PLL unlock interrupt */
2108     snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2109                 M98090_IULK_MASK, 0);
2110 }
2111
2112 static void max98090_pll_work(struct max98090_priv *max98090)
2113 {
2114     struct snd_soc_component *component = max98090->component;
2115     unsigned int pll;
2116     int i;
2117
2118     if (!snd_soc_component_active(component))
2119         return;
2120
2121     dev_info_ratelimited(component->dev, "PLL unlocked\n");
2122
2123     /*
2124      * As the datasheet suggested, the maximum PLL lock time should be
2125      * 7 msec.  The workaround resets the codec softly by toggling SHDN
2126      * off and on if PLL failed to lock for 10 msec.  Notably, there is
2127      * no suggested hold time for SHDN off.
2128      */
2129
2130     /* Toggle shutdown OFF then ON */
2131     snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2132                 M98090_SHDNN_MASK, 0);
2133     snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2134                 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2135
2136     for (i = 0; i < 10; ++i) {
2137         /* Give PLL time to lock */
2138         usleep_range(1000, 1200);
2139
2140         /* Check lock status */
2141         pll = snd_soc_component_read(
2142                 component, M98090_REG_DEVICE_STATUS);
2143         if (!(pll & M98090_ULK_MASK))
2144             break;
2145     }
2146 }
2147
2148 static void max98090_jack_work(struct work_struct *work)
2149 {
2150     struct max98090_priv *max98090 = container_of(work,
2151         struct max98090_priv,
2152         jack_work.work);
2153     struct snd_soc_component *component = max98090->component;
2154     int status = 0;
2155     int reg;
2156
2157     /* Read a second time */
2158     if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2159
2160         /* Strong pull up allows mic detection */
2161         snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2162             M98090_JDWK_MASK, 0);
2163
2164         msleep(50);
2165
2166         snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2167
2168         /* Weak pull up allows only insertion detection */
2169         snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2170             M98090_JDWK_MASK, M98090_JDWK_MASK);
2171     }
2172
2173     reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2174
2175     switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2176         case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2177             dev_dbg(component->dev, "No Headset Detected\n");
2178
2179             max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2180
2181             status |= 0;
2182
2183             break;
2184
2185         case 0:
2186             if (max98090->jack_state ==
2187                 M98090_JACK_STATE_HEADSET) {
2188
2189                 dev_dbg(component->dev,
2190                     "Headset Button Down Detected\n");
2191
2192                 /*
2193                  * max98090_headset_button_event(codec)
2194                  * could be defined, then called here.
2195                  */
2196
2197                 status |= SND_JACK_HEADSET;
2198                 status |= SND_JACK_BTN_0;
2199
2200                 break;
2201             }
2202
2203             /* Line is reported as Headphone */
2204             /* Nokia Headset is reported as Headphone */
2205             /* Mono Headphone is reported as Headphone */
2206             dev_dbg(component->dev, "Headphone Detected\n");
2207
2208             max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2209
2210             status |= SND_JACK_HEADPHONE;
2211
2212             break;
2213
2214         case M98090_JKSNS_MASK:
2215             dev_dbg(component->dev, "Headset Detected\n");
2216
2217             max98090->jack_state = M98090_JACK_STATE_HEADSET;
2218
2219             status |= SND_JACK_HEADSET;
2220
2221             break;
2222
2223         default:
2224             dev_dbg(component->dev, "Unrecognized Jack Status\n");
2225             break;
2226     }
2227
2228     snd_soc_jack_report(max98090->jack, status,
2229                 SND_JACK_HEADSET | SND_JACK_BTN_0);
2230 }
2231
2232 static irqreturn_t max98090_interrupt(int irq, void *data)
2233 {
2234     struct max98090_priv *max98090 = data;
2235     struct snd_soc_component *component = max98090->component;
2236     int ret;
2237     unsigned int mask;
2238     unsigned int active;
2239
2240     /* Treat interrupt before codec is initialized as spurious */
2241     if (component == NULL)
2242         return IRQ_NONE;
2243
2244     dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2245
2246     ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2247
2248     if (ret != 0) {
2249         dev_err(component->dev,
2250             "failed to read M98090_REG_INTERRUPT_S: %d\n",
2251             ret);
2252         return IRQ_NONE;
2253     }
2254
2255     ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2256
2257     if (ret != 0) {
2258         dev_err(component->dev,
2259             "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2260             ret);
2261         return IRQ_NONE;
2262     }
2263
2264     dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2265         active, mask, active & mask);
2266
2267     active &= mask;
2268
2269     if (!active)
2270         return IRQ_NONE;
2271
2272     if (active & M98090_CLD_MASK)
2273         dev_err(component->dev, "M98090_CLD_MASK\n");
2274
2275     if (active & M98090_SLD_MASK)
2276         dev_dbg(component->dev, "M98090_SLD_MASK\n");
2277
2278     if (active & M98090_ULK_MASK) {
2279         dev_dbg(component->dev, "M98090_ULK_MASK\n");
2280         max98090_pll_work(max98090);
2281     }
2282
2283     if (active & M98090_JDET_MASK) {
2284         dev_dbg(component->dev, "M98090_JDET_MASK\n");
2285
2286         pm_wakeup_event(component->dev, 100);
2287
2288         queue_delayed_work(system_power_efficient_wq,
2289                    &max98090->jack_work,
2290                    msecs_to_jiffies(100));
2291     }
2292
2293     if (active & M98090_DRCACT_MASK)
2294         dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2295
2296     if (active & M98090_DRCCLP_MASK)
2297         dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2298
2299     return IRQ_HANDLED;
2300 }
2301
2302 /**
2303  * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2304  *
2305  * @component:  MAX98090 component
2306  * @jack:   jack to report detection events on
2307  *
2308  * Enable microphone detection via IRQ on the MAX98090.  If GPIOs are
2309  * being used to bring out signals to the processor then only platform
2310  * data configuration is needed for MAX98090 and processor GPIOs should
2311  * be configured using snd_soc_jack_add_gpios() instead.
2312  *
2313  * If no jack is supplied detection will be disabled.
2314  */
2315 int max98090_mic_detect(struct snd_soc_component *component,
2316     struct snd_soc_jack *jack)
2317 {
2318     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2319
2320     dev_dbg(component->dev, "max98090_mic_detect\n");
2321
2322     max98090->jack = jack;
2323     if (jack) {
2324         snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2325             M98090_IJDET_MASK,
2326             1 << M98090_IJDET_SHIFT);
2327     } else {
2328         snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2329             M98090_IJDET_MASK,
2330             0);
2331     }
2332
2333     /* Send an initial empty report */
2334     snd_soc_jack_report(max98090->jack, 0,
2335                 SND_JACK_HEADSET | SND_JACK_BTN_0);
2336
2337     queue_delayed_work(system_power_efficient_wq,
2338                &max98090->jack_work,
2339                msecs_to_jiffies(100));
2340
2341     return 0;
2342 }
2343 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2344
2345 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2346 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2347
2348 static const struct snd_soc_dai_ops max98090_dai_ops = {
2349     .startup = max98090_dai_startup,
2350     .set_sysclk = max98090_dai_set_sysclk,
2351     .set_fmt = max98090_dai_set_fmt,
2352     .set_tdm_slot = max98090_set_tdm_slot,
2353     .hw_params = max98090_dai_hw_params,
2354     .mute_stream = max98090_dai_mute,
2355     .trigger = max98090_dai_trigger,
2356     .no_capture_mute = 1,
2357 };
2358
2359 static struct snd_soc_dai_driver max98090_dai[] = {
2360 {
2361     .name = "HiFi",
2362     .playback = {
2363         .stream_name = "HiFi Playback",
2364         .channels_min = 2,
2365         .channels_max = 2,
2366         .rates = MAX98090_RATES,
2367         .formats = MAX98090_FORMATS,
2368     },
2369     .capture = {
2370         .stream_name = "HiFi Capture",
2371         .channels_min = 1,
2372         .channels_max = 2,
2373         .rates = MAX98090_RATES,
2374         .formats = MAX98090_FORMATS,
2375     },
2376      .ops = &max98090_dai_ops,
2377 }
2378 };
2379
2380 static int max98090_probe(struct snd_soc_component *component)
2381 {
2382     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2383     struct max98090_cdata *cdata;
2384     enum max98090_type devtype;
2385     int ret = 0;
2386     int err;
2387     unsigned int micbias;
2388
2389     dev_dbg(component->dev, "max98090_probe\n");
2390
2391     max98090->mclk = devm_clk_get(component->dev, "mclk");
2392     if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2393         return -EPROBE_DEFER;
2394
2395     max98090->component = component;
2396
2397     /* Reset the codec, the DSP core, and disable all interrupts */
2398     max98090_reset(max98090);
2399
2400     /* Initialize private data */
2401
2402     max98090->sysclk = (unsigned)-1;
2403     max98090->pclk = (unsigned)-1;
2404     max98090->master = false;
2405
2406     cdata = &max98090->dai[0];
2407     cdata->rate = (unsigned)-1;
2408     cdata->fmt  = (unsigned)-1;
2409
2410     max98090->lin_state = 0;
2411     max98090->pa1en = 0;
2412     max98090->pa2en = 0;
2413
2414     ret = snd_soc_component_read(component, M98090_REG_REVISION_ID);
2415     if (ret < 0) {
2416         dev_err(component->dev, "Failed to read device revision: %d\n",
2417             ret);
2418         goto err_access;
2419     }
2420
2421     if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2422         devtype = MAX98090;
2423         dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2424     } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2425         devtype = MAX98091;
2426         dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2427     } else {
2428         devtype = MAX98090;
2429         dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2430     }
2431
2432     if (max98090->devtype != devtype) {
2433         dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2434         max98090->devtype = devtype;
2435     }
2436
2437     max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2438
2439     INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2440     INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2441               max98090_pll_det_enable_work);
2442     INIT_WORK(&max98090->pll_det_disable_work,
2443           max98090_pll_det_disable_work);
2444
2445     /* Enable jack detection */
2446     snd_soc_component_write(component, M98090_REG_JACK_DETECT,
2447         M98090_JDETEN_MASK | M98090_JDEB_25MS);
2448
2449     /*
2450      * Clear any old interrupts.
2451      * An old interrupt ocurring prior to installing the ISR
2452      * can keep a new interrupt from generating a trigger.
2453      */
2454     snd_soc_component_read(component, M98090_REG_DEVICE_STATUS);
2455
2456     /* High Performance is default */
2457     snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2458         M98090_DACHP_MASK,
2459         1 << M98090_DACHP_SHIFT);
2460     snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2461         M98090_PERFMODE_MASK,
2462         0 << M98090_PERFMODE_SHIFT);
2463     snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2464         M98090_ADCHP_MASK,
2465         1 << M98090_ADCHP_SHIFT);
2466
2467     /* Turn on VCM bandgap reference */
2468     snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2469         M98090_VCM_MODE_MASK);
2470
2471     err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2472     if (err) {
2473         micbias = M98090_MBVSEL_2V8;
2474         dev_info(component->dev, "use default 2.8v micbias\n");
2475     } else if (micbias > M98090_MBVSEL_2V8) {
2476         dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2477         micbias = M98090_MBVSEL_2V8;
2478     }
2479
2480     snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
2481         M98090_MBVSEL_MASK, micbias);
2482
2483     max98090_add_widgets(component);
2484
2485 err_access:
2486     return ret;
2487 }
2488
2489 static void max98090_remove(struct snd_soc_component *component)
2490 {
2491     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2492
2493     cancel_delayed_work_sync(&max98090->jack_work);
2494     cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2495     cancel_work_sync(&max98090->pll_det_disable_work);
2496     max98090->component = NULL;
2497 }
2498
2499 static void max98090_seq_notifier(struct snd_soc_component *component,
2500     enum snd_soc_dapm_type event, int subseq)
2501 {
2502     struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2503
2504     if (max98090->shdn_pending) {
2505         snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2506                 M98090_SHDNN_MASK, 0);
2507         msleep(40);
2508         snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2509                 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2510         max98090->shdn_pending = false;
2511     }
2512 }
2513
2514 static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2515     .probe          = max98090_probe,
2516     .remove         = max98090_remove,
2517     .seq_notifier       = max98090_seq_notifier,
2518     .set_bias_level     = max98090_set_bias_level,
2519     .idle_bias_on       = 1,
2520     .use_pmdown_time    = 1,
2521     .endianness     = 1,
2522 };
2523
2524 static const struct regmap_config max98090_regmap = {
2525     .reg_bits = 8,
2526     .val_bits = 8,
2527
2528     .max_register = MAX98090_MAX_REGISTER,
2529     .reg_defaults = max98090_reg,
2530     .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2531     .volatile_reg = max98090_volatile_register,
2532     .readable_reg = max98090_readable_register,
2533     .cache_type = REGCACHE_RBTREE,
2534 };
2535
2536 static const struct i2c_device_id max98090_i2c_id[] = {
2537     { "max98090", MAX98090 },
2538     { "max98091", MAX98091 },
2539     { }
2540 };
2541 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2542
2543 static int max98090_i2c_probe(struct i2c_client *i2c)
2544 {
2545     struct max98090_priv *max98090;
2546     const struct acpi_device_id *acpi_id;
2547     kernel_ulong_t driver_data = 0;
2548     int ret;
2549
2550     pr_debug("max98090_i2c_probe\n");
2551
2552     max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2553         GFP_KERNEL);
2554     if (max98090 == NULL)
2555         return -ENOMEM;
2556
2557     if (ACPI_HANDLE(&i2c->dev)) {
2558         acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2559                         &i2c->dev);
2560         if (!acpi_id) {
2561             dev_err(&i2c->dev, "No driver data\n");
2562             return -EINVAL;
2563         }
2564         driver_data = acpi_id->driver_data;
2565     } else {
2566         const struct i2c_device_id *i2c_id =
2567             i2c_match_id(max98090_i2c_id, i2c);
2568         driver_data = i2c_id->driver_data;
2569     }
2570
2571     max98090->devtype = driver_data;
2572     i2c_set_clientdata(i2c, max98090);
2573     max98090->pdata = i2c->dev.platform_data;
2574
2575     ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2576                    &max98090->dmic_freq);
2577     if (ret < 0)
2578         max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2579
2580     max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2581     if (IS_ERR(max98090->regmap)) {
2582         ret = PTR_ERR(max98090->regmap);
2583         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2584         goto err_enable;
2585     }
2586
2587     ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2588         max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2589         "max98090_interrupt", max98090);
2590     if (ret < 0) {
2591         dev_err(&i2c->dev, "request_irq failed: %d\n",
2592             ret);
2593         return ret;
2594     }
2595
2596     ret = devm_snd_soc_register_component(&i2c->dev,
2597             &soc_component_dev_max98090, max98090_dai,
2598             ARRAY_SIZE(max98090_dai));
2599 err_enable:
2600     return ret;
2601 }
2602
2603 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2604 {
2605     struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2606
2607     /*
2608      * Enable volume smoothing, disable zero cross.  This will cause
2609      * a quick 40ms ramp to mute on shutdown.
2610      */
2611     regmap_write(max98090->regmap,
2612         M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2613     regmap_write(max98090->regmap,
2614         M98090_REG_DEVICE_SHUTDOWN, 0x00);
2615     msleep(40);
2616 }
2617
2618 static int max98090_i2c_remove(struct i2c_client *client)
2619 {
2620     max98090_i2c_shutdown(client);
2621
2622     return 0;
2623 }
2624
2625 #ifdef CONFIG_PM
2626 static int max98090_runtime_resume(struct device *dev)
2627 {
2628     struct max98090_priv *max98090 = dev_get_drvdata(dev);
2629
2630     regcache_cache_only(max98090->regmap, false);
2631
2632     max98090_reset(max98090);
2633
2634     regcache_sync(max98090->regmap);
2635
2636     return 0;
2637 }
2638
2639 static int max98090_runtime_suspend(struct device *dev)
2640 {
2641     struct max98090_priv *max98090 = dev_get_drvdata(dev);
2642
2643     regcache_cache_only(max98090->regmap, true);
2644
2645     return 0;
2646 }
2647 #endif
2648
2649 #ifdef CONFIG_PM_SLEEP
2650 static int max98090_resume(struct device *dev)
2651 {
2652     struct max98090_priv *max98090 = dev_get_drvdata(dev);
2653     unsigned int status;
2654
2655     regcache_mark_dirty(max98090->regmap);
2656
2657     max98090_reset(max98090);
2658
2659     /* clear IRQ status */
2660     regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2661
2662     regcache_sync(max98090->regmap);
2663
2664     return 0;
2665 }
2666 #endif
2667
2668 static const struct dev_pm_ops max98090_pm = {
2669     SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2670         max98090_runtime_resume, NULL)
2671     SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
2672 };
2673
2674 #ifdef CONFIG_OF
2675 static const struct of_device_id max98090_of_match[] = {
2676     { .compatible = "maxim,max98090", },
2677     { .compatible = "maxim,max98091", },
2678     { }
2679 };
2680 MODULE_DEVICE_TABLE(of, max98090_of_match);
2681 #endif
2682
2683 #ifdef CONFIG_ACPI
2684 static const struct acpi_device_id max98090_acpi_match[] = {
2685     { "193C9890", MAX98090 },
2686     { }
2687 };
2688 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2689 #endif
2690
2691 static struct i2c_driver max98090_i2c_driver = {
2692     .driver = {
2693         .name = "max98090",
2694         .pm = &max98090_pm,
2695         .of_match_table = of_match_ptr(max98090_of_match),
2696         .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2697     },
2698     .probe_new = max98090_i2c_probe,
2699     .shutdown = max98090_i2c_shutdown,
2700     .remove = max98090_i2c_remove,
2701     .id_table = max98090_i2c_id,
2702 };
2703
2704 module_i2c_driver(max98090_i2c_driver);
2705
2706 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2707 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2708 MODULE_LICENSE("GPL");