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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * max98088.c -- MAX98088 ALSA SoC Audio driver
0004  *
0005  * Copyright 2010 Maxim Integrated Products
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/moduleparam.h>
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/pm.h>
0014 #include <linux/i2c.h>
0015 #include <linux/regmap.h>
0016 #include <linux/clk.h>
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/soc.h>
0021 #include <sound/initval.h>
0022 #include <sound/tlv.h>
0023 #include <linux/slab.h>
0024 #include <asm/div64.h>
0025 #include <sound/max98088.h>
0026 #include "max98088.h"
0027 
0028 enum max98088_type {
0029        MAX98088,
0030        MAX98089,
0031 };
0032 
0033 struct max98088_cdata {
0034        unsigned int rate;
0035        unsigned int fmt;
0036        int eq_sel;
0037 };
0038 
0039 struct max98088_priv {
0040     struct regmap *regmap;
0041     enum max98088_type devtype;
0042     struct max98088_pdata *pdata;
0043     struct clk *mclk;
0044     unsigned char mclk_prescaler;
0045     unsigned int sysclk;
0046     struct max98088_cdata dai[2];
0047     int eq_textcnt;
0048     const char **eq_texts;
0049     struct soc_enum eq_enum;
0050     u8 ina_state;
0051     u8 inb_state;
0052     unsigned int ex_mode;
0053     unsigned int digmic;
0054     unsigned int mic1pre;
0055     unsigned int mic2pre;
0056     unsigned int extmic_mode;
0057 };
0058 
0059 static const struct reg_default max98088_reg[] = {
0060     {  0xf, 0x00 }, /* 0F interrupt enable */
0061 
0062     { 0x10, 0x00 }, /* 10 master clock */
0063     { 0x11, 0x00 }, /* 11 DAI1 clock mode */
0064     { 0x12, 0x00 }, /* 12 DAI1 clock control */
0065     { 0x13, 0x00 }, /* 13 DAI1 clock control */
0066     { 0x14, 0x00 }, /* 14 DAI1 format */
0067     { 0x15, 0x00 }, /* 15 DAI1 clock */
0068     { 0x16, 0x00 }, /* 16 DAI1 config */
0069     { 0x17, 0x00 }, /* 17 DAI1 TDM */
0070     { 0x18, 0x00 }, /* 18 DAI1 filters */
0071     { 0x19, 0x00 }, /* 19 DAI2 clock mode */
0072     { 0x1a, 0x00 }, /* 1A DAI2 clock control */
0073     { 0x1b, 0x00 }, /* 1B DAI2 clock control */
0074     { 0x1c, 0x00 }, /* 1C DAI2 format */
0075     { 0x1d, 0x00 }, /* 1D DAI2 clock */
0076     { 0x1e, 0x00 }, /* 1E DAI2 config */
0077     { 0x1f, 0x00 }, /* 1F DAI2 TDM */
0078 
0079     { 0x20, 0x00 }, /* 20 DAI2 filters */
0080     { 0x21, 0x00 }, /* 21 data config */
0081     { 0x22, 0x00 }, /* 22 DAC mixer */
0082     { 0x23, 0x00 }, /* 23 left ADC mixer */
0083     { 0x24, 0x00 }, /* 24 right ADC mixer */
0084     { 0x25, 0x00 }, /* 25 left HP mixer */
0085     { 0x26, 0x00 }, /* 26 right HP mixer */
0086     { 0x27, 0x00 }, /* 27 HP control */
0087     { 0x28, 0x00 }, /* 28 left REC mixer */
0088     { 0x29, 0x00 }, /* 29 right REC mixer */
0089     { 0x2a, 0x00 }, /* 2A REC control */
0090     { 0x2b, 0x00 }, /* 2B left SPK mixer */
0091     { 0x2c, 0x00 }, /* 2C right SPK mixer */
0092     { 0x2d, 0x00 }, /* 2D SPK control */
0093     { 0x2e, 0x00 }, /* 2E sidetone */
0094     { 0x2f, 0x00 }, /* 2F DAI1 playback level */
0095 
0096     { 0x30, 0x00 }, /* 30 DAI1 playback level */
0097     { 0x31, 0x00 }, /* 31 DAI2 playback level */
0098     { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
0099     { 0x33, 0x00 }, /* 33 left ADC level */
0100     { 0x34, 0x00 }, /* 34 right ADC level */
0101     { 0x35, 0x00 }, /* 35 MIC1 level */
0102     { 0x36, 0x00 }, /* 36 MIC2 level */
0103     { 0x37, 0x00 }, /* 37 INA level */
0104     { 0x38, 0x00 }, /* 38 INB level */
0105     { 0x39, 0x00 }, /* 39 left HP volume */
0106     { 0x3a, 0x00 }, /* 3A right HP volume */
0107     { 0x3b, 0x00 }, /* 3B left REC volume */
0108     { 0x3c, 0x00 }, /* 3C right REC volume */
0109     { 0x3d, 0x00 }, /* 3D left SPK volume */
0110     { 0x3e, 0x00 }, /* 3E right SPK volume */
0111     { 0x3f, 0x00 }, /* 3F MIC config */
0112 
0113     { 0x40, 0x00 }, /* 40 MIC threshold */
0114     { 0x41, 0x00 }, /* 41 excursion limiter filter */
0115     { 0x42, 0x00 }, /* 42 excursion limiter threshold */
0116     { 0x43, 0x00 }, /* 43 ALC */
0117     { 0x44, 0x00 }, /* 44 power limiter threshold */
0118     { 0x45, 0x00 }, /* 45 power limiter config */
0119     { 0x46, 0x00 }, /* 46 distortion limiter config */
0120     { 0x47, 0x00 }, /* 47 audio input */
0121         { 0x48, 0x00 }, /* 48 microphone */
0122     { 0x49, 0x00 }, /* 49 level control */
0123     { 0x4a, 0x00 }, /* 4A bypass switches */
0124     { 0x4b, 0x00 }, /* 4B jack detect */
0125     { 0x4c, 0x00 }, /* 4C input enable */
0126     { 0x4d, 0x00 }, /* 4D output enable */
0127     { 0x4e, 0xF0 }, /* 4E bias control */
0128     { 0x4f, 0x00 }, /* 4F DAC power */
0129 
0130     { 0x50, 0x0F }, /* 50 DAC power */
0131     { 0x51, 0x00 }, /* 51 system */
0132     { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
0133     { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
0134     { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
0135     { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
0136     { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
0137     { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
0138     { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
0139     { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
0140     { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
0141     { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
0142     { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
0143     { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
0144     { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
0145     { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
0146 
0147     { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
0148     { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
0149     { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
0150     { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
0151     { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
0152     { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
0153     { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
0154     { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
0155     { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
0156     { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
0157     { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
0158     { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
0159     { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
0160     { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
0161     { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
0162     { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
0163 
0164     { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
0165     { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
0166     { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
0167     { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
0168     { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
0169     { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
0170     { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
0171     { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
0172     { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
0173     { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
0174     { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
0175     { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
0176     { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
0177     { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
0178     { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
0179     { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
0180 
0181     { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
0182     { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
0183     { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
0184     { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
0185     { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
0186     { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
0187     { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
0188     { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
0189     { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
0190     { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
0191     { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
0192     { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
0193     { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
0194     { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
0195     { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
0196     { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
0197 
0198     { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
0199     { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
0200     { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
0201     { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
0202     { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
0203     { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
0204     { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
0205     { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
0206     { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
0207     { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
0208     { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
0209         { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
0210     { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
0211     { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
0212     { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
0213     { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
0214 
0215     { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
0216     { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
0217     { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
0218     { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
0219     { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
0220     { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
0221     { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
0222     { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
0223     { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
0224     { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
0225     { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
0226     { 0xab, 0x00 }, /* AB DAI2 EQ4 */
0227     { 0xac, 0x00 }, /* AC DAI2 EQ5 */
0228     { 0xad, 0x00 }, /* AD DAI2 EQ5 */
0229     { 0xae, 0x00 }, /* AE DAI2 EQ5 */
0230     { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
0231 
0232     { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
0233     { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
0234     { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
0235     { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
0236     { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
0237     { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
0238     { 0xb6, 0x00 }, /* B6 DAI1 biquad */
0239     { 0xb7, 0x00 }, /* B7 DAI1 biquad */
0240     { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
0241     { 0xb9, 0x00 }, /* B9 DAI1 biquad */
0242     { 0xba, 0x00 }, /* BA DAI1 biquad */
0243     { 0xbb, 0x00 }, /* BB DAI1 biquad */
0244     { 0xbc, 0x00 }, /* BC DAI1 biquad */
0245     { 0xbd, 0x00 }, /* BD DAI1 biquad */
0246     { 0xbe, 0x00 }, /* BE DAI1 biquad */
0247         { 0xbf, 0x00 }, /* BF DAI1 biquad */
0248 
0249     { 0xc0, 0x00 }, /* C0 DAI2 biquad */
0250     { 0xc1, 0x00 }, /* C1 DAI2 biquad */
0251     { 0xc2, 0x00 }, /* C2 DAI2 biquad */
0252     { 0xc3, 0x00 }, /* C3 DAI2 biquad */
0253     { 0xc4, 0x00 }, /* C4 DAI2 biquad */
0254     { 0xc5, 0x00 }, /* C5 DAI2 biquad */
0255     { 0xc6, 0x00 }, /* C6 DAI2 biquad */
0256     { 0xc7, 0x00 }, /* C7 DAI2 biquad */
0257     { 0xc8, 0x00 }, /* C8 DAI2 biquad */
0258     { 0xc9, 0x00 }, /* C9 DAI2 biquad */
0259 };
0260 
0261 static bool max98088_readable_register(struct device *dev, unsigned int reg)
0262 {
0263     switch (reg) {
0264     case M98088_REG_00_IRQ_STATUS ... 0xC9:
0265     case M98088_REG_FF_REV_ID:
0266         return true;
0267     default:
0268         return false;
0269     }
0270 }
0271 
0272 static bool max98088_writeable_register(struct device *dev, unsigned int reg)
0273 {
0274     switch (reg) {
0275     case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
0276         return true;
0277     default:
0278         return false;
0279     }
0280 }
0281 
0282 static bool max98088_volatile_register(struct device *dev, unsigned int reg)
0283 {
0284     switch (reg) {
0285     case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
0286     case M98088_REG_FF_REV_ID:
0287         return true;
0288     default:
0289         return false;
0290     }
0291 }
0292 
0293 static const struct regmap_config max98088_regmap = {
0294     .reg_bits = 8,
0295     .val_bits = 8,
0296 
0297     .readable_reg = max98088_readable_register,
0298     .writeable_reg = max98088_writeable_register,
0299     .volatile_reg = max98088_volatile_register,
0300     .max_register = 0xff,
0301 
0302     .reg_defaults = max98088_reg,
0303     .num_reg_defaults = ARRAY_SIZE(max98088_reg),
0304     .cache_type = REGCACHE_RBTREE,
0305 };
0306 
0307 /*
0308  * Load equalizer DSP coefficient configurations registers
0309  */
0310 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
0311                    unsigned int band, u16 *coefs)
0312 {
0313        unsigned int eq_reg;
0314        unsigned int i;
0315 
0316     if (WARN_ON(band > 4) ||
0317         WARN_ON(dai > 1))
0318         return;
0319 
0320        /* Load the base register address */
0321        eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
0322 
0323        /* Add the band address offset, note adjustment for word address */
0324        eq_reg += band * (M98088_COEFS_PER_BAND << 1);
0325 
0326        /* Step through the registers and coefs */
0327        for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
0328                snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
0329                snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
0330        }
0331 }
0332 
0333 /*
0334  * Excursion limiter modes
0335  */
0336 static const char *max98088_exmode_texts[] = {
0337        "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
0338        "400-600Hz", "400-800Hz",
0339 };
0340 
0341 static const unsigned int max98088_exmode_values[] = {
0342        0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
0343 };
0344 
0345 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
0346                   M98088_REG_41_SPKDHP, 0, 127,
0347                   max98088_exmode_texts,
0348                   max98088_exmode_values);
0349 
0350 static const char *max98088_ex_thresh[] = { /* volts PP */
0351        "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
0352 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
0353                 M98088_REG_42_SPKDHP_THRESH, 0,
0354                 max98088_ex_thresh);
0355 
0356 static const char *max98088_fltr_mode[] = {"Voice", "Music" };
0357 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
0358                 M98088_REG_18_DAI1_FILTERS, 7,
0359                 max98088_fltr_mode);
0360 
0361 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
0362 
0363 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
0364                 M98088_REG_48_CFG_MIC, 0,
0365                 max98088_extmic_text);
0366 
0367 static const struct snd_kcontrol_new max98088_extmic_mux =
0368        SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
0369 
0370 static const char *max98088_dai1_fltr[] = {
0371        "Off", "fc=258/fs=16k", "fc=500/fs=16k",
0372        "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
0373 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
0374                 M98088_REG_18_DAI1_FILTERS, 0,
0375                 max98088_dai1_fltr);
0376 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
0377                 M98088_REG_18_DAI1_FILTERS, 4,
0378                 max98088_dai1_fltr);
0379 
0380 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
0381                                struct snd_ctl_elem_value *ucontrol)
0382 {
0383        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0384        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0385        unsigned int sel = ucontrol->value.integer.value[0];
0386 
0387        max98088->mic1pre = sel;
0388        snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
0389                (1+sel)<<M98088_MICPRE_SHIFT);
0390 
0391        return 0;
0392 }
0393 
0394 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
0395                                struct snd_ctl_elem_value *ucontrol)
0396 {
0397        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0398        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0399 
0400        ucontrol->value.integer.value[0] = max98088->mic1pre;
0401        return 0;
0402 }
0403 
0404 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
0405                                struct snd_ctl_elem_value *ucontrol)
0406 {
0407        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0408        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0409        unsigned int sel = ucontrol->value.integer.value[0];
0410 
0411        max98088->mic2pre = sel;
0412        snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
0413                (1+sel)<<M98088_MICPRE_SHIFT);
0414 
0415        return 0;
0416 }
0417 
0418 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
0419                                struct snd_ctl_elem_value *ucontrol)
0420 {
0421        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0422        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0423 
0424        ucontrol->value.integer.value[0] = max98088->mic2pre;
0425        return 0;
0426 }
0427 
0428 static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
0429     0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
0430     2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
0431 );
0432 
0433 static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
0434     0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
0435     7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
0436     15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
0437     22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
0438     28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
0439 );
0440 
0441 static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
0442     0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
0443     7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
0444     15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
0445     22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
0446     28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
0447 );
0448 
0449 static const struct snd_kcontrol_new max98088_snd_controls[] = {
0450 
0451     SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
0452              M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
0453     SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
0454              M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
0455     SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
0456              M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
0457 
0458        SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
0459                M98088_REG_3A_LVL_HP_R, 7, 1, 1),
0460        SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
0461                M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
0462        SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
0463                M98088_REG_3C_LVL_REC_R, 7, 1, 1),
0464 
0465        SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
0466        SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
0467 
0468        SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
0469                        M98088_REG_35_LVL_MIC1, 5, 2, 0,
0470                        max98088_mic1pre_get, max98088_mic1pre_set,
0471                        max98088_micboost_tlv),
0472        SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
0473                        M98088_REG_36_LVL_MIC2, 5, 2, 0,
0474                        max98088_mic2pre_get, max98088_mic2pre_set,
0475                        max98088_micboost_tlv),
0476 
0477        SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
0478        SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
0479 
0480        SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
0481        SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
0482 
0483        SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
0484        SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
0485 
0486        SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
0487        SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
0488 
0489        SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
0490        SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
0491 
0492        SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
0493        SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
0494        SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
0495        SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
0496                0, 1, 0),
0497 
0498        SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
0499        SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
0500        SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
0501        SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
0502 
0503        SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
0504                4, 15, 0),
0505        SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
0506        SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
0507        SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
0508 
0509        SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
0510        SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
0511 };
0512 
0513 /* Left speaker mixer switch */
0514 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
0515        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
0516        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
0517        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
0518        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
0519        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
0520        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
0521        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
0522        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
0523        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
0524        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
0525 };
0526 
0527 /* Right speaker mixer switch */
0528 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
0529        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
0530        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
0531        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
0532        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
0533        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
0534        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
0535        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
0536        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
0537        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
0538        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
0539 };
0540 
0541 /* Left headphone mixer switch */
0542 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
0543        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
0544        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
0545        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
0546        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
0547        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
0548        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
0549        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
0550        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
0551        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
0552        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
0553 };
0554 
0555 /* Right headphone mixer switch */
0556 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
0557        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
0558        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
0559        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
0560        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
0561        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
0562        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
0563        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
0564        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
0565        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
0566        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
0567 };
0568 
0569 /* Left earpiece/receiver mixer switch */
0570 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
0571        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
0572        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
0573        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
0574        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
0575        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
0576        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
0577        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
0578        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
0579        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
0580        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
0581 };
0582 
0583 /* Right earpiece/receiver mixer switch */
0584 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
0585        SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
0586        SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
0587        SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
0588        SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
0589        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
0590        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
0591        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
0592        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
0593        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
0594        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
0595 };
0596 
0597 /* Left ADC mixer switch */
0598 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
0599        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
0600        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
0601        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
0602        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
0603        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
0604        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
0605 };
0606 
0607 /* Right ADC mixer switch */
0608 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
0609        SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
0610        SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
0611        SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
0612        SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
0613        SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
0614        SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
0615 };
0616 
0617 static int max98088_mic_event(struct snd_soc_dapm_widget *w,
0618                             struct snd_kcontrol *kcontrol, int event)
0619 {
0620        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0621        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0622 
0623        switch (event) {
0624        case SND_SOC_DAPM_POST_PMU:
0625                if (w->reg == M98088_REG_35_LVL_MIC1) {
0626                        snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
0627                                (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
0628                } else {
0629                        snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
0630                                (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
0631                }
0632                break;
0633        case SND_SOC_DAPM_POST_PMD:
0634                snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
0635                break;
0636        default:
0637                return -EINVAL;
0638        }
0639 
0640        return 0;
0641 }
0642 
0643 /*
0644  * The line inputs are 2-channel stereo inputs with the left
0645  * and right channels sharing a common PGA power control signal.
0646  */
0647 static int max98088_line_pga(struct snd_soc_dapm_widget *w,
0648                             int event, int line, u8 channel)
0649 {
0650        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0651        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0652        u8 *state;
0653 
0654     if (WARN_ON(!(channel == 1 || channel == 2)))
0655         return -EINVAL;
0656 
0657        switch (line) {
0658        case LINE_INA:
0659                state = &max98088->ina_state;
0660                break;
0661        case LINE_INB:
0662                state = &max98088->inb_state;
0663                break;
0664        default:
0665                return -EINVAL;
0666        }
0667 
0668        switch (event) {
0669        case SND_SOC_DAPM_POST_PMU:
0670                *state |= channel;
0671                snd_soc_component_update_bits(component, w->reg,
0672                        (1 << w->shift), (1 << w->shift));
0673                break;
0674        case SND_SOC_DAPM_POST_PMD:
0675                *state &= ~channel;
0676                if (*state == 0) {
0677                        snd_soc_component_update_bits(component, w->reg,
0678                                (1 << w->shift), 0);
0679                }
0680                break;
0681        default:
0682                return -EINVAL;
0683        }
0684 
0685        return 0;
0686 }
0687 
0688 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
0689                                   struct snd_kcontrol *k, int event)
0690 {
0691        return max98088_line_pga(w, event, LINE_INA, 1);
0692 }
0693 
0694 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
0695                                   struct snd_kcontrol *k, int event)
0696 {
0697        return max98088_line_pga(w, event, LINE_INA, 2);
0698 }
0699 
0700 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
0701                                   struct snd_kcontrol *k, int event)
0702 {
0703        return max98088_line_pga(w, event, LINE_INB, 1);
0704 }
0705 
0706 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
0707                                   struct snd_kcontrol *k, int event)
0708 {
0709        return max98088_line_pga(w, event, LINE_INB, 2);
0710 }
0711 
0712 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
0713 
0714        SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
0715        SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
0716 
0717        SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
0718                M98088_REG_4D_PWR_EN_OUT, 1, 0),
0719        SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
0720                M98088_REG_4D_PWR_EN_OUT, 0, 0),
0721        SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
0722                M98088_REG_4D_PWR_EN_OUT, 1, 0),
0723        SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
0724                M98088_REG_4D_PWR_EN_OUT, 0, 0),
0725 
0726        SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
0727                7, 0, NULL, 0),
0728        SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
0729                6, 0, NULL, 0),
0730 
0731        SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
0732                5, 0, NULL, 0),
0733        SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
0734                4, 0, NULL, 0),
0735 
0736        SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
0737                3, 0, NULL, 0),
0738        SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
0739                2, 0, NULL, 0),
0740 
0741        SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
0742                &max98088_extmic_mux),
0743 
0744        SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
0745                &max98088_left_hp_mixer_controls[0],
0746                ARRAY_SIZE(max98088_left_hp_mixer_controls)),
0747 
0748        SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
0749                &max98088_right_hp_mixer_controls[0],
0750                ARRAY_SIZE(max98088_right_hp_mixer_controls)),
0751 
0752        SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
0753                &max98088_left_speaker_mixer_controls[0],
0754                ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
0755 
0756        SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
0757                &max98088_right_speaker_mixer_controls[0],
0758                ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
0759 
0760        SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
0761          &max98088_left_rec_mixer_controls[0],
0762                ARRAY_SIZE(max98088_left_rec_mixer_controls)),
0763 
0764        SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
0765          &max98088_right_rec_mixer_controls[0],
0766                ARRAY_SIZE(max98088_right_rec_mixer_controls)),
0767 
0768        SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
0769                &max98088_left_ADC_mixer_controls[0],
0770                ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
0771 
0772        SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
0773                &max98088_right_ADC_mixer_controls[0],
0774                ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
0775 
0776        SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
0777                5, 0, NULL, 0, max98088_mic_event,
0778                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0779 
0780        SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
0781                5, 0, NULL, 0, max98088_mic_event,
0782                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0783 
0784        SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
0785                7, 0, NULL, 0, max98088_pga_ina1_event,
0786                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0787 
0788        SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
0789                7, 0, NULL, 0, max98088_pga_ina2_event,
0790                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0791 
0792        SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
0793                6, 0, NULL, 0, max98088_pga_inb1_event,
0794                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0795 
0796        SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
0797                6, 0, NULL, 0, max98088_pga_inb2_event,
0798                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0799 
0800        SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
0801 
0802        SND_SOC_DAPM_OUTPUT("HPL"),
0803        SND_SOC_DAPM_OUTPUT("HPR"),
0804        SND_SOC_DAPM_OUTPUT("SPKL"),
0805        SND_SOC_DAPM_OUTPUT("SPKR"),
0806        SND_SOC_DAPM_OUTPUT("RECL"),
0807        SND_SOC_DAPM_OUTPUT("RECR"),
0808 
0809        SND_SOC_DAPM_INPUT("MIC1"),
0810        SND_SOC_DAPM_INPUT("MIC2"),
0811        SND_SOC_DAPM_INPUT("INA1"),
0812        SND_SOC_DAPM_INPUT("INA2"),
0813        SND_SOC_DAPM_INPUT("INB1"),
0814        SND_SOC_DAPM_INPUT("INB2"),
0815 };
0816 
0817 static const struct snd_soc_dapm_route max98088_audio_map[] = {
0818        /* Left headphone output mixer */
0819        {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
0820        {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
0821        {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
0822        {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
0823        {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
0824        {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
0825        {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
0826        {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
0827        {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
0828        {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
0829 
0830        /* Right headphone output mixer */
0831        {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
0832        {"Right HP Mixer", "Left DAC2 Switch", "DACL2"  },
0833        {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
0834        {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
0835        {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
0836        {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
0837        {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
0838        {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
0839        {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
0840        {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
0841 
0842        /* Left speaker output mixer */
0843        {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
0844        {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
0845        {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
0846        {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
0847        {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
0848        {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
0849        {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
0850        {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
0851        {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
0852        {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
0853 
0854        /* Right speaker output mixer */
0855        {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
0856        {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
0857        {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
0858        {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
0859        {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
0860        {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
0861        {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
0862        {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
0863        {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
0864        {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
0865 
0866        /* Earpiece/Receiver output mixer */
0867        {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
0868        {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
0869        {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
0870        {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
0871        {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
0872        {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
0873        {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
0874        {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
0875        {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
0876        {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
0877 
0878        /* Earpiece/Receiver output mixer */
0879        {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
0880        {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
0881        {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
0882        {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
0883        {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
0884        {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
0885        {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
0886        {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
0887        {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
0888        {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
0889 
0890        {"HP Left Out", NULL, "Left HP Mixer"},
0891        {"HP Right Out", NULL, "Right HP Mixer"},
0892        {"SPK Left Out", NULL, "Left SPK Mixer"},
0893        {"SPK Right Out", NULL, "Right SPK Mixer"},
0894        {"REC Left Out", NULL, "Left REC Mixer"},
0895        {"REC Right Out", NULL, "Right REC Mixer"},
0896 
0897        {"HPL", NULL, "HP Left Out"},
0898        {"HPR", NULL, "HP Right Out"},
0899        {"SPKL", NULL, "SPK Left Out"},
0900        {"SPKR", NULL, "SPK Right Out"},
0901        {"RECL", NULL, "REC Left Out"},
0902        {"RECR", NULL, "REC Right Out"},
0903 
0904        /* Left ADC input mixer */
0905        {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
0906        {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
0907        {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
0908        {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
0909        {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
0910        {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
0911 
0912        /* Right ADC input mixer */
0913        {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
0914        {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
0915        {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
0916        {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
0917        {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
0918        {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
0919 
0920        /* Inputs */
0921        {"ADCL", NULL, "Left ADC Mixer"},
0922        {"ADCR", NULL, "Right ADC Mixer"},
0923        {"INA1 Input", NULL, "INA1"},
0924        {"INA2 Input", NULL, "INA2"},
0925        {"INB1 Input", NULL, "INB1"},
0926        {"INB2 Input", NULL, "INB2"},
0927        {"MIC1 Input", NULL, "MIC1"},
0928        {"MIC2 Input", NULL, "MIC2"},
0929 };
0930 
0931 /* codec mclk clock divider coefficients */
0932 static const struct {
0933        u32 rate;
0934        u8  sr;
0935 } rate_table[] = {
0936        {8000,  0x10},
0937        {11025, 0x20},
0938        {16000, 0x30},
0939        {22050, 0x40},
0940        {24000, 0x50},
0941        {32000, 0x60},
0942        {44100, 0x70},
0943        {48000, 0x80},
0944        {88200, 0x90},
0945        {96000, 0xA0},
0946 };
0947 
0948 static inline int rate_value(int rate, u8 *value)
0949 {
0950        int i;
0951 
0952        for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
0953                if (rate_table[i].rate >= rate) {
0954                        *value = rate_table[i].sr;
0955                        return 0;
0956                }
0957        }
0958        *value = rate_table[0].sr;
0959        return -EINVAL;
0960 }
0961 
0962 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
0963                                   struct snd_pcm_hw_params *params,
0964                                   struct snd_soc_dai *dai)
0965 {
0966        struct snd_soc_component *component = dai->component;
0967        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
0968        struct max98088_cdata *cdata;
0969        unsigned long long ni;
0970        unsigned int rate;
0971        u8 regval;
0972 
0973        cdata = &max98088->dai[0];
0974 
0975        rate = params_rate(params);
0976 
0977        switch (params_width(params)) {
0978        case 16:
0979                snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
0980                        M98088_DAI_WS, 0);
0981                break;
0982        case 24:
0983                snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
0984                        M98088_DAI_WS, M98088_DAI_WS);
0985                break;
0986        default:
0987                return -EINVAL;
0988        }
0989 
0990        snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
0991 
0992        if (rate_value(rate, &regval))
0993                return -EINVAL;
0994 
0995        snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
0996                M98088_CLKMODE_MASK, regval);
0997        cdata->rate = rate;
0998 
0999        /* Configure NI when operating as master */
1000        if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
1001                & M98088_DAI_MAS) {
1002                unsigned long pclk;
1003 
1004                if (max98088->sysclk == 0) {
1005                        dev_err(component->dev, "Invalid system clock frequency\n");
1006                        return -EINVAL;
1007                }
1008                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1009                                * (unsigned long long int)rate;
1010                pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
1011                ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
1012                snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1013                        (ni >> 8) & 0x7F);
1014                snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1015                        ni & 0xFF);
1016        }
1017 
1018        /* Update sample rate mode */
1019        if (rate < 50000)
1020                snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1021                        M98088_DAI_DHF, 0);
1022        else
1023                snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1024                        M98088_DAI_DHF, M98088_DAI_DHF);
1025 
1026        snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1027                M98088_SHDNRUN);
1028 
1029        return 0;
1030 }
1031 
1032 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1033                                   struct snd_pcm_hw_params *params,
1034                                   struct snd_soc_dai *dai)
1035 {
1036        struct snd_soc_component *component = dai->component;
1037        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1038        struct max98088_cdata *cdata;
1039        unsigned long long ni;
1040        unsigned int rate;
1041        u8 regval;
1042 
1043        cdata = &max98088->dai[1];
1044 
1045        rate = params_rate(params);
1046 
1047        switch (params_width(params)) {
1048        case 16:
1049                snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1050                        M98088_DAI_WS, 0);
1051                break;
1052        case 24:
1053                snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1054                        M98088_DAI_WS, M98088_DAI_WS);
1055                break;
1056        default:
1057                return -EINVAL;
1058        }
1059 
1060        snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1061 
1062        if (rate_value(rate, &regval))
1063                return -EINVAL;
1064 
1065        snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
1066                M98088_CLKMODE_MASK, regval);
1067        cdata->rate = rate;
1068 
1069        /* Configure NI when operating as master */
1070        if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
1071                & M98088_DAI_MAS) {
1072                unsigned long pclk;
1073 
1074                if (max98088->sysclk == 0) {
1075                        dev_err(component->dev, "Invalid system clock frequency\n");
1076                        return -EINVAL;
1077                }
1078                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1079                                * (unsigned long long int)rate;
1080                pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
1081                ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
1082                snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1083                        (ni >> 8) & 0x7F);
1084                snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1085                        ni & 0xFF);
1086        }
1087 
1088        /* Update sample rate mode */
1089        if (rate < 50000)
1090                snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1091                        M98088_DAI_DHF, 0);
1092        else
1093                snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1094                        M98088_DAI_DHF, M98088_DAI_DHF);
1095 
1096        snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1097                M98088_SHDNRUN);
1098 
1099        return 0;
1100 }
1101 
1102 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1103                                   int clk_id, unsigned int freq, int dir)
1104 {
1105        struct snd_soc_component *component = dai->component;
1106        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1107 
1108        /* Requested clock frequency is already setup */
1109        if (freq == max98088->sysclk)
1110                return 0;
1111 
1112     if (!IS_ERR(max98088->mclk)) {
1113         freq = clk_round_rate(max98088->mclk, freq);
1114         clk_set_rate(max98088->mclk, freq);
1115     }
1116 
1117        /* Setup clocks for slave mode, and using the PLL
1118         * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1119         *         0x02 (when master clk is 20MHz to 30MHz)..
1120         */
1121        if ((freq >= 10000000) && (freq < 20000000)) {
1122                snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
1123                max98088->mclk_prescaler = 1;
1124        } else if ((freq >= 20000000) && (freq < 30000000)) {
1125                snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
1126                max98088->mclk_prescaler = 2;
1127        } else {
1128                dev_err(component->dev, "Invalid master clock frequency\n");
1129                return -EINVAL;
1130        }
1131 
1132        if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS)  & M98088_SHDNRUN) {
1133                snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1134                        M98088_SHDNRUN, 0);
1135                snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1136                        M98088_SHDNRUN, M98088_SHDNRUN);
1137        }
1138 
1139        dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1140 
1141        max98088->sysclk = freq;
1142        return 0;
1143 }
1144 
1145 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1146                                 unsigned int fmt)
1147 {
1148        struct snd_soc_component *component = codec_dai->component;
1149        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1150        struct max98088_cdata *cdata;
1151        u8 reg15val;
1152        u8 reg14val = 0;
1153 
1154        cdata = &max98088->dai[0];
1155 
1156        if (fmt != cdata->fmt) {
1157                cdata->fmt = fmt;
1158 
1159                switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1160                case SND_SOC_DAIFMT_CBC_CFC:
1161                        /* Consumer mode PLL */
1162                        snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1163                                0x80);
1164                        snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1165                                0x00);
1166                        break;
1167                case SND_SOC_DAIFMT_CBP_CFP:
1168                        /* Set to provider mode */
1169                        reg14val |= M98088_DAI_MAS;
1170                        break;
1171                default:
1172                        dev_err(component->dev, "Clock mode unsupported");
1173                        return -EINVAL;
1174                }
1175 
1176                switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1177                case SND_SOC_DAIFMT_I2S:
1178                        reg14val |= M98088_DAI_DLY;
1179                        break;
1180                case SND_SOC_DAIFMT_LEFT_J:
1181                        break;
1182                default:
1183                        return -EINVAL;
1184                }
1185 
1186                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1187                case SND_SOC_DAIFMT_NB_NF:
1188                        break;
1189                case SND_SOC_DAIFMT_NB_IF:
1190                        reg14val |= M98088_DAI_WCI;
1191                        break;
1192                case SND_SOC_DAIFMT_IB_NF:
1193                        reg14val |= M98088_DAI_BCI;
1194                        break;
1195                case SND_SOC_DAIFMT_IB_IF:
1196                        reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1197                        break;
1198                default:
1199                        return -EINVAL;
1200                }
1201 
1202                snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
1203                        M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1204                        M98088_DAI_WCI, reg14val);
1205 
1206                reg15val = M98088_DAI_BSEL64;
1207                if (max98088->digmic)
1208                        reg15val |= M98088_DAI_OSR64;
1209                snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
1210        }
1211 
1212        return 0;
1213 }
1214 
1215 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1216                                 unsigned int fmt)
1217 {
1218        struct snd_soc_component *component = codec_dai->component;
1219        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1220        struct max98088_cdata *cdata;
1221        u8 reg1Cval = 0;
1222 
1223        cdata = &max98088->dai[1];
1224 
1225        if (fmt != cdata->fmt) {
1226                cdata->fmt = fmt;
1227 
1228                switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1229                case SND_SOC_DAIFMT_CBC_CFC:
1230                        /* Consumer mode PLL */
1231                        snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1232                                0x80);
1233                        snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1234                                0x00);
1235                        break;
1236                case SND_SOC_DAIFMT_CBP_CFP:
1237                        /* Set to provider mode */
1238                        reg1Cval |= M98088_DAI_MAS;
1239                        break;
1240                default:
1241                        dev_err(component->dev, "Clock mode unsupported");
1242                        return -EINVAL;
1243                }
1244 
1245                switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1246                case SND_SOC_DAIFMT_I2S:
1247                        reg1Cval |= M98088_DAI_DLY;
1248                        break;
1249                case SND_SOC_DAIFMT_LEFT_J:
1250                        break;
1251                default:
1252                        return -EINVAL;
1253                }
1254 
1255                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1256                case SND_SOC_DAIFMT_NB_NF:
1257                        break;
1258                case SND_SOC_DAIFMT_NB_IF:
1259                        reg1Cval |= M98088_DAI_WCI;
1260                        break;
1261                case SND_SOC_DAIFMT_IB_NF:
1262                        reg1Cval |= M98088_DAI_BCI;
1263                        break;
1264                case SND_SOC_DAIFMT_IB_IF:
1265                        reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1266                        break;
1267                default:
1268                        return -EINVAL;
1269                }
1270 
1271                snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1272                        M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1273                        M98088_DAI_WCI, reg1Cval);
1274 
1275                snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
1276                        M98088_DAI_BSEL64);
1277        }
1278 
1279        return 0;
1280 }
1281 
1282 static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute,
1283                   int direction)
1284 {
1285        struct snd_soc_component *component = codec_dai->component;
1286        int reg;
1287 
1288        if (mute)
1289                reg = M98088_DAI_MUTE;
1290        else
1291                reg = 0;
1292 
1293        snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
1294                            M98088_DAI_MUTE_MASK, reg);
1295        return 0;
1296 }
1297 
1298 static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute,
1299                   int direction)
1300 {
1301        struct snd_soc_component *component = codec_dai->component;
1302        int reg;
1303 
1304        if (mute)
1305                reg = M98088_DAI_MUTE;
1306        else
1307                reg = 0;
1308 
1309        snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
1310                            M98088_DAI_MUTE_MASK, reg);
1311        return 0;
1312 }
1313 
1314 static int max98088_set_bias_level(struct snd_soc_component *component,
1315                                   enum snd_soc_bias_level level)
1316 {
1317     struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1318 
1319     switch (level) {
1320     case SND_SOC_BIAS_ON:
1321         break;
1322 
1323     case SND_SOC_BIAS_PREPARE:
1324         /*
1325          * SND_SOC_BIAS_PREPARE is called while preparing for a
1326          * transition to ON or away from ON. If current bias_level
1327          * is SND_SOC_BIAS_ON, then it is preparing for a transition
1328          * away from ON. Disable the clock in that case, otherwise
1329          * enable it.
1330          */
1331         if (!IS_ERR(max98088->mclk)) {
1332             if (snd_soc_component_get_bias_level(component) ==
1333                 SND_SOC_BIAS_ON)
1334                 clk_disable_unprepare(max98088->mclk);
1335             else
1336                 clk_prepare_enable(max98088->mclk);
1337         }
1338         break;
1339 
1340     case SND_SOC_BIAS_STANDBY:
1341         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1342             regcache_sync(max98088->regmap);
1343 
1344         snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1345                    M98088_MBEN, M98088_MBEN);
1346         break;
1347 
1348     case SND_SOC_BIAS_OFF:
1349         snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1350                     M98088_MBEN, 0);
1351         regcache_mark_dirty(max98088->regmap);
1352         break;
1353     }
1354     return 0;
1355 }
1356 
1357 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1358 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1359 
1360 static const struct snd_soc_dai_ops max98088_dai1_ops = {
1361        .set_sysclk = max98088_dai_set_sysclk,
1362        .set_fmt = max98088_dai1_set_fmt,
1363        .hw_params = max98088_dai1_hw_params,
1364        .mute_stream = max98088_dai1_mute,
1365        .no_capture_mute = 1,
1366 };
1367 
1368 static const struct snd_soc_dai_ops max98088_dai2_ops = {
1369        .set_sysclk = max98088_dai_set_sysclk,
1370        .set_fmt = max98088_dai2_set_fmt,
1371        .hw_params = max98088_dai2_hw_params,
1372        .mute_stream = max98088_dai2_mute,
1373        .no_capture_mute = 1,
1374 };
1375 
1376 static struct snd_soc_dai_driver max98088_dai[] = {
1377 {
1378        .name = "HiFi",
1379        .playback = {
1380                .stream_name = "HiFi Playback",
1381                .channels_min = 1,
1382                .channels_max = 2,
1383                .rates = MAX98088_RATES,
1384                .formats = MAX98088_FORMATS,
1385        },
1386        .capture = {
1387                .stream_name = "HiFi Capture",
1388                .channels_min = 1,
1389                .channels_max = 2,
1390                .rates = MAX98088_RATES,
1391                .formats = MAX98088_FORMATS,
1392        },
1393         .ops = &max98088_dai1_ops,
1394 },
1395 {
1396        .name = "Aux",
1397        .playback = {
1398                .stream_name = "Aux Playback",
1399                .channels_min = 1,
1400                .channels_max = 2,
1401                .rates = MAX98088_RATES,
1402                .formats = MAX98088_FORMATS,
1403        },
1404        .ops = &max98088_dai2_ops,
1405 }
1406 };
1407 
1408 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1409 
1410 static int max98088_get_channel(struct snd_soc_component *component, const char *name)
1411 {
1412     int ret;
1413 
1414     ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name);
1415     if (ret < 0)
1416         dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
1417     return ret;
1418 }
1419 
1420 static void max98088_setup_eq1(struct snd_soc_component *component)
1421 {
1422        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1423        struct max98088_pdata *pdata = max98088->pdata;
1424        struct max98088_eq_cfg *coef_set;
1425        int best, best_val, save, i, sel, fs;
1426        struct max98088_cdata *cdata;
1427 
1428        cdata = &max98088->dai[0];
1429 
1430        if (!pdata || !max98088->eq_textcnt)
1431                return;
1432 
1433        /* Find the selected configuration with nearest sample rate */
1434        fs = cdata->rate;
1435        sel = cdata->eq_sel;
1436 
1437        best = 0;
1438        best_val = INT_MAX;
1439        for (i = 0; i < pdata->eq_cfgcnt; i++) {
1440                if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1441                    abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1442                        best = i;
1443                        best_val = abs(pdata->eq_cfg[i].rate - fs);
1444                }
1445        }
1446 
1447        dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1448                pdata->eq_cfg[best].name,
1449                pdata->eq_cfg[best].rate, fs);
1450 
1451        /* Disable EQ while configuring, and save current on/off state */
1452        save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1453        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1454 
1455        coef_set = &pdata->eq_cfg[sel];
1456 
1457        m98088_eq_band(component, 0, 0, coef_set->band1);
1458        m98088_eq_band(component, 0, 1, coef_set->band2);
1459        m98088_eq_band(component, 0, 2, coef_set->band3);
1460        m98088_eq_band(component, 0, 3, coef_set->band4);
1461        m98088_eq_band(component, 0, 4, coef_set->band5);
1462 
1463        /* Restore the original on/off state */
1464        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1465 }
1466 
1467 static void max98088_setup_eq2(struct snd_soc_component *component)
1468 {
1469        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1470        struct max98088_pdata *pdata = max98088->pdata;
1471        struct max98088_eq_cfg *coef_set;
1472        int best, best_val, save, i, sel, fs;
1473        struct max98088_cdata *cdata;
1474 
1475        cdata = &max98088->dai[1];
1476 
1477        if (!pdata || !max98088->eq_textcnt)
1478                return;
1479 
1480        /* Find the selected configuration with nearest sample rate */
1481        fs = cdata->rate;
1482 
1483        sel = cdata->eq_sel;
1484        best = 0;
1485        best_val = INT_MAX;
1486        for (i = 0; i < pdata->eq_cfgcnt; i++) {
1487                if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1488                    abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1489                        best = i;
1490                        best_val = abs(pdata->eq_cfg[i].rate - fs);
1491                }
1492        }
1493 
1494        dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1495                pdata->eq_cfg[best].name,
1496                pdata->eq_cfg[best].rate, fs);
1497 
1498        /* Disable EQ while configuring, and save current on/off state */
1499        save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1500        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1501 
1502        coef_set = &pdata->eq_cfg[sel];
1503 
1504        m98088_eq_band(component, 1, 0, coef_set->band1);
1505        m98088_eq_band(component, 1, 1, coef_set->band2);
1506        m98088_eq_band(component, 1, 2, coef_set->band3);
1507        m98088_eq_band(component, 1, 3, coef_set->band4);
1508        m98088_eq_band(component, 1, 4, coef_set->band5);
1509 
1510        /* Restore the original on/off state */
1511        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1512                save);
1513 }
1514 
1515 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1516                                 struct snd_ctl_elem_value *ucontrol)
1517 {
1518        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1519        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1520        struct max98088_pdata *pdata = max98088->pdata;
1521        int channel = max98088_get_channel(component, kcontrol->id.name);
1522        struct max98088_cdata *cdata;
1523     int sel = ucontrol->value.enumerated.item[0];
1524 
1525        if (channel < 0)
1526            return channel;
1527 
1528        cdata = &max98088->dai[channel];
1529 
1530        if (sel >= pdata->eq_cfgcnt)
1531                return -EINVAL;
1532 
1533        cdata->eq_sel = sel;
1534 
1535        switch (channel) {
1536        case 0:
1537                max98088_setup_eq1(component);
1538                break;
1539        case 1:
1540                max98088_setup_eq2(component);
1541                break;
1542        }
1543 
1544        return 0;
1545 }
1546 
1547 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1548                                 struct snd_ctl_elem_value *ucontrol)
1549 {
1550        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1551        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1552        int channel = max98088_get_channel(component, kcontrol->id.name);
1553        struct max98088_cdata *cdata;
1554 
1555        if (channel < 0)
1556            return channel;
1557 
1558        cdata = &max98088->dai[channel];
1559        ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1560        return 0;
1561 }
1562 
1563 static void max98088_handle_eq_pdata(struct snd_soc_component *component)
1564 {
1565        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1566        struct max98088_pdata *pdata = max98088->pdata;
1567        struct max98088_eq_cfg *cfg;
1568        unsigned int cfgcnt;
1569        int i, j;
1570        const char **t;
1571        int ret;
1572        struct snd_kcontrol_new controls[] = {
1573                SOC_ENUM_EXT((char *)eq_mode_name[0],
1574                        max98088->eq_enum,
1575                        max98088_get_eq_enum,
1576                        max98088_put_eq_enum),
1577                SOC_ENUM_EXT((char *)eq_mode_name[1],
1578                        max98088->eq_enum,
1579                        max98088_get_eq_enum,
1580                        max98088_put_eq_enum),
1581        };
1582        BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
1583 
1584        cfg = pdata->eq_cfg;
1585        cfgcnt = pdata->eq_cfgcnt;
1586 
1587        /* Setup an array of texts for the equalizer enum.
1588         * This is based on Mark Brown's equalizer driver code.
1589         */
1590        max98088->eq_textcnt = 0;
1591        max98088->eq_texts = NULL;
1592        for (i = 0; i < cfgcnt; i++) {
1593                for (j = 0; j < max98088->eq_textcnt; j++) {
1594                        if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1595                                break;
1596                }
1597 
1598                if (j != max98088->eq_textcnt)
1599                        continue;
1600 
1601                /* Expand the array */
1602                t = krealloc(max98088->eq_texts,
1603                             sizeof(char *) * (max98088->eq_textcnt + 1),
1604                             GFP_KERNEL);
1605                if (t == NULL)
1606                        continue;
1607 
1608                /* Store the new entry */
1609                t[max98088->eq_textcnt] = cfg[i].name;
1610                max98088->eq_textcnt++;
1611                max98088->eq_texts = t;
1612        }
1613 
1614        /* Now point the soc_enum to .texts array items */
1615        max98088->eq_enum.texts = max98088->eq_texts;
1616        max98088->eq_enum.items = max98088->eq_textcnt;
1617 
1618        ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1619        if (ret != 0)
1620                dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1621 }
1622 
1623 static void max98088_handle_pdata(struct snd_soc_component *component)
1624 {
1625        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1626        struct max98088_pdata *pdata = max98088->pdata;
1627        u8 regval = 0;
1628 
1629        if (!pdata) {
1630                dev_dbg(component->dev, "No platform data\n");
1631                return;
1632        }
1633 
1634        /* Configure mic for analog/digital mic mode */
1635        if (pdata->digmic_left_mode)
1636                regval |= M98088_DIGMIC_L;
1637 
1638        if (pdata->digmic_right_mode)
1639                regval |= M98088_DIGMIC_R;
1640 
1641        max98088->digmic = (regval ? 1 : 0);
1642 
1643        snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
1644 
1645        /* Configure receiver output */
1646        regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1647        snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
1648                M98088_REC_LINEMODE_MASK, regval);
1649 
1650        /* Configure equalizers */
1651        if (pdata->eq_cfgcnt)
1652                max98088_handle_eq_pdata(component);
1653 }
1654 
1655 static int max98088_probe(struct snd_soc_component *component)
1656 {
1657        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1658        struct max98088_cdata *cdata;
1659        int ret = 0;
1660 
1661        regcache_mark_dirty(max98088->regmap);
1662 
1663        /* initialize private data */
1664 
1665        max98088->sysclk = (unsigned)-1;
1666        max98088->eq_textcnt = 0;
1667 
1668        cdata = &max98088->dai[0];
1669        cdata->rate = (unsigned)-1;
1670        cdata->fmt  = (unsigned)-1;
1671        cdata->eq_sel = 0;
1672 
1673        cdata = &max98088->dai[1];
1674        cdata->rate = (unsigned)-1;
1675        cdata->fmt  = (unsigned)-1;
1676        cdata->eq_sel = 0;
1677 
1678        max98088->ina_state = 0;
1679        max98088->inb_state = 0;
1680        max98088->ex_mode = 0;
1681        max98088->digmic = 0;
1682        max98088->mic1pre = 0;
1683        max98088->mic2pre = 0;
1684 
1685        ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
1686        if (ret < 0) {
1687                dev_err(component->dev, "Failed to read device revision: %d\n",
1688                        ret);
1689                goto err_access;
1690        }
1691        dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
1692 
1693        snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1694 
1695        snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
1696 
1697        snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
1698                M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1699                M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1700 
1701        snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
1702        snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
1703 
1704        snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
1705                M98088_S1NORMAL|M98088_SDATA);
1706 
1707        snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
1708                M98088_S2NORMAL|M98088_SDATA);
1709 
1710        max98088_handle_pdata(component);
1711 
1712 err_access:
1713        return ret;
1714 }
1715 
1716 static void max98088_remove(struct snd_soc_component *component)
1717 {
1718        struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1719 
1720        kfree(max98088->eq_texts);
1721 }
1722 
1723 static const struct snd_soc_component_driver soc_component_dev_max98088 = {
1724     .probe          = max98088_probe,
1725     .remove         = max98088_remove,
1726     .set_bias_level     = max98088_set_bias_level,
1727     .controls       = max98088_snd_controls,
1728     .num_controls       = ARRAY_SIZE(max98088_snd_controls),
1729     .dapm_widgets       = max98088_dapm_widgets,
1730     .num_dapm_widgets   = ARRAY_SIZE(max98088_dapm_widgets),
1731     .dapm_routes        = max98088_audio_map,
1732     .num_dapm_routes    = ARRAY_SIZE(max98088_audio_map),
1733     .suspend_bias_off   = 1,
1734     .idle_bias_on       = 1,
1735     .use_pmdown_time    = 1,
1736     .endianness     = 1,
1737 };
1738 
1739 static const struct i2c_device_id max98088_i2c_id[] = {
1740        { "max98088", MAX98088 },
1741        { "max98089", MAX98089 },
1742        { }
1743 };
1744 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
1745 
1746 static int max98088_i2c_probe(struct i2c_client *i2c)
1747 {
1748     struct max98088_priv *max98088;
1749     int ret;
1750     const struct i2c_device_id *id;
1751 
1752     max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
1753                 GFP_KERNEL);
1754     if (max98088 == NULL)
1755         return -ENOMEM;
1756 
1757     max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
1758     if (IS_ERR(max98088->regmap))
1759         return PTR_ERR(max98088->regmap);
1760 
1761     max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
1762     if (IS_ERR(max98088->mclk))
1763         if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
1764             return PTR_ERR(max98088->mclk);
1765 
1766     id = i2c_match_id(max98088_i2c_id, i2c);
1767     max98088->devtype = id->driver_data;
1768 
1769     i2c_set_clientdata(i2c, max98088);
1770     max98088->pdata = i2c->dev.platform_data;
1771 
1772     ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_max98088,
1773                           &max98088_dai[0], 2);
1774     return ret;
1775 }
1776 
1777 #if defined(CONFIG_OF)
1778 static const struct of_device_id max98088_of_match[] = {
1779     { .compatible = "maxim,max98088" },
1780     { .compatible = "maxim,max98089" },
1781     { }
1782 };
1783 MODULE_DEVICE_TABLE(of, max98088_of_match);
1784 #endif
1785 
1786 static struct i2c_driver max98088_i2c_driver = {
1787     .driver = {
1788         .name = "max98088",
1789         .of_match_table = of_match_ptr(max98088_of_match),
1790     },
1791     .probe_new = max98088_i2c_probe,
1792     .id_table = max98088_i2c_id,
1793 };
1794 
1795 module_i2c_driver(max98088_i2c_driver);
1796 
1797 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
1798 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
1799 MODULE_LICENSE("GPL");
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