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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
0003 
0004 #include <linux/module.h>
0005 #include <linux/init.h>
0006 #include <linux/io.h>
0007 #include <linux/platform_device.h>
0008 #include <linux/clk.h>
0009 #include <linux/of_clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <sound/soc.h>
0012 #include <sound/soc-dapm.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/of_platform.h>
0015 #include <sound/tlv.h>
0016 #include "lpass-wsa-macro.h"
0017 
0018 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL   (0x0000)
0019 #define CDC_WSA_MCLK_EN_MASK            BIT(0)
0020 #define CDC_WSA_MCLK_ENABLE         BIT(0)
0021 #define CDC_WSA_MCLK_DISABLE            0
0022 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
0023 #define CDC_WSA_FS_CNT_EN_MASK          BIT(0)
0024 #define CDC_WSA_FS_CNT_ENABLE           BIT(0)
0025 #define CDC_WSA_FS_CNT_DISABLE          0
0026 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL    (0x0008)
0027 #define CDC_WSA_SWR_CLK_EN_MASK         BIT(0)
0028 #define CDC_WSA_SWR_CLK_ENABLE          BIT(0)
0029 #define CDC_WSA_SWR_RST_EN_MASK         BIT(1)
0030 #define CDC_WSA_SWR_RST_ENABLE          BIT(1)
0031 #define CDC_WSA_SWR_RST_DISABLE         0
0032 #define CDC_WSA_TOP_TOP_CFG0            (0x0080)
0033 #define CDC_WSA_TOP_TOP_CFG1            (0x0084)
0034 #define CDC_WSA_TOP_FREQ_MCLK           (0x0088)
0035 #define CDC_WSA_TOP_DEBUG_BUS_SEL       (0x008C)
0036 #define CDC_WSA_TOP_DEBUG_EN0           (0x0090)
0037 #define CDC_WSA_TOP_DEBUG_EN1           (0x0094)
0038 #define CDC_WSA_TOP_DEBUG_DSM_LB        (0x0098)
0039 #define CDC_WSA_TOP_RX_I2S_CTL          (0x009C)
0040 #define CDC_WSA_TOP_TX_I2S_CTL          (0x00A0)
0041 #define CDC_WSA_TOP_I2S_CLK         (0x00A4)
0042 #define CDC_WSA_TOP_I2S_RESET           (0x00A8)
0043 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0     (0x0100)
0044 #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0)
0045 #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3)
0046 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1     (0x0104)
0047 #define CDC_WSA_RX_INTX_2_SEL_MASK      GENMASK(2, 0)
0048 #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3)
0049 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0     (0x0108)
0050 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1     (0x010C)
0051 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0      (0x0110)
0052 #define CDC_WSA_RX_MIX_TX1_SEL_MASK     GENMASK(5, 3)
0053 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT     3
0054 #define CDC_WSA_RX_MIX_TX0_SEL_MASK     GENMASK(2, 0)
0055 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0       (0x0114)
0056 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0    (0x0118)
0057 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL      (0x0244)
0058 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK     BIT(5)
0059 #define CDC_WSA_TX_SPKR_PROT_RESET      BIT(5)
0060 #define CDC_WSA_TX_SPKR_PROT_NO_RESET       0
0061 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK    BIT(4)
0062 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE     BIT(4)
0063 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE    0
0064 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK  GENMASK(3, 0)
0065 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K    0
0066 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0     (0x0248)
0067 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL      (0x0264)
0068 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0     (0x0268)
0069 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL      (0x0284)
0070 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0     (0x0288)
0071 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL      (0x02A4)
0072 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0     (0x02A8)
0073 #define CDC_WSA_INTR_CTRL_CFG           (0x0340)
0074 #define CDC_WSA_INTR_CTRL_CLR_COMMIT        (0x0344)
0075 #define CDC_WSA_INTR_CTRL_PIN1_MASK0        (0x0360)
0076 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0      (0x0368)
0077 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0       (0x0370)
0078 #define CDC_WSA_INTR_CTRL_PIN2_MASK0        (0x0380)
0079 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0      (0x0388)
0080 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0       (0x0390)
0081 #define CDC_WSA_INTR_CTRL_LEVEL0        (0x03C0)
0082 #define CDC_WSA_INTR_CTRL_BYPASS0       (0x03C8)
0083 #define CDC_WSA_INTR_CTRL_SET0          (0x03D0)
0084 #define CDC_WSA_RX0_RX_PATH_CTL         (0x0400)
0085 #define CDC_WSA_RX_PATH_CLK_EN_MASK     BIT(5)
0086 #define CDC_WSA_RX_PATH_CLK_ENABLE      BIT(5)
0087 #define CDC_WSA_RX_PATH_CLK_DISABLE     0
0088 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK    BIT(4)
0089 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE     BIT(4)
0090 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE    0
0091 #define CDC_WSA_RX0_RX_PATH_CFG0        (0x0404)
0092 #define CDC_WSA_RX_PATH_COMP_EN_MASK        BIT(1)
0093 #define CDC_WSA_RX_PATH_COMP_ENABLE     BIT(1)
0094 #define CDC_WSA_RX_PATH_HD2_EN_MASK     BIT(2)
0095 #define CDC_WSA_RX_PATH_HD2_ENABLE      BIT(2)
0096 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK      BIT(3)
0097 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072  BIT(3)
0098 #define CDC_WSA_RX0_RX_PATH_CFG1        (0x0408)
0099 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK   BIT(0)
0100 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE    BIT(0)
0101 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE   0
0102 #define CDC_WSA_RX0_RX_PATH_CFG2        (0x040C)
0103 #define CDC_WSA_RX0_RX_PATH_CFG3        (0x0410)
0104 #define CDC_WSA_RX_DC_DCOEFF_MASK       GENMASK(1, 0)
0105 #define CDC_WSA_RX0_RX_VOL_CTL          (0x0414)
0106 #define CDC_WSA_RX0_RX_PATH_MIX_CTL     (0x0418)
0107 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK     BIT(5)
0108 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE      BIT(5)
0109 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE     0
0110 #define CDC_WSA_RX0_RX_PATH_MIX_CFG     (0x041C)
0111 #define CDC_WSA_RX0_RX_VOL_MIX_CTL      (0x0420)
0112 #define CDC_WSA_RX0_RX_PATH_SEC0        (0x0424)
0113 #define CDC_WSA_RX0_RX_PATH_SEC1        (0x0428)
0114 #define CDC_WSA_RX_PGA_HALF_DB_MASK     BIT(0)
0115 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE       BIT(0)
0116 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE      0
0117 #define CDC_WSA_RX0_RX_PATH_SEC2        (0x042C)
0118 #define CDC_WSA_RX0_RX_PATH_SEC3        (0x0430)
0119 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK      GENMASK(1, 0)
0120 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK      GENMASK(5, 2)
0121 #define CDC_WSA_RX0_RX_PATH_SEC5        (0x0438)
0122 #define CDC_WSA_RX0_RX_PATH_SEC6        (0x043C)
0123 #define CDC_WSA_RX0_RX_PATH_SEC7        (0x0440)
0124 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0        (0x0444)
0125 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1        (0x0448)
0126 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL      (0x044C)
0127 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK       BIT(0)
0128 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE        BIT(0)
0129 #define CDC_WSA_RX1_RX_PATH_CTL         (0x0480)
0130 #define CDC_WSA_RX1_RX_PATH_CFG0        (0x0484)
0131 #define CDC_WSA_RX1_RX_PATH_CFG1        (0x0488)
0132 #define CDC_WSA_RX1_RX_PATH_CFG2        (0x048C)
0133 #define CDC_WSA_RX1_RX_PATH_CFG3        (0x0490)
0134 #define CDC_WSA_RX1_RX_VOL_CTL          (0x0494)
0135 #define CDC_WSA_RX1_RX_PATH_MIX_CTL     (0x0498)
0136 #define CDC_WSA_RX1_RX_PATH_MIX_CFG     (0x049C)
0137 #define CDC_WSA_RX1_RX_VOL_MIX_CTL      (0x04A0)
0138 #define CDC_WSA_RX1_RX_PATH_SEC0        (0x04A4)
0139 #define CDC_WSA_RX1_RX_PATH_SEC1        (0x04A8)
0140 #define CDC_WSA_RX1_RX_PATH_SEC2        (0x04AC)
0141 #define CDC_WSA_RX1_RX_PATH_SEC3        (0x04B0)
0142 #define CDC_WSA_RX1_RX_PATH_SEC5        (0x04B8)
0143 #define CDC_WSA_RX1_RX_PATH_SEC6        (0x04BC)
0144 #define CDC_WSA_RX1_RX_PATH_SEC7        (0x04C0)
0145 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0        (0x04C4)
0146 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1        (0x04C8)
0147 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL      (0x04CC)
0148 #define CDC_WSA_BOOST0_BOOST_PATH_CTL       (0x0500)
0149 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK      BIT(4)
0150 #define CDC_WSA_BOOST_PATH_CLK_ENABLE       BIT(4)
0151 #define CDC_WSA_BOOST_PATH_CLK_DISABLE      0
0152 #define CDC_WSA_BOOST0_BOOST_CTL        (0x0504)
0153 #define CDC_WSA_BOOST0_BOOST_CFG1       (0x0508)
0154 #define CDC_WSA_BOOST0_BOOST_CFG2       (0x050C)
0155 #define CDC_WSA_BOOST1_BOOST_PATH_CTL       (0x0540)
0156 #define CDC_WSA_BOOST1_BOOST_CTL        (0x0544)
0157 #define CDC_WSA_BOOST1_BOOST_CFG1       (0x0548)
0158 #define CDC_WSA_BOOST1_BOOST_CFG2       (0x054C)
0159 #define CDC_WSA_COMPANDER0_CTL0         (0x0580)
0160 #define CDC_WSA_COMPANDER_CLK_EN_MASK       BIT(0)
0161 #define CDC_WSA_COMPANDER_CLK_ENABLE        BIT(0)
0162 #define CDC_WSA_COMPANDER_SOFT_RST_MASK     BIT(1)
0163 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE   BIT(1)
0164 #define CDC_WSA_COMPANDER_HALT_MASK     BIT(2)
0165 #define CDC_WSA_COMPANDER_HALT          BIT(2)
0166 #define CDC_WSA_COMPANDER0_CTL1         (0x0584)
0167 #define CDC_WSA_COMPANDER0_CTL2         (0x0588)
0168 #define CDC_WSA_COMPANDER0_CTL3         (0x058C)
0169 #define CDC_WSA_COMPANDER0_CTL4         (0x0590)
0170 #define CDC_WSA_COMPANDER0_CTL5         (0x0594)
0171 #define CDC_WSA_COMPANDER0_CTL6         (0x0598)
0172 #define CDC_WSA_COMPANDER0_CTL7         (0x059C)
0173 #define CDC_WSA_COMPANDER1_CTL0         (0x05C0)
0174 #define CDC_WSA_COMPANDER1_CTL1         (0x05C4)
0175 #define CDC_WSA_COMPANDER1_CTL2         (0x05C8)
0176 #define CDC_WSA_COMPANDER1_CTL3         (0x05CC)
0177 #define CDC_WSA_COMPANDER1_CTL4         (0x05D0)
0178 #define CDC_WSA_COMPANDER1_CTL5         (0x05D4)
0179 #define CDC_WSA_COMPANDER1_CTL6         (0x05D8)
0180 #define CDC_WSA_COMPANDER1_CTL7         (0x05DC)
0181 #define CDC_WSA_SOFTCLIP0_CRC           (0x0600)
0182 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK        BIT(0)
0183 #define CDC_WSA_SOFTCLIP_CLK_ENABLE     BIT(0)
0184 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL     (0x0604)
0185 #define CDC_WSA_SOFTCLIP_EN_MASK        BIT(0)
0186 #define CDC_WSA_SOFTCLIP_ENABLE         BIT(0)
0187 #define CDC_WSA_SOFTCLIP1_CRC           (0x0640)
0188 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL     (0x0644)
0189 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL   (0x0680)
0190 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK        BIT(0)
0191 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE     BIT(0)
0192 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0       (0x0684)
0193 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK  GENMASK(4, 1)
0194 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K   BIT(3)
0195 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL   (0x06C0)
0196 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0       (0x06C4)
0197 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL    (0x0700)
0198 #define CDC_WSA_SPLINE_ASRC0_CTL0       (0x0704)
0199 #define CDC_WSA_SPLINE_ASRC0_CTL1       (0x0708)
0200 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL       (0x070C)
0201 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB   (0x0710)
0202 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB   (0x0714)
0203 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB   (0x0718)
0204 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB   (0x071C)
0205 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO        (0x0720)
0206 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL        (0x0740)
0207 #define CDC_WSA_SPLINE_ASRC1_CTL0       (0x0744)
0208 #define CDC_WSA_SPLINE_ASRC1_CTL1       (0x0748)
0209 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL       (0x074C)
0210 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
0211 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
0212 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
0213 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
0214 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO    (0x0760)
0215 #define WSA_MAX_OFFSET              (0x0760)
0216 
0217 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0218             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
0219             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
0220 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
0221             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
0222 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0223         SNDRV_PCM_FMTBIT_S24_LE |\
0224         SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
0225 
0226 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0227             SNDRV_PCM_RATE_48000)
0228 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0229         SNDRV_PCM_FMTBIT_S24_LE |\
0230         SNDRV_PCM_FMTBIT_S24_3LE)
0231 
0232 #define NUM_INTERPOLATORS 2
0233 #define WSA_NUM_CLKS_MAX    5
0234 #define WSA_MACRO_MCLK_FREQ 19200000
0235 #define WSA_MACRO_MUX_INP_MASK2 0x38
0236 #define WSA_MACRO_MUX_CFG_OFFSET 0x8
0237 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4
0238 #define WSA_MACRO_RX_COMP_OFFSET 0x40
0239 #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40
0240 #define WSA_MACRO_RX_PATH_OFFSET 0x80
0241 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
0242 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
0243 #define WSA_MACRO_FS_RATE_MASK 0x0F
0244 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03
0245 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18
0246 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2
0247 
0248 enum {
0249     WSA_MACRO_GAIN_OFFSET_M1P5_DB,
0250     WSA_MACRO_GAIN_OFFSET_0_DB,
0251 };
0252 enum {
0253     WSA_MACRO_RX0 = 0,
0254     WSA_MACRO_RX1,
0255     WSA_MACRO_RX_MIX,
0256     WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX,
0257     WSA_MACRO_RX_MIX1,
0258     WSA_MACRO_RX_MAX,
0259 };
0260 
0261 enum {
0262     WSA_MACRO_TX0 = 0,
0263     WSA_MACRO_TX1,
0264     WSA_MACRO_TX_MAX,
0265 };
0266 
0267 enum {
0268     WSA_MACRO_EC0_MUX = 0,
0269     WSA_MACRO_EC1_MUX,
0270     WSA_MACRO_EC_MUX_MAX,
0271 };
0272 
0273 enum {
0274     WSA_MACRO_COMP1, /* SPK_L */
0275     WSA_MACRO_COMP2, /* SPK_R */
0276     WSA_MACRO_COMP_MAX
0277 };
0278 
0279 enum {
0280     WSA_MACRO_SOFTCLIP0, /* RX0 */
0281     WSA_MACRO_SOFTCLIP1, /* RX1 */
0282     WSA_MACRO_SOFTCLIP_MAX
0283 };
0284 
0285 enum {
0286     INTn_1_INP_SEL_ZERO = 0,
0287     INTn_1_INP_SEL_RX0,
0288     INTn_1_INP_SEL_RX1,
0289     INTn_1_INP_SEL_RX2,
0290     INTn_1_INP_SEL_RX3,
0291     INTn_1_INP_SEL_DEC0,
0292     INTn_1_INP_SEL_DEC1,
0293 };
0294 
0295 enum {
0296     INTn_2_INP_SEL_ZERO = 0,
0297     INTn_2_INP_SEL_RX0,
0298     INTn_2_INP_SEL_RX1,
0299     INTn_2_INP_SEL_RX2,
0300     INTn_2_INP_SEL_RX3,
0301 };
0302 
0303 struct interp_sample_rate {
0304     int sample_rate;
0305     int rate_val;
0306 };
0307 
0308 static struct interp_sample_rate int_prim_sample_rate_val[] = {
0309     {8000, 0x0},    /* 8K */
0310     {16000, 0x1},   /* 16K */
0311     {24000, -EINVAL},/* 24K */
0312     {32000, 0x3},   /* 32K */
0313     {48000, 0x4},   /* 48K */
0314     {96000, 0x5},   /* 96K */
0315     {192000, 0x6},  /* 192K */
0316     {384000, 0x7},  /* 384K */
0317     {44100, 0x8}, /* 44.1K */
0318 };
0319 
0320 static struct interp_sample_rate int_mix_sample_rate_val[] = {
0321     {48000, 0x4},   /* 48K */
0322     {96000, 0x5},   /* 96K */
0323     {192000, 0x6},  /* 192K */
0324 };
0325 
0326 enum {
0327     WSA_MACRO_AIF_INVALID = 0,
0328     WSA_MACRO_AIF1_PB,
0329     WSA_MACRO_AIF_MIX1_PB,
0330     WSA_MACRO_AIF_VI,
0331     WSA_MACRO_AIF_ECHO,
0332     WSA_MACRO_MAX_DAIS,
0333 };
0334 
0335 struct wsa_macro {
0336     struct device *dev;
0337     int comp_enabled[WSA_MACRO_COMP_MAX];
0338     int ec_hq[WSA_MACRO_RX1 + 1];
0339     u16 prim_int_users[WSA_MACRO_RX1 + 1];
0340     u16 wsa_mclk_users;
0341     bool reset_swr;
0342     unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
0343     unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
0344     int rx_port_value[WSA_MACRO_RX_MAX];
0345     int ear_spkr_gain;
0346     int spkr_gain_offset;
0347     int spkr_mode;
0348     int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
0349     int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
0350     struct regmap *regmap;
0351     struct clk *mclk;
0352     struct clk *npl;
0353     struct clk *macro;
0354     struct clk *dcodec;
0355     struct clk *fsgen;
0356     struct clk_hw hw;
0357 };
0358 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)
0359 
0360 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
0361 
0362 static const char *const rx_text[] = {
0363     "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
0364 };
0365 
0366 static const char *const rx_mix_text[] = {
0367     "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
0368 };
0369 
0370 static const char *const rx_mix_ec_text[] = {
0371     "ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
0372 };
0373 
0374 static const char *const rx_mux_text[] = {
0375     "ZERO", "AIF1_PB", "AIF_MIX1_PB"
0376 };
0377 
0378 static const char *const rx_sidetone_mix_text[] = {
0379     "ZERO", "SRC0"
0380 };
0381 
0382 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
0383     "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
0384     "G_4_DB", "G_5_DB", "G_6_DB"
0385 };
0386 
0387 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
0388                 wsa_macro_ear_spkr_pa_gain_text);
0389 
0390 /* RX INT0 */
0391 static const struct soc_enum rx0_prim_inp0_chain_enum =
0392     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
0393         0, 7, rx_text);
0394 
0395 static const struct soc_enum rx0_prim_inp1_chain_enum =
0396     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
0397         3, 7, rx_text);
0398 
0399 static const struct soc_enum rx0_prim_inp2_chain_enum =
0400     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
0401         3, 7, rx_text);
0402 
0403 static const struct soc_enum rx0_mix_chain_enum =
0404     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
0405         0, 5, rx_mix_text);
0406 
0407 static const struct soc_enum rx0_sidetone_mix_enum =
0408     SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
0409 
0410 static const struct snd_kcontrol_new rx0_prim_inp0_mux =
0411     SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
0412 
0413 static const struct snd_kcontrol_new rx0_prim_inp1_mux =
0414     SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
0415 
0416 static const struct snd_kcontrol_new rx0_prim_inp2_mux =
0417     SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
0418 
0419 static const struct snd_kcontrol_new rx0_mix_mux =
0420     SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);
0421 
0422 static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
0423     SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
0424 
0425 /* RX INT1 */
0426 static const struct soc_enum rx1_prim_inp0_chain_enum =
0427     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
0428         0, 7, rx_text);
0429 
0430 static const struct soc_enum rx1_prim_inp1_chain_enum =
0431     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
0432         3, 7, rx_text);
0433 
0434 static const struct soc_enum rx1_prim_inp2_chain_enum =
0435     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
0436         3, 7, rx_text);
0437 
0438 static const struct soc_enum rx1_mix_chain_enum =
0439     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
0440         0, 5, rx_mix_text);
0441 
0442 static const struct snd_kcontrol_new rx1_prim_inp0_mux =
0443     SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);
0444 
0445 static const struct snd_kcontrol_new rx1_prim_inp1_mux =
0446     SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);
0447 
0448 static const struct snd_kcontrol_new rx1_prim_inp2_mux =
0449     SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);
0450 
0451 static const struct snd_kcontrol_new rx1_mix_mux =
0452     SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum);
0453 
0454 static const struct soc_enum rx_mix_ec0_enum =
0455     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
0456         0, 3, rx_mix_ec_text);
0457 
0458 static const struct soc_enum rx_mix_ec1_enum =
0459     SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
0460         3, 3, rx_mix_ec_text);
0461 
0462 static const struct snd_kcontrol_new rx_mix_ec0_mux =
0463     SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
0464 
0465 static const struct snd_kcontrol_new rx_mix_ec1_mux =
0466     SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
0467 
0468 static const struct reg_default wsa_defaults[] = {
0469     /* WSA Macro */
0470     { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
0471     { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
0472     { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
0473     { CDC_WSA_TOP_TOP_CFG0, 0x00},
0474     { CDC_WSA_TOP_TOP_CFG1, 0x00},
0475     { CDC_WSA_TOP_FREQ_MCLK, 0x00},
0476     { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
0477     { CDC_WSA_TOP_DEBUG_EN0, 0x00},
0478     { CDC_WSA_TOP_DEBUG_EN1, 0x00},
0479     { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
0480     { CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
0481     { CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
0482     { CDC_WSA_TOP_I2S_CLK, 0x02},
0483     { CDC_WSA_TOP_I2S_RESET, 0x00},
0484     { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
0485     { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
0486     { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
0487     { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
0488     { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
0489     { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
0490     { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
0491     { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
0492     { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
0493     { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
0494     { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
0495     { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
0496     { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
0497     { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
0498     { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
0499     { CDC_WSA_INTR_CTRL_CFG, 0x00},
0500     { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
0501     { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
0502     { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
0503     { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
0504     { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
0505     { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
0506     { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
0507     { CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
0508     { CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
0509     { CDC_WSA_INTR_CTRL_SET0, 0x00},
0510     { CDC_WSA_RX0_RX_PATH_CTL, 0x04},
0511     { CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
0512     { CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
0513     { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
0514     { CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
0515     { CDC_WSA_RX0_RX_VOL_CTL, 0x00},
0516     { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
0517     { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
0518     { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
0519     { CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
0520     { CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
0521     { CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
0522     { CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
0523     { CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
0524     { CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
0525     { CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
0526     { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
0527     { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
0528     { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
0529     { CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
0530     { CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
0531     { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
0532     { CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
0533     { CDC_WSA_RX1_RX_VOL_CTL, 0x00},
0534     { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
0535     { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
0536     { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
0537     { CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
0538     { CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
0539     { CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
0540     { CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
0541     { CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
0542     { CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
0543     { CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
0544     { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
0545     { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
0546     { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
0547     { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
0548     { CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
0549     { CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
0550     { CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
0551     { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
0552     { CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
0553     { CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
0554     { CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
0555     { CDC_WSA_COMPANDER0_CTL0, 0x60},
0556     { CDC_WSA_COMPANDER0_CTL1, 0xDB},
0557     { CDC_WSA_COMPANDER0_CTL2, 0xFF},
0558     { CDC_WSA_COMPANDER0_CTL3, 0x35},
0559     { CDC_WSA_COMPANDER0_CTL4, 0xFF},
0560     { CDC_WSA_COMPANDER0_CTL5, 0x00},
0561     { CDC_WSA_COMPANDER0_CTL6, 0x01},
0562     { CDC_WSA_COMPANDER0_CTL7, 0x28},
0563     { CDC_WSA_COMPANDER1_CTL0, 0x60},
0564     { CDC_WSA_COMPANDER1_CTL1, 0xDB},
0565     { CDC_WSA_COMPANDER1_CTL2, 0xFF},
0566     { CDC_WSA_COMPANDER1_CTL3, 0x35},
0567     { CDC_WSA_COMPANDER1_CTL4, 0xFF},
0568     { CDC_WSA_COMPANDER1_CTL5, 0x00},
0569     { CDC_WSA_COMPANDER1_CTL6, 0x01},
0570     { CDC_WSA_COMPANDER1_CTL7, 0x28},
0571     { CDC_WSA_SOFTCLIP0_CRC, 0x00},
0572     { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
0573     { CDC_WSA_SOFTCLIP1_CRC, 0x00},
0574     { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
0575     { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
0576     { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
0577     { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
0578     { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
0579     { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
0580     { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
0581     { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
0582     { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
0583     { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
0584     { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
0585     { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
0586     { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
0587     { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
0588     { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
0589     { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
0590     { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
0591     { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
0592     { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
0593     { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
0594     { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
0595     { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
0596     { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
0597 };
0598 
0599 static bool wsa_is_wronly_register(struct device *dev,
0600                     unsigned int reg)
0601 {
0602     switch (reg) {
0603     case CDC_WSA_INTR_CTRL_CLR_COMMIT:
0604     case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
0605     case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
0606         return true;
0607     }
0608 
0609     return false;
0610 }
0611 
0612 static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
0613 {
0614     switch (reg) {
0615     case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
0616     case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
0617     case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
0618     case CDC_WSA_TOP_TOP_CFG0:
0619     case CDC_WSA_TOP_TOP_CFG1:
0620     case CDC_WSA_TOP_FREQ_MCLK:
0621     case CDC_WSA_TOP_DEBUG_BUS_SEL:
0622     case CDC_WSA_TOP_DEBUG_EN0:
0623     case CDC_WSA_TOP_DEBUG_EN1:
0624     case CDC_WSA_TOP_DEBUG_DSM_LB:
0625     case CDC_WSA_TOP_RX_I2S_CTL:
0626     case CDC_WSA_TOP_TX_I2S_CTL:
0627     case CDC_WSA_TOP_I2S_CLK:
0628     case CDC_WSA_TOP_I2S_RESET:
0629     case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
0630     case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
0631     case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
0632     case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
0633     case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
0634     case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
0635     case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
0636     case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
0637     case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
0638     case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
0639     case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
0640     case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
0641     case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
0642     case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
0643     case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
0644     case CDC_WSA_INTR_CTRL_CFG:
0645     case CDC_WSA_INTR_CTRL_PIN1_MASK0:
0646     case CDC_WSA_INTR_CTRL_PIN2_MASK0:
0647     case CDC_WSA_INTR_CTRL_LEVEL0:
0648     case CDC_WSA_INTR_CTRL_BYPASS0:
0649     case CDC_WSA_INTR_CTRL_SET0:
0650     case CDC_WSA_RX0_RX_PATH_CTL:
0651     case CDC_WSA_RX0_RX_PATH_CFG0:
0652     case CDC_WSA_RX0_RX_PATH_CFG1:
0653     case CDC_WSA_RX0_RX_PATH_CFG2:
0654     case CDC_WSA_RX0_RX_PATH_CFG3:
0655     case CDC_WSA_RX0_RX_VOL_CTL:
0656     case CDC_WSA_RX0_RX_PATH_MIX_CTL:
0657     case CDC_WSA_RX0_RX_PATH_MIX_CFG:
0658     case CDC_WSA_RX0_RX_VOL_MIX_CTL:
0659     case CDC_WSA_RX0_RX_PATH_SEC0:
0660     case CDC_WSA_RX0_RX_PATH_SEC1:
0661     case CDC_WSA_RX0_RX_PATH_SEC2:
0662     case CDC_WSA_RX0_RX_PATH_SEC3:
0663     case CDC_WSA_RX0_RX_PATH_SEC5:
0664     case CDC_WSA_RX0_RX_PATH_SEC6:
0665     case CDC_WSA_RX0_RX_PATH_SEC7:
0666     case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
0667     case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
0668     case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
0669     case CDC_WSA_RX1_RX_PATH_CTL:
0670     case CDC_WSA_RX1_RX_PATH_CFG0:
0671     case CDC_WSA_RX1_RX_PATH_CFG1:
0672     case CDC_WSA_RX1_RX_PATH_CFG2:
0673     case CDC_WSA_RX1_RX_PATH_CFG3:
0674     case CDC_WSA_RX1_RX_VOL_CTL:
0675     case CDC_WSA_RX1_RX_PATH_MIX_CTL:
0676     case CDC_WSA_RX1_RX_PATH_MIX_CFG:
0677     case CDC_WSA_RX1_RX_VOL_MIX_CTL:
0678     case CDC_WSA_RX1_RX_PATH_SEC0:
0679     case CDC_WSA_RX1_RX_PATH_SEC1:
0680     case CDC_WSA_RX1_RX_PATH_SEC2:
0681     case CDC_WSA_RX1_RX_PATH_SEC3:
0682     case CDC_WSA_RX1_RX_PATH_SEC5:
0683     case CDC_WSA_RX1_RX_PATH_SEC6:
0684     case CDC_WSA_RX1_RX_PATH_SEC7:
0685     case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
0686     case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
0687     case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
0688     case CDC_WSA_BOOST0_BOOST_PATH_CTL:
0689     case CDC_WSA_BOOST0_BOOST_CTL:
0690     case CDC_WSA_BOOST0_BOOST_CFG1:
0691     case CDC_WSA_BOOST0_BOOST_CFG2:
0692     case CDC_WSA_BOOST1_BOOST_PATH_CTL:
0693     case CDC_WSA_BOOST1_BOOST_CTL:
0694     case CDC_WSA_BOOST1_BOOST_CFG1:
0695     case CDC_WSA_BOOST1_BOOST_CFG2:
0696     case CDC_WSA_COMPANDER0_CTL0:
0697     case CDC_WSA_COMPANDER0_CTL1:
0698     case CDC_WSA_COMPANDER0_CTL2:
0699     case CDC_WSA_COMPANDER0_CTL3:
0700     case CDC_WSA_COMPANDER0_CTL4:
0701     case CDC_WSA_COMPANDER0_CTL5:
0702     case CDC_WSA_COMPANDER0_CTL7:
0703     case CDC_WSA_COMPANDER1_CTL0:
0704     case CDC_WSA_COMPANDER1_CTL1:
0705     case CDC_WSA_COMPANDER1_CTL2:
0706     case CDC_WSA_COMPANDER1_CTL3:
0707     case CDC_WSA_COMPANDER1_CTL4:
0708     case CDC_WSA_COMPANDER1_CTL5:
0709     case CDC_WSA_COMPANDER1_CTL7:
0710     case CDC_WSA_SOFTCLIP0_CRC:
0711     case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
0712     case CDC_WSA_SOFTCLIP1_CRC:
0713     case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
0714     case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
0715     case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
0716     case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
0717     case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
0718     case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
0719     case CDC_WSA_SPLINE_ASRC0_CTL0:
0720     case CDC_WSA_SPLINE_ASRC0_CTL1:
0721     case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
0722     case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
0723     case CDC_WSA_SPLINE_ASRC1_CTL0:
0724     case CDC_WSA_SPLINE_ASRC1_CTL1:
0725     case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
0726         return true;
0727     }
0728 
0729     return false;
0730 }
0731 
0732 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
0733 {
0734     bool ret;
0735 
0736     ret = wsa_is_rw_register(dev, reg);
0737     if (!ret)
0738         return wsa_is_wronly_register(dev, reg);
0739 
0740     return ret;
0741 }
0742 
0743 static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
0744 {
0745     switch (reg) {
0746     case CDC_WSA_INTR_CTRL_CLR_COMMIT:
0747     case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
0748     case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
0749     case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
0750     case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
0751     case CDC_WSA_COMPANDER0_CTL6:
0752     case CDC_WSA_COMPANDER1_CTL6:
0753     case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
0754     case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
0755     case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
0756     case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
0757     case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
0758     case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
0759     case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
0760     case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
0761     case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
0762     case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
0763         return true;
0764     }
0765 
0766     return wsa_is_rw_register(dev, reg);
0767 }
0768 
0769 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
0770 {
0771     /* Update volatile list for rx/tx macros */
0772     switch (reg) {
0773     case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
0774     case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
0775     case CDC_WSA_COMPANDER0_CTL6:
0776     case CDC_WSA_COMPANDER1_CTL6:
0777     case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
0778     case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
0779     case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
0780     case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
0781     case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
0782     case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
0783     case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
0784     case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
0785     case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
0786     case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
0787         return true;
0788     }
0789     return false;
0790 }
0791 
0792 static const struct regmap_config wsa_regmap_config = {
0793     .name = "wsa_macro",
0794     .reg_bits = 16,
0795     .val_bits = 32, /* 8 but with 32 bit read/write */
0796     .reg_stride = 4,
0797     .cache_type = REGCACHE_FLAT,
0798     .reg_defaults = wsa_defaults,
0799     .num_reg_defaults = ARRAY_SIZE(wsa_defaults),
0800     .max_register = WSA_MAX_OFFSET,
0801     .writeable_reg = wsa_is_writeable_register,
0802     .volatile_reg = wsa_is_volatile_register,
0803     .readable_reg = wsa_is_readable_register,
0804 };
0805 
0806 /**
0807  * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
0808  * settings based on speaker mode.
0809  *
0810  * @component: codec instance
0811  * @mode: Indicates speaker configuration mode.
0812  *
0813  * Returns 0 on success or -EINVAL on error.
0814  */
0815 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
0816 {
0817     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
0818 
0819     wsa->spkr_mode = mode;
0820 
0821     switch (mode) {
0822     case WSA_MACRO_SPKR_MODE_1:
0823         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
0824         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
0825         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
0826         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
0827         snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
0828         snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
0829         break;
0830     default:
0831         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
0832         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
0833         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
0834         snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
0835         snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
0836         snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
0837         break;
0838     }
0839     return 0;
0840 }
0841 EXPORT_SYMBOL(wsa_macro_set_spkr_mode);
0842 
0843 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
0844                         u8 int_prim_fs_rate_reg_val,
0845                         u32 sample_rate)
0846 {
0847     u8 int_1_mix1_inp;
0848     u32 j, port;
0849     u16 int_mux_cfg0, int_mux_cfg1;
0850     u16 int_fs_reg;
0851     u8 inp0_sel, inp1_sel, inp2_sel;
0852     struct snd_soc_component *component = dai->component;
0853     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
0854 
0855     for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
0856         int_1_mix1_inp = port;
0857         if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) {
0858             dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n",
0859                 __func__, dai->id);
0860             return -EINVAL;
0861         }
0862 
0863         int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;
0864 
0865         /*
0866          * Loop through all interpolator MUX inputs and find out
0867          * to which interpolator input, the cdc_dma rx port
0868          * is connected
0869          */
0870         for (j = 0; j < NUM_INTERPOLATORS; j++) {
0871             int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
0872             inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 
0873                                 CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
0874             inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 
0875                                 CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
0876             inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
0877                                 CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
0878 
0879             if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
0880                 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
0881                 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
0882                 int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
0883                          WSA_MACRO_RX_PATH_OFFSET * j;
0884                 /* sample_rate is in Hz */
0885                 snd_soc_component_update_bits(component, int_fs_reg,
0886                                   WSA_MACRO_FS_RATE_MASK,
0887                                   int_prim_fs_rate_reg_val);
0888             }
0889             int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
0890         }
0891     }
0892 
0893     return 0;
0894 }
0895 
0896 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
0897                            u8 int_mix_fs_rate_reg_val,
0898                            u32 sample_rate)
0899 {
0900     u8 int_2_inp;
0901     u32 j, port;
0902     u16 int_mux_cfg1, int_fs_reg;
0903     u8 int_mux_cfg1_val;
0904     struct snd_soc_component *component = dai->component;
0905     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
0906 
0907     for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
0908         int_2_inp = port;
0909         if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) {
0910             dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n",
0911                 __func__, dai->id);
0912             return -EINVAL;
0913         }
0914 
0915         int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
0916         for (j = 0; j < NUM_INTERPOLATORS; j++) {
0917             int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
0918                                     CDC_WSA_RX_INTX_2_SEL_MASK);
0919 
0920             if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
0921                 int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
0922                     WSA_MACRO_RX_PATH_OFFSET * j;
0923 
0924                 snd_soc_component_update_bits(component,
0925                               int_fs_reg,
0926                               WSA_MACRO_FS_RATE_MASK,
0927                               int_mix_fs_rate_reg_val);
0928             }
0929             int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
0930         }
0931     }
0932     return 0;
0933 }
0934 
0935 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
0936                        u32 sample_rate)
0937 {
0938     int rate_val = 0;
0939     int i, ret;
0940 
0941     /* set mixing path rate */
0942     for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
0943         if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
0944             rate_val = int_mix_sample_rate_val[i].rate_val;
0945             break;
0946         }
0947     }
0948     if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
0949         goto prim_rate;
0950 
0951     ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
0952     if (ret < 0)
0953         return ret;
0954 prim_rate:
0955     /* set primary path sample rate */
0956     for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
0957         if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
0958             rate_val = int_prim_sample_rate_val[i].rate_val;
0959             break;
0960         }
0961     }
0962     if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
0963         return -EINVAL;
0964 
0965     ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);
0966 
0967     return ret;
0968 }
0969 
0970 static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
0971                    struct snd_pcm_hw_params *params,
0972                    struct snd_soc_dai *dai)
0973 {
0974     struct snd_soc_component *component = dai->component;
0975     int ret;
0976 
0977     switch (substream->stream) {
0978     case SNDRV_PCM_STREAM_PLAYBACK:
0979         ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
0980         if (ret) {
0981             dev_err(component->dev,
0982                 "%s: cannot set sample rate: %u\n",
0983                 __func__, params_rate(params));
0984             return ret;
0985         }
0986         break;
0987     default:
0988         break;
0989     }
0990     return 0;
0991 }
0992 
0993 static int wsa_macro_get_channel_map(struct snd_soc_dai *dai,
0994                      unsigned int *tx_num, unsigned int *tx_slot,
0995                      unsigned int *rx_num, unsigned int *rx_slot)
0996 {
0997     struct snd_soc_component *component = dai->component;
0998     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
0999     u16 val, mask = 0, cnt = 0, temp;
1000 
1001     switch (dai->id) {
1002     case WSA_MACRO_AIF_VI:
1003         *tx_slot = wsa->active_ch_mask[dai->id];
1004         *tx_num = wsa->active_ch_cnt[dai->id];
1005         break;
1006     case WSA_MACRO_AIF1_PB:
1007     case WSA_MACRO_AIF_MIX1_PB:
1008         for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
1009                     WSA_MACRO_RX_MAX) {
1010             mask |= (1 << temp);
1011             if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
1012                 break;
1013         }
1014         if (mask & 0x0C)
1015             mask = mask >> 0x2;
1016         *rx_slot = mask;
1017         *rx_num = cnt;
1018         break;
1019     case WSA_MACRO_AIF_ECHO:
1020         val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1021         if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
1022             mask |= 0x2;
1023             cnt++;
1024         }
1025         if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
1026             mask |= 0x1;
1027             cnt++;
1028         }
1029         *tx_slot = mask;
1030         *tx_num = cnt;
1031         break;
1032     default:
1033         dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1034         break;
1035     }
1036     return 0;
1037 }
1038 
1039 static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
1040     .hw_params = wsa_macro_hw_params,
1041     .get_channel_map = wsa_macro_get_channel_map,
1042 };
1043 
1044 static struct snd_soc_dai_driver wsa_macro_dai[] = {
1045     {
1046         .name = "wsa_macro_rx1",
1047         .id = WSA_MACRO_AIF1_PB,
1048         .playback = {
1049             .stream_name = "WSA_AIF1 Playback",
1050             .rates = WSA_MACRO_RX_RATES,
1051             .formats = WSA_MACRO_RX_FORMATS,
1052             .rate_max = 384000,
1053             .rate_min = 8000,
1054             .channels_min = 1,
1055             .channels_max = 2,
1056         },
1057         .ops = &wsa_macro_dai_ops,
1058     },
1059     {
1060         .name = "wsa_macro_rx_mix",
1061         .id = WSA_MACRO_AIF_MIX1_PB,
1062         .playback = {
1063             .stream_name = "WSA_AIF_MIX1 Playback",
1064             .rates = WSA_MACRO_RX_MIX_RATES,
1065             .formats = WSA_MACRO_RX_FORMATS,
1066             .rate_max = 192000,
1067             .rate_min = 48000,
1068             .channels_min = 1,
1069             .channels_max = 2,
1070         },
1071         .ops = &wsa_macro_dai_ops,
1072     },
1073     {
1074         .name = "wsa_macro_vifeedback",
1075         .id = WSA_MACRO_AIF_VI,
1076         .capture = {
1077             .stream_name = "WSA_AIF_VI Capture",
1078             .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
1079             .formats = WSA_MACRO_RX_FORMATS,
1080             .rate_max = 48000,
1081             .rate_min = 8000,
1082             .channels_min = 1,
1083             .channels_max = 4,
1084         },
1085         .ops = &wsa_macro_dai_ops,
1086     },
1087     {
1088         .name = "wsa_macro_echo",
1089         .id = WSA_MACRO_AIF_ECHO,
1090         .capture = {
1091             .stream_name = "WSA_AIF_ECHO Capture",
1092             .rates = WSA_MACRO_ECHO_RATES,
1093             .formats = WSA_MACRO_ECHO_FORMATS,
1094             .rate_max = 48000,
1095             .rate_min = 8000,
1096             .channels_min = 1,
1097             .channels_max = 2,
1098         },
1099         .ops = &wsa_macro_dai_ops,
1100     },
1101 };
1102 
1103 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
1104 {
1105     struct regmap *regmap = wsa->regmap;
1106 
1107     if (mclk_enable) {
1108         if (wsa->wsa_mclk_users == 0) {
1109             regcache_mark_dirty(regmap);
1110             regcache_sync(regmap);
1111             /* 9.6MHz MCLK, set value 0x00 if other frequency */
1112             regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
1113             regmap_update_bits(regmap,
1114                        CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1115                        CDC_WSA_MCLK_EN_MASK,
1116                        CDC_WSA_MCLK_ENABLE);
1117             regmap_update_bits(regmap,
1118                        CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1119                        CDC_WSA_FS_CNT_EN_MASK,
1120                        CDC_WSA_FS_CNT_ENABLE);
1121         }
1122         wsa->wsa_mclk_users++;
1123     } else {
1124         if (wsa->wsa_mclk_users <= 0) {
1125             dev_err(wsa->dev, "clock already disabled\n");
1126             wsa->wsa_mclk_users = 0;
1127             return;
1128         }
1129         wsa->wsa_mclk_users--;
1130         if (wsa->wsa_mclk_users == 0) {
1131             regmap_update_bits(regmap,
1132                        CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1133                        CDC_WSA_FS_CNT_EN_MASK,
1134                        CDC_WSA_FS_CNT_DISABLE);
1135             regmap_update_bits(regmap,
1136                        CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1137                        CDC_WSA_MCLK_EN_MASK,
1138                        CDC_WSA_MCLK_DISABLE);
1139         }
1140     }
1141 }
1142 
1143 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
1144                 struct snd_kcontrol *kcontrol, int event)
1145 {
1146     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1147     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1148 
1149     wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
1150     return 0;
1151 }
1152 
1153 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
1154                     struct snd_kcontrol *kcontrol,
1155                     int event)
1156 {
1157     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1158     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1159     u32 tx_reg0, tx_reg1;
1160 
1161     if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1162         tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
1163         tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
1164     } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1165         tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
1166         tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
1167     }
1168 
1169     switch (event) {
1170     case SND_SOC_DAPM_POST_PMU:
1171             /* Enable V&I sensing */
1172         snd_soc_component_update_bits(component, tx_reg0,
1173                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1174                           CDC_WSA_TX_SPKR_PROT_RESET);
1175         snd_soc_component_update_bits(component, tx_reg1,
1176                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1177                           CDC_WSA_TX_SPKR_PROT_RESET);
1178         snd_soc_component_update_bits(component, tx_reg0,
1179                           CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1180                           CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1181         snd_soc_component_update_bits(component, tx_reg1,
1182                           CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1183                           CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1184         snd_soc_component_update_bits(component, tx_reg0,
1185                           CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1186                           CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1187         snd_soc_component_update_bits(component, tx_reg1,
1188                           CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1189                           CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1190         snd_soc_component_update_bits(component, tx_reg0,
1191                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1192                           CDC_WSA_TX_SPKR_PROT_NO_RESET);
1193         snd_soc_component_update_bits(component, tx_reg1,
1194                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1195                           CDC_WSA_TX_SPKR_PROT_NO_RESET);
1196         break;
1197     case SND_SOC_DAPM_POST_PMD:
1198         /* Disable V&I sensing */
1199         snd_soc_component_update_bits(component, tx_reg0,
1200                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1201                           CDC_WSA_TX_SPKR_PROT_RESET);
1202         snd_soc_component_update_bits(component, tx_reg1,
1203                           CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1204                           CDC_WSA_TX_SPKR_PROT_RESET);
1205         snd_soc_component_update_bits(component, tx_reg0,
1206                           CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1207                           CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1208         snd_soc_component_update_bits(component, tx_reg1,
1209                           CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1210                           CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1211         break;
1212     }
1213 
1214     return 0;
1215 }
1216 
1217 static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
1218                      struct snd_kcontrol *kcontrol, int event)
1219 {
1220     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1221     u16 path_reg, gain_reg;
1222     int val;
1223 
1224     switch (w->shift) {
1225     case WSA_MACRO_RX_MIX0:
1226         path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1227         gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
1228         break;
1229     case WSA_MACRO_RX_MIX1:
1230         path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1231         gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
1232         break;
1233     default:
1234         return 0;
1235     }
1236 
1237     switch (event) {
1238     case SND_SOC_DAPM_POST_PMU:
1239         val = snd_soc_component_read(component, gain_reg);
1240         snd_soc_component_write(component, gain_reg, val);
1241         break;
1242     case SND_SOC_DAPM_POST_PMD:
1243         snd_soc_component_update_bits(component, path_reg,
1244                           CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
1245                           CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
1246         break;
1247     }
1248 
1249     return 0;
1250 }
1251 
1252 static void wsa_macro_hd2_control(struct snd_soc_component *component,
1253                   u16 reg, int event)
1254 {
1255     u16 hd2_scale_reg;
1256     u16 hd2_enable_reg;
1257 
1258     if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
1259         hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
1260         hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
1261     }
1262     if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
1263         hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
1264         hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
1265     }
1266 
1267     if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
1268         snd_soc_component_update_bits(component, hd2_scale_reg,
1269                           CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1270                           0x10);
1271         snd_soc_component_update_bits(component, hd2_scale_reg,
1272                           CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1273                           0x1);
1274         snd_soc_component_update_bits(component, hd2_enable_reg,
1275                           CDC_WSA_RX_PATH_HD2_EN_MASK,
1276                           CDC_WSA_RX_PATH_HD2_ENABLE);
1277     }
1278 
1279     if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
1280         snd_soc_component_update_bits(component, hd2_enable_reg,
1281                           CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
1282         snd_soc_component_update_bits(component, hd2_scale_reg,
1283                           CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1284                           0);
1285         snd_soc_component_update_bits(component, hd2_scale_reg,
1286                           CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1287                           0);
1288     }
1289 }
1290 
1291 static int wsa_macro_config_compander(struct snd_soc_component *component,
1292                       int comp, int event)
1293 {
1294     u16 comp_ctl0_reg, rx_path_cfg0_reg;
1295     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1296 
1297     if (!wsa->comp_enabled[comp])
1298         return 0;
1299 
1300     comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
1301                     (comp * WSA_MACRO_RX_COMP_OFFSET);
1302     rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
1303                     (comp * WSA_MACRO_RX_PATH_OFFSET);
1304 
1305     if (SND_SOC_DAPM_EVENT_ON(event)) {
1306         /* Enable Compander Clock */
1307         snd_soc_component_update_bits(component, comp_ctl0_reg,
1308                           CDC_WSA_COMPANDER_CLK_EN_MASK,
1309                           CDC_WSA_COMPANDER_CLK_ENABLE);
1310         snd_soc_component_update_bits(component, comp_ctl0_reg,
1311                           CDC_WSA_COMPANDER_SOFT_RST_MASK,
1312                           CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1313         snd_soc_component_update_bits(component, comp_ctl0_reg,
1314                           CDC_WSA_COMPANDER_SOFT_RST_MASK,
1315                           0);
1316         snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1317                           CDC_WSA_RX_PATH_COMP_EN_MASK,
1318                           CDC_WSA_RX_PATH_COMP_ENABLE);
1319     }
1320 
1321     if (SND_SOC_DAPM_EVENT_OFF(event)) {
1322         snd_soc_component_update_bits(component, comp_ctl0_reg,
1323                           CDC_WSA_COMPANDER_HALT_MASK,
1324                           CDC_WSA_COMPANDER_HALT);
1325         snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1326                           CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
1327         snd_soc_component_update_bits(component, comp_ctl0_reg,
1328                           CDC_WSA_COMPANDER_SOFT_RST_MASK,
1329                           CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1330         snd_soc_component_update_bits(component, comp_ctl0_reg,
1331                           CDC_WSA_COMPANDER_SOFT_RST_MASK,
1332                           0);
1333         snd_soc_component_update_bits(component, comp_ctl0_reg,
1334                           CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
1335         snd_soc_component_update_bits(component, comp_ctl0_reg,
1336                           CDC_WSA_COMPANDER_HALT_MASK, 0);
1337     }
1338 
1339     return 0;
1340 }
1341 
1342 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
1343                      struct wsa_macro *wsa,
1344                      int path,
1345                      bool enable)
1346 {
1347     u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC +
1348             (path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
1349     u8 softclip_mux_mask = (1 << path);
1350     u8 softclip_mux_value = (1 << path);
1351 
1352     if (enable) {
1353         if (wsa->softclip_clk_users[path] == 0) {
1354             snd_soc_component_update_bits(component,
1355                         softclip_clk_reg,
1356                         CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1357                         CDC_WSA_SOFTCLIP_CLK_ENABLE);
1358             snd_soc_component_update_bits(component,
1359                 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1360                 softclip_mux_mask, softclip_mux_value);
1361         }
1362         wsa->softclip_clk_users[path]++;
1363     } else {
1364         wsa->softclip_clk_users[path]--;
1365         if (wsa->softclip_clk_users[path] == 0) {
1366             snd_soc_component_update_bits(component,
1367                         softclip_clk_reg,
1368                         CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1369                         0);
1370             snd_soc_component_update_bits(component,
1371                 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1372                 softclip_mux_mask, 0x00);
1373         }
1374     }
1375 }
1376 
1377 static int wsa_macro_config_softclip(struct snd_soc_component *component,
1378                      int path, int event)
1379 {
1380     u16 softclip_ctrl_reg;
1381     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1382     int softclip_path = 0;
1383 
1384     if (path == WSA_MACRO_COMP1)
1385         softclip_path = WSA_MACRO_SOFTCLIP0;
1386     else if (path == WSA_MACRO_COMP2)
1387         softclip_path = WSA_MACRO_SOFTCLIP1;
1388 
1389     if (!wsa->is_softclip_on[softclip_path])
1390         return 0;
1391 
1392     softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
1393                 (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
1394 
1395     if (SND_SOC_DAPM_EVENT_ON(event)) {
1396         /* Enable Softclip clock and mux */
1397         wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1398                           true);
1399         /* Enable Softclip control */
1400         snd_soc_component_update_bits(component, softclip_ctrl_reg,
1401                           CDC_WSA_SOFTCLIP_EN_MASK,
1402                           CDC_WSA_SOFTCLIP_ENABLE);
1403     }
1404 
1405     if (SND_SOC_DAPM_EVENT_OFF(event)) {
1406         snd_soc_component_update_bits(component, softclip_ctrl_reg,
1407                           CDC_WSA_SOFTCLIP_EN_MASK, 0);
1408         wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1409                           false);
1410     }
1411 
1412     return 0;
1413 }
1414 
1415 static bool wsa_macro_adie_lb(struct snd_soc_component *component,
1416                   int interp_idx)
1417 {
1418     u16 int_mux_cfg0,  int_mux_cfg1;
1419     u8 int_n_inp0, int_n_inp1, int_n_inp2;
1420 
1421     int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1422     int_mux_cfg1 = int_mux_cfg0 + 4;
1423 
1424     int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1425                           CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
1426     if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1427         int_n_inp0 == INTn_1_INP_SEL_DEC1)
1428         return true;
1429 
1430     int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1431                           CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
1432     if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1433         int_n_inp1 == INTn_1_INP_SEL_DEC1)
1434         return true;
1435 
1436     int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1437                           CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
1438     if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1439         int_n_inp2 == INTn_1_INP_SEL_DEC1)
1440         return true;
1441 
1442     return false;
1443 }
1444 
1445 static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1446                       struct snd_kcontrol *kcontrol,
1447                       int event)
1448 {
1449     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1450     u16 reg;
1451 
1452     reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift;
1453     switch (event) {
1454     case SND_SOC_DAPM_PRE_PMU:
1455         if (wsa_macro_adie_lb(component, w->shift)) {
1456             snd_soc_component_update_bits(component, reg,
1457                          CDC_WSA_RX_PATH_CLK_EN_MASK,
1458                          CDC_WSA_RX_PATH_CLK_ENABLE);
1459         }
1460         break;
1461     default:
1462         break;
1463     }
1464     return 0;
1465 }
1466 
1467 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
1468 {
1469     u16 prim_int_reg = 0;
1470 
1471     switch (reg) {
1472     case CDC_WSA_RX0_RX_PATH_CTL:
1473     case CDC_WSA_RX0_RX_PATH_MIX_CTL:
1474         prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
1475         *ind = 0;
1476         break;
1477     case CDC_WSA_RX1_RX_PATH_CTL:
1478     case CDC_WSA_RX1_RX_PATH_MIX_CTL:
1479         prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
1480         *ind = 1;
1481         break;
1482     }
1483 
1484     return prim_int_reg;
1485 }
1486 
1487 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
1488                           u16 reg, int event)
1489 {
1490     u16 prim_int_reg;
1491     u16 ind = 0;
1492     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1493 
1494     prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);
1495 
1496     switch (event) {
1497     case SND_SOC_DAPM_PRE_PMU:
1498         wsa->prim_int_users[ind]++;
1499         if (wsa->prim_int_users[ind] == 1) {
1500             snd_soc_component_update_bits(component,
1501                               prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
1502                               CDC_WSA_RX_DC_DCOEFF_MASK,
1503                               0x3);
1504             snd_soc_component_update_bits(component, prim_int_reg,
1505                     CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
1506                     CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
1507             wsa_macro_hd2_control(component, prim_int_reg, event);
1508             snd_soc_component_update_bits(component,
1509                 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1510                 CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
1511                 CDC_WSA_RX_DSMDEM_CLK_ENABLE);
1512         }
1513         if ((reg != prim_int_reg) &&
1514             ((snd_soc_component_read(
1515                 component, prim_int_reg)) & 0x10))
1516             snd_soc_component_update_bits(component, reg,
1517                     0x10, 0x10);
1518         break;
1519     case SND_SOC_DAPM_POST_PMD:
1520         wsa->prim_int_users[ind]--;
1521         if (wsa->prim_int_users[ind] == 0) {
1522             snd_soc_component_update_bits(component,
1523                 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1524                 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
1525             wsa_macro_hd2_control(component, prim_int_reg, event);
1526         }
1527         break;
1528     }
1529 
1530     return 0;
1531 }
1532 
1533 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
1534                       struct wsa_macro *wsa,
1535                       int event, int gain_reg)
1536 {
1537     int comp_gain_offset, val;
1538 
1539     switch (wsa->spkr_mode) {
1540     /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
1541     case WSA_MACRO_SPKR_MODE_1:
1542         comp_gain_offset = -12;
1543         break;
1544     /* Default case compander gain is 15 dB */
1545     default:
1546         comp_gain_offset = -15;
1547         break;
1548     }
1549 
1550     switch (event) {
1551     case SND_SOC_DAPM_POST_PMU:
1552         /* Apply ear spkr gain only if compander is enabled */
1553         if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1554             (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1555             (wsa->ear_spkr_gain != 0)) {
1556             /* For example, val is -8(-12+5-1) for 4dB of gain */
1557             val = comp_gain_offset + wsa->ear_spkr_gain - 1;
1558             snd_soc_component_write(component, gain_reg, val);
1559         }
1560         break;
1561     case SND_SOC_DAPM_POST_PMD:
1562         /*
1563          * Reset RX0 volume to 0 dB if compander is enabled and
1564          * ear_spkr_gain is non-zero.
1565          */
1566         if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1567             (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1568             (wsa->ear_spkr_gain != 0)) {
1569             snd_soc_component_write(component, gain_reg, 0x0);
1570         }
1571         break;
1572     }
1573 
1574     return 0;
1575 }
1576 
1577 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
1578                      struct snd_kcontrol *kcontrol,
1579                      int event)
1580 {
1581     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1582     u16 gain_reg;
1583     u16 reg;
1584     int val;
1585     int offset_val = 0;
1586     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1587 
1588     if (w->shift == WSA_MACRO_COMP1) {
1589         reg = CDC_WSA_RX0_RX_PATH_CTL;
1590         gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
1591     } else if (w->shift == WSA_MACRO_COMP2) {
1592         reg = CDC_WSA_RX1_RX_PATH_CTL;
1593         gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
1594     }
1595 
1596     switch (event) {
1597     case SND_SOC_DAPM_PRE_PMU:
1598         /* Reset if needed */
1599         wsa_macro_enable_prim_interpolator(component, reg, event);
1600         break;
1601     case SND_SOC_DAPM_POST_PMU:
1602         wsa_macro_config_compander(component, w->shift, event);
1603         wsa_macro_config_softclip(component, w->shift, event);
1604         /* apply gain after int clk is enabled */
1605         if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1606             (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1607              wsa->comp_enabled[WSA_MACRO_COMP2])) {
1608             snd_soc_component_update_bits(component,
1609                     CDC_WSA_RX0_RX_PATH_SEC1,
1610                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1611                     CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1612             snd_soc_component_update_bits(component,
1613                     CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1614                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1615                     CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1616             snd_soc_component_update_bits(component,
1617                     CDC_WSA_RX1_RX_PATH_SEC1,
1618                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1619                     CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1620             snd_soc_component_update_bits(component,
1621                     CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1622                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1623                     CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1624             offset_val = -2;
1625         }
1626         val = snd_soc_component_read(component, gain_reg);
1627         val += offset_val;
1628         snd_soc_component_write(component, gain_reg, val);
1629         wsa_macro_config_ear_spkr_gain(component, wsa,
1630                         event, gain_reg);
1631         break;
1632     case SND_SOC_DAPM_POST_PMD:
1633         wsa_macro_config_compander(component, w->shift, event);
1634         wsa_macro_config_softclip(component, w->shift, event);
1635         wsa_macro_enable_prim_interpolator(component, reg, event);
1636         if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1637             (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1638              wsa->comp_enabled[WSA_MACRO_COMP2])) {
1639             snd_soc_component_update_bits(component,
1640                     CDC_WSA_RX0_RX_PATH_SEC1,
1641                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1642                     CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1643             snd_soc_component_update_bits(component,
1644                     CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1645                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1646                     CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1647             snd_soc_component_update_bits(component,
1648                     CDC_WSA_RX1_RX_PATH_SEC1,
1649                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1650                     CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1651             snd_soc_component_update_bits(component,
1652                     CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1653                     CDC_WSA_RX_PGA_HALF_DB_MASK,
1654                     CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1655             offset_val = 2;
1656             val = snd_soc_component_read(component, gain_reg);
1657             val += offset_val;
1658             snd_soc_component_write(component, gain_reg, val);
1659         }
1660         wsa_macro_config_ear_spkr_gain(component, wsa,
1661                         event, gain_reg);
1662         break;
1663     }
1664 
1665     return 0;
1666 }
1667 
1668 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
1669                      struct snd_kcontrol *kcontrol,
1670                      int event)
1671 {
1672     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1673     u16 boost_path_ctl, boost_path_cfg1;
1674     u16 reg, reg_mix;
1675 
1676     if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) {
1677         boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
1678         boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
1679         reg = CDC_WSA_RX0_RX_PATH_CTL;
1680         reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1681     } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) {
1682         boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
1683         boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
1684         reg = CDC_WSA_RX1_RX_PATH_CTL;
1685         reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1686     }
1687 
1688     switch (event) {
1689     case SND_SOC_DAPM_PRE_PMU:
1690         snd_soc_component_update_bits(component, boost_path_cfg1,
1691                           CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1692                           CDC_WSA_RX_PATH_SMART_BST_ENABLE);
1693         snd_soc_component_update_bits(component, boost_path_ctl,
1694                           CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1695                           CDC_WSA_BOOST_PATH_CLK_ENABLE);
1696         if ((snd_soc_component_read(component, reg_mix)) & 0x10)
1697             snd_soc_component_update_bits(component, reg_mix,
1698                         0x10, 0x00);
1699         break;
1700     case SND_SOC_DAPM_POST_PMU:
1701         snd_soc_component_update_bits(component, reg, 0x10, 0x00);
1702         break;
1703     case SND_SOC_DAPM_POST_PMD:
1704         snd_soc_component_update_bits(component, boost_path_ctl,
1705                           CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1706                           CDC_WSA_BOOST_PATH_CLK_DISABLE);
1707         snd_soc_component_update_bits(component, boost_path_cfg1,
1708                           CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1709                           CDC_WSA_RX_PATH_SMART_BST_DISABLE);
1710         break;
1711     }
1712 
1713     return 0;
1714 }
1715 
1716 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
1717                  struct snd_kcontrol *kcontrol,
1718                  int event)
1719 {
1720     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1721     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1722     u16 val, ec_tx, ec_hq_reg;
1723 
1724     val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1725 
1726     switch (w->shift) {
1727     case WSA_MACRO_EC0_MUX:
1728         val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
1729         ec_tx = val - 1;
1730         break;
1731     case WSA_MACRO_EC1_MUX:
1732         val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
1733         ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
1734         break;
1735     default:
1736         dev_err(component->dev, "%s: Invalid shift %u\n",
1737             __func__, w->shift);
1738         return -EINVAL;
1739     }
1740 
1741     if (wsa->ec_hq[ec_tx]) {
1742         ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx;
1743         snd_soc_component_update_bits(component, ec_hq_reg,
1744                          CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
1745                          CDC_WSA_EC_HQ_EC_CLK_ENABLE);
1746         ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
1747         /* default set to 48k */
1748         snd_soc_component_update_bits(component, ec_hq_reg,
1749                       CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
1750                       CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
1751     }
1752 
1753     return 0;
1754 }
1755 
1756 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
1757                    struct snd_ctl_elem_value *ucontrol)
1758 {
1759 
1760     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1761     int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1762     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1763 
1764     ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
1765 
1766     return 0;
1767 }
1768 
1769 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
1770                    struct snd_ctl_elem_value *ucontrol)
1771 {
1772     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1773     int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1774     int value = ucontrol->value.integer.value[0];
1775     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1776 
1777     wsa->ec_hq[ec_tx] = value;
1778 
1779     return 0;
1780 }
1781 
1782 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
1783                    struct snd_ctl_elem_value *ucontrol)
1784 {
1785 
1786     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1787     int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1788     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1789 
1790     ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
1791     return 0;
1792 }
1793 
1794 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
1795                    struct snd_ctl_elem_value *ucontrol)
1796 {
1797     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1798     int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1799     int value = ucontrol->value.integer.value[0];
1800     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1801 
1802     wsa->comp_enabled[comp] = value;
1803 
1804     return 0;
1805 }
1806 
1807 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
1808                       struct snd_ctl_elem_value *ucontrol)
1809 {
1810     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1811     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1812 
1813     ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;
1814 
1815     return 0;
1816 }
1817 
1818 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
1819                       struct snd_ctl_elem_value *ucontrol)
1820 {
1821     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1822     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1823 
1824     wsa->ear_spkr_gain =  ucontrol->value.integer.value[0];
1825 
1826     return 0;
1827 }
1828 
1829 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
1830                 struct snd_ctl_elem_value *ucontrol)
1831 {
1832     struct snd_soc_dapm_widget *widget =
1833         snd_soc_dapm_kcontrol_widget(kcontrol);
1834     struct snd_soc_component *component =
1835                 snd_soc_dapm_to_component(widget->dapm);
1836     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1837 
1838     ucontrol->value.integer.value[0] =
1839             wsa->rx_port_value[widget->shift];
1840     return 0;
1841 }
1842 
1843 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
1844                 struct snd_ctl_elem_value *ucontrol)
1845 {
1846     struct snd_soc_dapm_widget *widget =
1847         snd_soc_dapm_kcontrol_widget(kcontrol);
1848     struct snd_soc_component *component =
1849                 snd_soc_dapm_to_component(widget->dapm);
1850     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1851     struct snd_soc_dapm_update *update = NULL;
1852     u32 rx_port_value = ucontrol->value.integer.value[0];
1853     u32 bit_input;
1854     u32 aif_rst;
1855     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1856 
1857     aif_rst = wsa->rx_port_value[widget->shift];
1858     if (!rx_port_value) {
1859         if (aif_rst == 0) {
1860             dev_err(component->dev, "%s: AIF reset already\n", __func__);
1861             return 0;
1862         }
1863         if (aif_rst >= WSA_MACRO_RX_MAX) {
1864             dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
1865             return 0;
1866         }
1867     }
1868     wsa->rx_port_value[widget->shift] = rx_port_value;
1869 
1870     bit_input = widget->shift;
1871 
1872     switch (rx_port_value) {
1873     case 0:
1874         if (wsa->active_ch_cnt[aif_rst]) {
1875             clear_bit(bit_input,
1876                   &wsa->active_ch_mask[aif_rst]);
1877             wsa->active_ch_cnt[aif_rst]--;
1878         }
1879         break;
1880     case 1:
1881     case 2:
1882         set_bit(bit_input,
1883             &wsa->active_ch_mask[rx_port_value]);
1884         wsa->active_ch_cnt[rx_port_value]++;
1885         break;
1886     default:
1887         dev_err(component->dev,
1888             "%s: Invalid AIF_ID for WSA RX MUX %d\n",
1889             __func__, rx_port_value);
1890         return -EINVAL;
1891     }
1892 
1893     snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
1894                     rx_port_value, e, update);
1895     return 0;
1896 }
1897 
1898 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
1899                       struct snd_ctl_elem_value *ucontrol)
1900 {
1901     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1902     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1903     int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;
1904 
1905     ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
1906 
1907     return 0;
1908 }
1909 
1910 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
1911                       struct snd_ctl_elem_value *ucontrol)
1912 {
1913     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1914     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1915     int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1916 
1917     wsa->is_softclip_on[path] =  ucontrol->value.integer.value[0];
1918 
1919     return 0;
1920 }
1921 
1922 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
1923     SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
1924              wsa_macro_ear_spkr_pa_gain_get,
1925              wsa_macro_ear_spkr_pa_gain_put),
1926     SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
1927             WSA_MACRO_SOFTCLIP0, 1, 0,
1928             wsa_macro_soft_clip_enable_get,
1929             wsa_macro_soft_clip_enable_put),
1930     SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
1931             WSA_MACRO_SOFTCLIP1, 1, 0,
1932             wsa_macro_soft_clip_enable_get,
1933             wsa_macro_soft_clip_enable_put),
1934 
1935     SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
1936               -84, 40, digital_gain),
1937     SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
1938               -84, 40, digital_gain),
1939 
1940     SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
1941     SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
1942     SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
1943            1, 0),
1944     SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
1945            1, 0),
1946     SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
1947                wsa_macro_get_compander, wsa_macro_set_compander),
1948     SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
1949                wsa_macro_get_compander, wsa_macro_set_compander),
1950     SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
1951                wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
1952     SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
1953                wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
1954 };
1955 
1956 static const struct soc_enum rx_mux_enum =
1957     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
1958 
1959 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
1960     SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
1961               wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1962     SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
1963               wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1964     SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
1965               wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1966     SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
1967               wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1968 };
1969 
1970 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
1971                        struct snd_ctl_elem_value *ucontrol)
1972 {
1973     struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1974     struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1975     struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1976     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1977     u32 spk_tx_id = mixer->shift;
1978     u32 dai_id = widget->shift;
1979 
1980     if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
1981         ucontrol->value.integer.value[0] = 1;
1982     else
1983         ucontrol->value.integer.value[0] = 0;
1984 
1985     return 0;
1986 }
1987 
1988 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
1989                        struct snd_ctl_elem_value *ucontrol)
1990 {
1991     struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1992     struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1993     struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1994     struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1995     u32 enable = ucontrol->value.integer.value[0];
1996     u32 spk_tx_id = mixer->shift;
1997 
1998     if (enable) {
1999         if (spk_tx_id == WSA_MACRO_TX0 &&
2000             !test_bit(WSA_MACRO_TX0,
2001                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2002             set_bit(WSA_MACRO_TX0,
2003                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2004             wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2005         }
2006         if (spk_tx_id == WSA_MACRO_TX1 &&
2007             !test_bit(WSA_MACRO_TX1,
2008                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2009             set_bit(WSA_MACRO_TX1,
2010                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2011             wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2012         }
2013     } else {
2014         if (spk_tx_id == WSA_MACRO_TX0 &&
2015             test_bit(WSA_MACRO_TX0,
2016                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2017             clear_bit(WSA_MACRO_TX0,
2018                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2019             wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2020         }
2021         if (spk_tx_id == WSA_MACRO_TX1 &&
2022             test_bit(WSA_MACRO_TX1,
2023                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2024             clear_bit(WSA_MACRO_TX1,
2025                 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2026             wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2027         }
2028     }
2029     snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
2030 
2031     return 0;
2032 }
2033 
2034 static const struct snd_kcontrol_new aif_vi_mixer[] = {
2035     SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
2036             wsa_macro_vi_feed_mixer_get,
2037             wsa_macro_vi_feed_mixer_put),
2038     SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
2039             wsa_macro_vi_feed_mixer_get,
2040             wsa_macro_vi_feed_mixer_put),
2041 };
2042 
2043 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
2044     SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
2045                 SND_SOC_NOPM, 0, 0),
2046     SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
2047                 SND_SOC_NOPM, 0, 0),
2048 
2049     SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
2050                    SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
2051                    wsa_macro_enable_vi_feedback,
2052                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2053     SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
2054                  SND_SOC_NOPM, 0, 0),
2055 
2056     SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
2057                0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
2058     SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
2059                WSA_MACRO_EC0_MUX, 0,
2060                &rx_mix_ec0_mux, wsa_macro_enable_echo,
2061                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2062     SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
2063                WSA_MACRO_EC1_MUX, 0,
2064                &rx_mix_ec1_mux, wsa_macro_enable_echo,
2065                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2066 
2067     SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
2068              &rx_mux[WSA_MACRO_RX0]),
2069     SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
2070              &rx_mux[WSA_MACRO_RX1]),
2071     SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
2072              &rx_mux[WSA_MACRO_RX_MIX0]),
2073     SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
2074              &rx_mux[WSA_MACRO_RX_MIX1]),
2075 
2076     SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2077     SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2078     SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2079     SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2080 
2081     SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux),
2082     SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux),
2083     SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux),
2084     SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
2085                0, &rx0_mix_mux, wsa_macro_enable_mix_path,
2086                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2087     SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux),
2088     SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux),
2089     SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux),
2090     SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
2091                0, &rx1_mix_mux, wsa_macro_enable_mix_path,
2092                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2093 
2094     SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
2095                  wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2096     SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0,
2097                  wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2098 
2099     SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2100     SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2101 
2102     SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
2103              4, 0, &rx0_sidetone_mix_mux),
2104 
2105     SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
2106     SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
2107     SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),
2108 
2109     SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
2110                  WSA_MACRO_COMP1, 0, NULL, 0,
2111                  wsa_macro_enable_interpolator,
2112                  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2113                  SND_SOC_DAPM_POST_PMD),
2114 
2115     SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
2116                  WSA_MACRO_COMP2, 0, NULL, 0,
2117                  wsa_macro_enable_interpolator,
2118                  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2119                  SND_SOC_DAPM_POST_PMD),
2120 
2121     SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
2122                  NULL, 0, wsa_macro_spk_boost_event,
2123                  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2124                  SND_SOC_DAPM_POST_PMD),
2125 
2126     SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
2127                  NULL, 0, wsa_macro_spk_boost_event,
2128                  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2129                  SND_SOC_DAPM_POST_PMD),
2130 
2131     SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
2132     SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
2133     SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),
2134 
2135     SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
2136     SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
2137     SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2138     SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2139     SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
2140                   wsa_macro_mclk_event,
2141                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2142 };
2143 
2144 static const struct snd_soc_dapm_route wsa_audio_map[] = {
2145     /* VI Feedback */
2146     {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
2147     {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
2148     {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
2149     {"WSA AIF_VI", NULL, "WSA_MCLK"},
2150 
2151     {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2152     {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2153     {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2154     {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2155     {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
2156     {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
2157     {"WSA AIF_ECHO", NULL, "WSA_MCLK"},
2158 
2159     {"WSA AIF1 PB", NULL, "WSA_MCLK"},
2160     {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
2161 
2162     {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2163     {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2164     {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2165     {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2166 
2167     {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2168     {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2169     {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2170     {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2171 
2172     {"WSA RX0", NULL, "WSA RX0 MUX"},
2173     {"WSA RX1", NULL, "WSA RX1 MUX"},
2174     {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
2175     {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
2176 
2177     {"WSA RX0", NULL, "WSA_RX0_CLK"},
2178     {"WSA RX1", NULL, "WSA_RX1_CLK"},
2179     {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
2180     {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},
2181 
2182     {"WSA_RX0 INP0", "RX0", "WSA RX0"},
2183     {"WSA_RX0 INP0", "RX1", "WSA RX1"},
2184     {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
2185     {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
2186     {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
2187     {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
2188     {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},
2189 
2190     {"WSA_RX0 INP1", "RX0", "WSA RX0"},
2191     {"WSA_RX0 INP1", "RX1", "WSA RX1"},
2192     {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
2193     {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
2194     {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
2195     {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
2196     {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},
2197 
2198     {"WSA_RX0 INP2", "RX0", "WSA RX0"},
2199     {"WSA_RX0 INP2", "RX1", "WSA RX1"},
2200     {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
2201     {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
2202     {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
2203     {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
2204     {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},
2205 
2206     {"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
2207     {"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
2208     {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2209     {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2210     {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},
2211 
2212     {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
2213     {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
2214     {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
2215     {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
2216     {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},
2217 
2218     {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
2219     {"WSA_SPK1 OUT", NULL, "WSA_MCLK"},
2220 
2221     {"WSA_RX1 INP0", "RX0", "WSA RX0"},
2222     {"WSA_RX1 INP0", "RX1", "WSA RX1"},
2223     {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
2224     {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
2225     {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
2226     {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
2227     {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},
2228 
2229     {"WSA_RX1 INP1", "RX0", "WSA RX0"},
2230     {"WSA_RX1 INP1", "RX1", "WSA RX1"},
2231     {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
2232     {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
2233     {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
2234     {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
2235     {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},
2236 
2237     {"WSA_RX1 INP2", "RX0", "WSA RX0"},
2238     {"WSA_RX1 INP2", "RX1", "WSA RX1"},
2239     {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
2240     {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
2241     {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
2242     {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
2243     {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},
2244 
2245     {"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
2246     {"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
2247     {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2248     {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2249     {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},
2250 
2251     {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
2252     {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},
2253 
2254     {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
2255     {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
2256     {"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
2257 };
2258 
2259 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
2260 {
2261     struct regmap *regmap = wsa->regmap;
2262 
2263     if (enable) {
2264         int ret;
2265 
2266         ret = clk_prepare_enable(wsa->mclk);
2267         if (ret) {
2268             dev_err(wsa->dev, "failed to enable mclk\n");
2269             return ret;
2270         }
2271         wsa_macro_mclk_enable(wsa, true);
2272 
2273         /* reset swr ip */
2274         if (wsa->reset_swr)
2275             regmap_update_bits(regmap,
2276                        CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2277                        CDC_WSA_SWR_RST_EN_MASK,
2278                        CDC_WSA_SWR_RST_ENABLE);
2279 
2280         regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2281                    CDC_WSA_SWR_CLK_EN_MASK,
2282                    CDC_WSA_SWR_CLK_ENABLE);
2283 
2284         /* Bring out of reset */
2285         if (wsa->reset_swr)
2286             regmap_update_bits(regmap,
2287                        CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2288                        CDC_WSA_SWR_RST_EN_MASK,
2289                        CDC_WSA_SWR_RST_DISABLE);
2290         wsa->reset_swr = false;
2291     } else {
2292         regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2293                    CDC_WSA_SWR_CLK_EN_MASK, 0);
2294         wsa_macro_mclk_enable(wsa, false);
2295         clk_disable_unprepare(wsa->mclk);
2296     }
2297 
2298     return 0;
2299 }
2300 
2301 static int wsa_macro_component_probe(struct snd_soc_component *comp)
2302 {
2303     struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
2304 
2305     snd_soc_component_init_regmap(comp, wsa->regmap);
2306 
2307     wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
2308 
2309     /* set SPKR rate to FS_2P4_3P072 */
2310     snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
2311                 CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2312                 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2313 
2314     snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
2315                 CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2316                 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2317 
2318     wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);
2319 
2320     return 0;
2321 }
2322 
2323 static int swclk_gate_enable(struct clk_hw *hw)
2324 {
2325     return wsa_swrm_clock(to_wsa_macro(hw), true);
2326 }
2327 
2328 static void swclk_gate_disable(struct clk_hw *hw)
2329 {
2330     wsa_swrm_clock(to_wsa_macro(hw), false);
2331 }
2332 
2333 static int swclk_gate_is_enabled(struct clk_hw *hw)
2334 {
2335     struct wsa_macro *wsa = to_wsa_macro(hw);
2336     int ret, val;
2337 
2338     regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
2339     ret = val & BIT(0);
2340 
2341     return ret;
2342 }
2343 
2344 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2345                        unsigned long parent_rate)
2346 {
2347     return parent_rate / 2;
2348 }
2349 
2350 static const struct clk_ops swclk_gate_ops = {
2351     .prepare = swclk_gate_enable,
2352     .unprepare = swclk_gate_disable,
2353     .is_enabled = swclk_gate_is_enabled,
2354     .recalc_rate = swclk_recalc_rate,
2355 };
2356 
2357 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
2358 {
2359     struct device *dev = wsa->dev;
2360     const char *parent_clk_name;
2361     const char *clk_name = "mclk";
2362     struct clk_hw *hw;
2363     struct clk_init_data init;
2364     int ret;
2365 
2366     parent_clk_name = __clk_get_name(wsa->npl);
2367 
2368     init.name = clk_name;
2369     init.ops = &swclk_gate_ops;
2370     init.flags = 0;
2371     init.parent_names = &parent_clk_name;
2372     init.num_parents = 1;
2373     wsa->hw.init = &init;
2374     hw = &wsa->hw;
2375     ret = clk_hw_register(wsa->dev, hw);
2376     if (ret)
2377         return ret;
2378 
2379     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2380 }
2381 
2382 static const struct snd_soc_component_driver wsa_macro_component_drv = {
2383     .name = "WSA MACRO",
2384     .probe = wsa_macro_component_probe,
2385     .controls = wsa_macro_snd_controls,
2386     .num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
2387     .dapm_widgets = wsa_macro_dapm_widgets,
2388     .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
2389     .dapm_routes = wsa_audio_map,
2390     .num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
2391 };
2392 
2393 static int wsa_macro_probe(struct platform_device *pdev)
2394 {
2395     struct device *dev = &pdev->dev;
2396     struct wsa_macro *wsa;
2397     void __iomem *base;
2398     int ret;
2399 
2400     wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
2401     if (!wsa)
2402         return -ENOMEM;
2403 
2404     wsa->macro = devm_clk_get_optional(dev, "macro");
2405     if (IS_ERR(wsa->macro))
2406         return PTR_ERR(wsa->macro);
2407 
2408     wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
2409     if (IS_ERR(wsa->dcodec))
2410         return PTR_ERR(wsa->dcodec);
2411 
2412     wsa->mclk = devm_clk_get(dev, "mclk");
2413     if (IS_ERR(wsa->mclk))
2414         return PTR_ERR(wsa->mclk);
2415 
2416     wsa->npl = devm_clk_get(dev, "npl");
2417     if (IS_ERR(wsa->npl))
2418         return PTR_ERR(wsa->npl);
2419 
2420     wsa->fsgen = devm_clk_get(dev, "fsgen");
2421     if (IS_ERR(wsa->fsgen))
2422         return PTR_ERR(wsa->fsgen);
2423 
2424     base = devm_platform_ioremap_resource(pdev, 0);
2425     if (IS_ERR(base))
2426         return PTR_ERR(base);
2427 
2428     wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config);
2429     if (IS_ERR(wsa->regmap))
2430         return PTR_ERR(wsa->regmap);
2431 
2432     dev_set_drvdata(dev, wsa);
2433 
2434     wsa->reset_swr = true;
2435     wsa->dev = dev;
2436 
2437     /* set MCLK and NPL rates */
2438     clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
2439     clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);
2440 
2441     ret = clk_prepare_enable(wsa->macro);
2442     if (ret)
2443         goto err;
2444 
2445     ret = clk_prepare_enable(wsa->dcodec);
2446     if (ret)
2447         goto err_dcodec;
2448 
2449     ret = clk_prepare_enable(wsa->mclk);
2450     if (ret)
2451         goto err_mclk;
2452 
2453     ret = clk_prepare_enable(wsa->npl);
2454     if (ret)
2455         goto err_npl;
2456 
2457     ret = clk_prepare_enable(wsa->fsgen);
2458     if (ret)
2459         goto err_fsgen;
2460 
2461     ret = wsa_macro_register_mclk_output(wsa);
2462     if (ret)
2463         goto err_clkout;
2464 
2465 
2466     ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
2467                           wsa_macro_dai,
2468                           ARRAY_SIZE(wsa_macro_dai));
2469     if (ret)
2470         goto err_clkout;
2471 
2472     pm_runtime_set_autosuspend_delay(dev, 3000);
2473     pm_runtime_use_autosuspend(dev);
2474     pm_runtime_mark_last_busy(dev);
2475     pm_runtime_set_active(dev);
2476     pm_runtime_enable(dev);
2477 
2478     return 0;
2479 
2480 err_clkout:
2481     clk_disable_unprepare(wsa->fsgen);
2482 err_fsgen:
2483     clk_disable_unprepare(wsa->npl);
2484 err_npl:
2485     clk_disable_unprepare(wsa->mclk);
2486 err_mclk:
2487     clk_disable_unprepare(wsa->dcodec);
2488 err_dcodec:
2489     clk_disable_unprepare(wsa->macro);
2490 err:
2491     return ret;
2492 
2493 }
2494 
2495 static int wsa_macro_remove(struct platform_device *pdev)
2496 {
2497     struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);
2498 
2499     clk_disable_unprepare(wsa->macro);
2500     clk_disable_unprepare(wsa->dcodec);
2501     clk_disable_unprepare(wsa->mclk);
2502     clk_disable_unprepare(wsa->npl);
2503     clk_disable_unprepare(wsa->fsgen);
2504 
2505     return 0;
2506 }
2507 
2508 static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev)
2509 {
2510     struct wsa_macro *wsa = dev_get_drvdata(dev);
2511 
2512     regcache_cache_only(wsa->regmap, true);
2513     regcache_mark_dirty(wsa->regmap);
2514 
2515     clk_disable_unprepare(wsa->mclk);
2516     clk_disable_unprepare(wsa->npl);
2517     clk_disable_unprepare(wsa->fsgen);
2518 
2519     return 0;
2520 }
2521 
2522 static int __maybe_unused wsa_macro_runtime_resume(struct device *dev)
2523 {
2524     struct wsa_macro *wsa = dev_get_drvdata(dev);
2525     int ret;
2526 
2527     ret = clk_prepare_enable(wsa->mclk);
2528     if (ret) {
2529         dev_err(dev, "unable to prepare mclk\n");
2530         return ret;
2531     }
2532 
2533     ret = clk_prepare_enable(wsa->npl);
2534     if (ret) {
2535         dev_err(dev, "unable to prepare mclkx2\n");
2536         goto err_npl;
2537     }
2538 
2539     ret = clk_prepare_enable(wsa->fsgen);
2540     if (ret) {
2541         dev_err(dev, "unable to prepare fsgen\n");
2542         goto err_fsgen;
2543     }
2544 
2545     regcache_cache_only(wsa->regmap, false);
2546     regcache_sync(wsa->regmap);
2547 
2548     return 0;
2549 err_fsgen:
2550     clk_disable_unprepare(wsa->npl);
2551 err_npl:
2552     clk_disable_unprepare(wsa->mclk);
2553 
2554     return ret;
2555 }
2556 
2557 static const struct dev_pm_ops wsa_macro_pm_ops = {
2558     SET_RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL)
2559 };
2560 
2561 static const struct of_device_id wsa_macro_dt_match[] = {
2562     {.compatible = "qcom,sc7280-lpass-wsa-macro"},
2563     {.compatible = "qcom,sm8250-lpass-wsa-macro"},
2564     {}
2565 };
2566 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);
2567 
2568 static struct platform_driver wsa_macro_driver = {
2569     .driver = {
2570         .name = "wsa_macro",
2571         .of_match_table = wsa_macro_dt_match,
2572         .pm = &wsa_macro_pm_ops,
2573     },
2574     .probe = wsa_macro_probe,
2575     .remove = wsa_macro_remove,
2576 };
2577 
2578 module_platform_driver(wsa_macro_driver);
2579 MODULE_DESCRIPTION("WSA macro driver");
2580 MODULE_LICENSE("GPL");
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