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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
0003 
0004 #include <linux/clk.h>
0005 #include <linux/clk-provider.h>
0006 #include <linux/init.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/of_clk.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <sound/soc.h>
0016 #include <sound/soc-dapm.h>
0017 #include <sound/tlv.h>
0018 
0019 #include "lpass-macro-common.h"
0020 
0021 /* VA macro registers */
0022 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL    (0x0000)
0023 #define CDC_VA_MCLK_CONTROL_EN          BIT(0)
0024 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL  (0x0004)
0025 #define CDC_VA_FS_CONTROL_EN            BIT(0)
0026 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL     (0x0008)
0027 #define CDC_VA_TOP_CSR_TOP_CFG0         (0x0080)
0028 #define CDC_VA_FS_BROADCAST_EN          BIT(1)
0029 #define CDC_VA_TOP_CSR_DMIC0_CTL        (0x0084)
0030 #define CDC_VA_TOP_CSR_DMIC1_CTL        (0x0088)
0031 #define CDC_VA_TOP_CSR_DMIC2_CTL        (0x008C)
0032 #define CDC_VA_TOP_CSR_DMIC3_CTL        (0x0090)
0033 #define CDC_VA_DMIC_EN_MASK         BIT(0)
0034 #define CDC_VA_DMIC_ENABLE          BIT(0)
0035 #define CDC_VA_DMIC_CLK_SEL_MASK        GENMASK(3, 1)
0036 #define CDC_VA_DMIC_CLK_SEL_SHFT        1
0037 #define CDC_VA_DMIC_CLK_SEL_DIV0        0x0
0038 #define CDC_VA_DMIC_CLK_SEL_DIV1        0x2
0039 #define CDC_VA_DMIC_CLK_SEL_DIV2        0x4
0040 #define CDC_VA_DMIC_CLK_SEL_DIV3        0x6
0041 #define CDC_VA_DMIC_CLK_SEL_DIV4        0x8
0042 #define CDC_VA_DMIC_CLK_SEL_DIV5        0xa
0043 #define CDC_VA_TOP_CSR_DMIC_CFG         (0x0094)
0044 #define CDC_VA_RESET_ALL_DMICS_MASK     BIT(7)
0045 #define CDC_VA_RESET_ALL_DMICS_RESET        BIT(7)
0046 #define CDC_VA_RESET_ALL_DMICS_DISABLE      0
0047 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK       BIT(3)
0048 #define CDC_VA_DMIC3_FREQ_CHANGE_EN     BIT(3)
0049 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK       BIT(2)
0050 #define CDC_VA_DMIC2_FREQ_CHANGE_EN     BIT(2)
0051 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK       BIT(1)
0052 #define CDC_VA_DMIC1_FREQ_CHANGE_EN     BIT(1)
0053 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK       BIT(0)
0054 #define CDC_VA_DMIC0_FREQ_CHANGE_EN     BIT(0)
0055 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE     0
0056 #define CDC_VA_TOP_CSR_DEBUG_BUS        (0x009C)
0057 #define CDC_VA_TOP_CSR_DEBUG_EN         (0x00A0)
0058 #define CDC_VA_TOP_CSR_TX_I2S_CTL       (0x00A4)
0059 #define CDC_VA_TOP_CSR_I2S_CLK          (0x00A8)
0060 #define CDC_VA_TOP_CSR_I2S_RESET        (0x00AC)
0061 #define CDC_VA_TOP_CSR_CORE_ID_0        (0x00C0)
0062 #define CDC_VA_TOP_CSR_CORE_ID_1        (0x00C4)
0063 #define CDC_VA_TOP_CSR_CORE_ID_2        (0x00C8)
0064 #define CDC_VA_TOP_CSR_CORE_ID_3        (0x00CC)
0065 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0     (0x00D0)
0066 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1     (0x00D4)
0067 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2     (0x00D8)
0068 #define CDC_VA_TOP_CSR_SWR_CTRL         (0x00DC)
0069 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0        (0x0100)
0070 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1        (0x0104)
0071 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0        (0x0108)
0072 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1        (0x010C)
0073 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0        (0x0110)
0074 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1        (0x0114)
0075 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0        (0x0118)
0076 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1        (0x011C)
0077 #define CDC_VA_TX0_TX_PATH_CTL          (0x0400)
0078 #define CDC_VA_TX_PATH_CLK_EN_MASK      BIT(5)
0079 #define CDC_VA_TX_PATH_CLK_EN           BIT(5)
0080 #define CDC_VA_TX_PATH_CLK_DISABLE      0
0081 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK     BIT(4)
0082 #define CDC_VA_TX_PATH_PGA_MUTE_EN      BIT(4)
0083 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE     0
0084 #define CDC_VA_TX0_TX_PATH_CFG0         (0x0404)
0085 #define CDC_VA_ADC_MODE_MASK            GENMASK(2, 1)
0086 #define CDC_VA_ADC_MODE_SHIFT           1
0087 #define  TX_HPF_CUT_OFF_FREQ_MASK       GENMASK(6, 5)
0088 #define  CF_MIN_3DB_4HZ         0x0
0089 #define  CF_MIN_3DB_75HZ        0x1
0090 #define  CF_MIN_3DB_150HZ       0x2
0091 #define CDC_VA_TX0_TX_PATH_CFG1         (0x0408)
0092 #define CDC_VA_TX0_TX_VOL_CTL           (0x040C)
0093 #define CDC_VA_TX0_TX_PATH_SEC0         (0x0410)
0094 #define CDC_VA_TX0_TX_PATH_SEC1         (0x0414)
0095 #define CDC_VA_TX0_TX_PATH_SEC2         (0x0418)
0096 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK   BIT(1)
0097 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ    BIT(1)
0098 #define CDC_VA_TX_HPF_ZERO_GATE_MASK        BIT(0)
0099 #define CDC_VA_TX_HPF_ZERO_NO_GATE      BIT(0)
0100 #define CDC_VA_TX_HPF_ZERO_GATE         0
0101 #define CDC_VA_TX0_TX_PATH_SEC3         (0x041C)
0102 #define CDC_VA_TX0_TX_PATH_SEC4         (0x0420)
0103 #define CDC_VA_TX0_TX_PATH_SEC5         (0x0424)
0104 #define CDC_VA_TX0_TX_PATH_SEC6         (0x0428)
0105 #define CDC_VA_TX0_TX_PATH_SEC7         (0x042C)
0106 #define CDC_VA_TX1_TX_PATH_CTL          (0x0480)
0107 #define CDC_VA_TX1_TX_PATH_CFG0         (0x0484)
0108 #define CDC_VA_TX1_TX_PATH_CFG1         (0x0488)
0109 #define CDC_VA_TX1_TX_VOL_CTL           (0x048C)
0110 #define CDC_VA_TX1_TX_PATH_SEC0         (0x0490)
0111 #define CDC_VA_TX1_TX_PATH_SEC1         (0x0494)
0112 #define CDC_VA_TX1_TX_PATH_SEC2         (0x0498)
0113 #define CDC_VA_TX1_TX_PATH_SEC3         (0x049C)
0114 #define CDC_VA_TX1_TX_PATH_SEC4         (0x04A0)
0115 #define CDC_VA_TX1_TX_PATH_SEC5         (0x04A4)
0116 #define CDC_VA_TX1_TX_PATH_SEC6         (0x04A8)
0117 #define CDC_VA_TX2_TX_PATH_CTL          (0x0500)
0118 #define CDC_VA_TX2_TX_PATH_CFG0         (0x0504)
0119 #define CDC_VA_TX2_TX_PATH_CFG1         (0x0508)
0120 #define CDC_VA_TX2_TX_VOL_CTL           (0x050C)
0121 #define CDC_VA_TX2_TX_PATH_SEC0         (0x0510)
0122 #define CDC_VA_TX2_TX_PATH_SEC1         (0x0514)
0123 #define CDC_VA_TX2_TX_PATH_SEC2         (0x0518)
0124 #define CDC_VA_TX2_TX_PATH_SEC3         (0x051C)
0125 #define CDC_VA_TX2_TX_PATH_SEC4         (0x0520)
0126 #define CDC_VA_TX2_TX_PATH_SEC5         (0x0524)
0127 #define CDC_VA_TX2_TX_PATH_SEC6         (0x0528)
0128 #define CDC_VA_TX3_TX_PATH_CTL          (0x0580)
0129 #define CDC_VA_TX3_TX_PATH_CFG0         (0x0584)
0130 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK    BIT(7)
0131 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC    BIT(7)
0132 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC     0
0133 #define CDC_VA_TX3_TX_PATH_CFG1         (0x0588)
0134 #define CDC_VA_TX3_TX_VOL_CTL           (0x058C)
0135 #define CDC_VA_TX3_TX_PATH_SEC0         (0x0590)
0136 #define CDC_VA_TX3_TX_PATH_SEC1         (0x0594)
0137 #define CDC_VA_TX3_TX_PATH_SEC2         (0x0598)
0138 #define CDC_VA_TX3_TX_PATH_SEC3         (0x059C)
0139 #define CDC_VA_TX3_TX_PATH_SEC4         (0x05A0)
0140 #define CDC_VA_TX3_TX_PATH_SEC5         (0x05A4)
0141 #define CDC_VA_TX3_TX_PATH_SEC6         (0x05A8)
0142 
0143 #define VA_MAX_OFFSET               (0x07A8)
0144 
0145 #define VA_MACRO_NUM_DECIMATORS 4
0146 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0147             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
0148             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
0149 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0150         SNDRV_PCM_FMTBIT_S24_LE |\
0151         SNDRV_PCM_FMTBIT_S24_3LE)
0152 
0153 #define VA_MACRO_MCLK_FREQ 9600000
0154 #define VA_MACRO_TX_PATH_OFFSET 0x80
0155 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
0156 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
0157 
0158 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
0159 
0160 enum {
0161     VA_MACRO_AIF_INVALID = 0,
0162     VA_MACRO_AIF1_CAP,
0163     VA_MACRO_AIF2_CAP,
0164     VA_MACRO_AIF3_CAP,
0165     VA_MACRO_MAX_DAIS,
0166 };
0167 
0168 enum {
0169     VA_MACRO_DEC0,
0170     VA_MACRO_DEC1,
0171     VA_MACRO_DEC2,
0172     VA_MACRO_DEC3,
0173     VA_MACRO_DEC4,
0174     VA_MACRO_DEC5,
0175     VA_MACRO_DEC6,
0176     VA_MACRO_DEC7,
0177     VA_MACRO_DEC_MAX,
0178 };
0179 
0180 enum {
0181     VA_MACRO_CLK_DIV_2,
0182     VA_MACRO_CLK_DIV_3,
0183     VA_MACRO_CLK_DIV_4,
0184     VA_MACRO_CLK_DIV_6,
0185     VA_MACRO_CLK_DIV_8,
0186     VA_MACRO_CLK_DIV_16,
0187 };
0188 
0189 #define VA_NUM_CLKS_MAX     3
0190 
0191 struct va_macro {
0192     struct device *dev;
0193     unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
0194     unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
0195     u16 dmic_clk_div;
0196 
0197     int dec_mode[VA_MACRO_NUM_DECIMATORS];
0198     struct regmap *regmap;
0199     struct clk *mclk;
0200     struct clk *macro;
0201     struct clk *dcodec;
0202     struct clk *fsgen;
0203     struct clk_hw hw;
0204     struct lpass_macro *pds;
0205 
0206     s32 dmic_0_1_clk_cnt;
0207     s32 dmic_2_3_clk_cnt;
0208     s32 dmic_4_5_clk_cnt;
0209     s32 dmic_6_7_clk_cnt;
0210     u8 dmic_0_1_clk_div;
0211     u8 dmic_2_3_clk_div;
0212     u8 dmic_4_5_clk_div;
0213     u8 dmic_6_7_clk_div;
0214 };
0215 
0216 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
0217 
0218 static bool va_is_volatile_register(struct device *dev, unsigned int reg)
0219 {
0220     switch (reg) {
0221     case CDC_VA_TOP_CSR_CORE_ID_0:
0222     case CDC_VA_TOP_CSR_CORE_ID_1:
0223     case CDC_VA_TOP_CSR_CORE_ID_2:
0224     case CDC_VA_TOP_CSR_CORE_ID_3:
0225     case CDC_VA_TOP_CSR_DMIC0_CTL:
0226     case CDC_VA_TOP_CSR_DMIC1_CTL:
0227     case CDC_VA_TOP_CSR_DMIC2_CTL:
0228     case CDC_VA_TOP_CSR_DMIC3_CTL:
0229         return true;
0230     }
0231     return false;
0232 }
0233 
0234 static const struct reg_default va_defaults[] = {
0235     /* VA macro */
0236     { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
0237     { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
0238     { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
0239     { CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
0240     { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
0241     { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
0242     { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
0243     { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
0244     { CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
0245     { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
0246     { CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
0247     { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
0248     { CDC_VA_TOP_CSR_I2S_CLK, 0x00},
0249     { CDC_VA_TOP_CSR_I2S_RESET, 0x00},
0250     { CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
0251     { CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
0252     { CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
0253     { CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
0254     { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
0255     { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
0256     { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
0257     { CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
0258 
0259     /* VA core */
0260     { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
0261     { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
0262     { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
0263     { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
0264     { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
0265     { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
0266     { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
0267     { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
0268     { CDC_VA_TX0_TX_PATH_CTL, 0x04},
0269     { CDC_VA_TX0_TX_PATH_CFG0, 0x10},
0270     { CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
0271     { CDC_VA_TX0_TX_VOL_CTL, 0x00},
0272     { CDC_VA_TX0_TX_PATH_SEC0, 0x00},
0273     { CDC_VA_TX0_TX_PATH_SEC1, 0x00},
0274     { CDC_VA_TX0_TX_PATH_SEC2, 0x01},
0275     { CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
0276     { CDC_VA_TX0_TX_PATH_SEC4, 0x20},
0277     { CDC_VA_TX0_TX_PATH_SEC5, 0x00},
0278     { CDC_VA_TX0_TX_PATH_SEC6, 0x00},
0279     { CDC_VA_TX0_TX_PATH_SEC7, 0x25},
0280     { CDC_VA_TX1_TX_PATH_CTL, 0x04},
0281     { CDC_VA_TX1_TX_PATH_CFG0, 0x10},
0282     { CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
0283     { CDC_VA_TX1_TX_VOL_CTL, 0x00},
0284     { CDC_VA_TX1_TX_PATH_SEC0, 0x00},
0285     { CDC_VA_TX1_TX_PATH_SEC1, 0x00},
0286     { CDC_VA_TX1_TX_PATH_SEC2, 0x01},
0287     { CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
0288     { CDC_VA_TX1_TX_PATH_SEC4, 0x20},
0289     { CDC_VA_TX1_TX_PATH_SEC5, 0x00},
0290     { CDC_VA_TX1_TX_PATH_SEC6, 0x00},
0291     { CDC_VA_TX2_TX_PATH_CTL, 0x04},
0292     { CDC_VA_TX2_TX_PATH_CFG0, 0x10},
0293     { CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
0294     { CDC_VA_TX2_TX_VOL_CTL, 0x00},
0295     { CDC_VA_TX2_TX_PATH_SEC0, 0x00},
0296     { CDC_VA_TX2_TX_PATH_SEC1, 0x00},
0297     { CDC_VA_TX2_TX_PATH_SEC2, 0x01},
0298     { CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
0299     { CDC_VA_TX2_TX_PATH_SEC4, 0x20},
0300     { CDC_VA_TX2_TX_PATH_SEC5, 0x00},
0301     { CDC_VA_TX2_TX_PATH_SEC6, 0x00},
0302     { CDC_VA_TX3_TX_PATH_CTL, 0x04},
0303     { CDC_VA_TX3_TX_PATH_CFG0, 0x10},
0304     { CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
0305     { CDC_VA_TX3_TX_VOL_CTL, 0x00},
0306     { CDC_VA_TX3_TX_PATH_SEC0, 0x00},
0307     { CDC_VA_TX3_TX_PATH_SEC1, 0x00},
0308     { CDC_VA_TX3_TX_PATH_SEC2, 0x01},
0309     { CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
0310     { CDC_VA_TX3_TX_PATH_SEC4, 0x20},
0311     { CDC_VA_TX3_TX_PATH_SEC5, 0x00},
0312     { CDC_VA_TX3_TX_PATH_SEC6, 0x00},
0313 };
0314 
0315 static bool va_is_rw_register(struct device *dev, unsigned int reg)
0316 {
0317     switch (reg) {
0318     case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
0319     case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
0320     case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
0321     case CDC_VA_TOP_CSR_TOP_CFG0:
0322     case CDC_VA_TOP_CSR_DMIC0_CTL:
0323     case CDC_VA_TOP_CSR_DMIC1_CTL:
0324     case CDC_VA_TOP_CSR_DMIC2_CTL:
0325     case CDC_VA_TOP_CSR_DMIC3_CTL:
0326     case CDC_VA_TOP_CSR_DMIC_CFG:
0327     case CDC_VA_TOP_CSR_DEBUG_BUS:
0328     case CDC_VA_TOP_CSR_DEBUG_EN:
0329     case CDC_VA_TOP_CSR_TX_I2S_CTL:
0330     case CDC_VA_TOP_CSR_I2S_CLK:
0331     case CDC_VA_TOP_CSR_I2S_RESET:
0332     case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
0333     case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
0334     case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
0335     case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
0336     case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
0337     case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
0338     case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
0339     case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
0340     case CDC_VA_TX0_TX_PATH_CTL:
0341     case CDC_VA_TX0_TX_PATH_CFG0:
0342     case CDC_VA_TX0_TX_PATH_CFG1:
0343     case CDC_VA_TX0_TX_VOL_CTL:
0344     case CDC_VA_TX0_TX_PATH_SEC0:
0345     case CDC_VA_TX0_TX_PATH_SEC1:
0346     case CDC_VA_TX0_TX_PATH_SEC2:
0347     case CDC_VA_TX0_TX_PATH_SEC3:
0348     case CDC_VA_TX0_TX_PATH_SEC4:
0349     case CDC_VA_TX0_TX_PATH_SEC5:
0350     case CDC_VA_TX0_TX_PATH_SEC6:
0351     case CDC_VA_TX0_TX_PATH_SEC7:
0352     case CDC_VA_TX1_TX_PATH_CTL:
0353     case CDC_VA_TX1_TX_PATH_CFG0:
0354     case CDC_VA_TX1_TX_PATH_CFG1:
0355     case CDC_VA_TX1_TX_VOL_CTL:
0356     case CDC_VA_TX1_TX_PATH_SEC0:
0357     case CDC_VA_TX1_TX_PATH_SEC1:
0358     case CDC_VA_TX1_TX_PATH_SEC2:
0359     case CDC_VA_TX1_TX_PATH_SEC3:
0360     case CDC_VA_TX1_TX_PATH_SEC4:
0361     case CDC_VA_TX1_TX_PATH_SEC5:
0362     case CDC_VA_TX1_TX_PATH_SEC6:
0363     case CDC_VA_TX2_TX_PATH_CTL:
0364     case CDC_VA_TX2_TX_PATH_CFG0:
0365     case CDC_VA_TX2_TX_PATH_CFG1:
0366     case CDC_VA_TX2_TX_VOL_CTL:
0367     case CDC_VA_TX2_TX_PATH_SEC0:
0368     case CDC_VA_TX2_TX_PATH_SEC1:
0369     case CDC_VA_TX2_TX_PATH_SEC2:
0370     case CDC_VA_TX2_TX_PATH_SEC3:
0371     case CDC_VA_TX2_TX_PATH_SEC4:
0372     case CDC_VA_TX2_TX_PATH_SEC5:
0373     case CDC_VA_TX2_TX_PATH_SEC6:
0374     case CDC_VA_TX3_TX_PATH_CTL:
0375     case CDC_VA_TX3_TX_PATH_CFG0:
0376     case CDC_VA_TX3_TX_PATH_CFG1:
0377     case CDC_VA_TX3_TX_VOL_CTL:
0378     case CDC_VA_TX3_TX_PATH_SEC0:
0379     case CDC_VA_TX3_TX_PATH_SEC1:
0380     case CDC_VA_TX3_TX_PATH_SEC2:
0381     case CDC_VA_TX3_TX_PATH_SEC3:
0382     case CDC_VA_TX3_TX_PATH_SEC4:
0383     case CDC_VA_TX3_TX_PATH_SEC5:
0384     case CDC_VA_TX3_TX_PATH_SEC6:
0385         return true;
0386     }
0387 
0388     return false;
0389 }
0390 
0391 static bool va_is_readable_register(struct device *dev, unsigned int reg)
0392 {
0393     switch (reg) {
0394     case CDC_VA_TOP_CSR_CORE_ID_0:
0395     case CDC_VA_TOP_CSR_CORE_ID_1:
0396     case CDC_VA_TOP_CSR_CORE_ID_2:
0397     case CDC_VA_TOP_CSR_CORE_ID_3:
0398         return true;
0399     }
0400 
0401     return va_is_rw_register(dev, reg);
0402 }
0403 
0404 static const struct regmap_config va_regmap_config = {
0405     .name = "va_macro",
0406     .reg_bits = 32,
0407     .val_bits = 32,
0408     .reg_stride = 4,
0409     .cache_type = REGCACHE_FLAT,
0410     .reg_defaults = va_defaults,
0411     .num_reg_defaults = ARRAY_SIZE(va_defaults),
0412     .max_register = VA_MAX_OFFSET,
0413     .volatile_reg = va_is_volatile_register,
0414     .readable_reg = va_is_readable_register,
0415     .writeable_reg = va_is_rw_register,
0416 };
0417 
0418 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
0419 {
0420     struct regmap *regmap = va->regmap;
0421 
0422     if (enable) {
0423         regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
0424                    CDC_VA_MCLK_CONTROL_EN,
0425                    CDC_VA_MCLK_CONTROL_EN);
0426 
0427         regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
0428                    CDC_VA_FS_CONTROL_EN,
0429                    CDC_VA_FS_CONTROL_EN);
0430 
0431         regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
0432                    CDC_VA_FS_BROADCAST_EN,
0433                    CDC_VA_FS_BROADCAST_EN);
0434     } else {
0435         regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
0436                    CDC_VA_MCLK_CONTROL_EN, 0x0);
0437 
0438         regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
0439                    CDC_VA_FS_CONTROL_EN, 0x0);
0440 
0441         regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
0442                    CDC_VA_FS_BROADCAST_EN, 0x0);
0443     }
0444 
0445     return 0;
0446 }
0447 
0448 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
0449 {
0450     struct regmap *regmap = va->regmap;
0451 
0452     if (mclk_enable) {
0453         va_clk_rsc_fs_gen_request(va, true);
0454         regcache_mark_dirty(regmap);
0455         regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
0456     } else {
0457         va_clk_rsc_fs_gen_request(va, false);
0458     }
0459 
0460     return 0;
0461 }
0462 
0463 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
0464                    struct snd_kcontrol *kcontrol, int event)
0465 {
0466     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
0467     struct va_macro *va = snd_soc_component_get_drvdata(comp);
0468 
0469     switch (event) {
0470     case SND_SOC_DAPM_PRE_PMU:
0471         return clk_prepare_enable(va->fsgen);
0472     case SND_SOC_DAPM_POST_PMD:
0473         clk_disable_unprepare(va->fsgen);
0474     }
0475 
0476     return 0;
0477 }
0478 
0479 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
0480                  struct snd_ctl_elem_value *ucontrol)
0481 {
0482     struct snd_soc_dapm_widget *widget =
0483         snd_soc_dapm_kcontrol_widget(kcontrol);
0484     struct snd_soc_component *component =
0485         snd_soc_dapm_to_component(widget->dapm);
0486     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0487     unsigned int val;
0488     u16 mic_sel_reg;
0489 
0490     val = ucontrol->value.enumerated.item[0];
0491 
0492     switch (e->reg) {
0493     case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
0494         mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
0495         break;
0496     case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
0497         mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
0498         break;
0499     case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
0500         mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
0501         break;
0502     case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
0503         mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
0504         break;
0505     default:
0506         dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
0507             __func__, e->reg);
0508         return -EINVAL;
0509     }
0510 
0511     if (val != 0)
0512         snd_soc_component_update_bits(component, mic_sel_reg,
0513                           CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
0514                           CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
0515 
0516     return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
0517 }
0518 
0519 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
0520                  struct snd_ctl_elem_value *ucontrol)
0521 {
0522     struct snd_soc_dapm_widget *widget =
0523         snd_soc_dapm_kcontrol_widget(kcontrol);
0524     struct snd_soc_component *component =
0525                 snd_soc_dapm_to_component(widget->dapm);
0526     struct soc_mixer_control *mc =
0527         (struct soc_mixer_control *)kcontrol->private_value;
0528     u32 dai_id = widget->shift;
0529     u32 dec_id = mc->shift;
0530     struct va_macro *va = snd_soc_component_get_drvdata(component);
0531 
0532     if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
0533         ucontrol->value.integer.value[0] = 1;
0534     else
0535         ucontrol->value.integer.value[0] = 0;
0536 
0537     return 0;
0538 }
0539 
0540 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
0541                  struct snd_ctl_elem_value *ucontrol)
0542 {
0543     struct snd_soc_dapm_widget *widget =
0544                     snd_soc_dapm_kcontrol_widget(kcontrol);
0545     struct snd_soc_component *component =
0546                 snd_soc_dapm_to_component(widget->dapm);
0547     struct snd_soc_dapm_update *update = NULL;
0548     struct soc_mixer_control *mc =
0549         (struct soc_mixer_control *)kcontrol->private_value;
0550     u32 dai_id = widget->shift;
0551     u32 dec_id = mc->shift;
0552     u32 enable = ucontrol->value.integer.value[0];
0553     struct va_macro *va = snd_soc_component_get_drvdata(component);
0554 
0555     if (enable) {
0556         set_bit(dec_id, &va->active_ch_mask[dai_id]);
0557         va->active_ch_cnt[dai_id]++;
0558     } else {
0559         clear_bit(dec_id, &va->active_ch_mask[dai_id]);
0560         va->active_ch_cnt[dai_id]--;
0561     }
0562 
0563     snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
0564 
0565     return 0;
0566 }
0567 
0568 static int va_dmic_clk_enable(struct snd_soc_component *component,
0569                   u32 dmic, bool enable)
0570 {
0571     struct va_macro *va = snd_soc_component_get_drvdata(component);
0572     u16 dmic_clk_reg;
0573     s32 *dmic_clk_cnt;
0574     u8 *dmic_clk_div;
0575     u8 freq_change_mask;
0576     u8 clk_div;
0577 
0578     switch (dmic) {
0579     case 0:
0580     case 1:
0581         dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
0582         dmic_clk_div = &(va->dmic_0_1_clk_div);
0583         dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
0584         freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
0585         break;
0586     case 2:
0587     case 3:
0588         dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
0589         dmic_clk_div = &(va->dmic_2_3_clk_div);
0590         dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
0591         freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
0592         break;
0593     case 4:
0594     case 5:
0595         dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
0596         dmic_clk_div = &(va->dmic_4_5_clk_div);
0597         dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
0598         freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
0599         break;
0600     case 6:
0601     case 7:
0602         dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
0603         dmic_clk_div = &(va->dmic_6_7_clk_div);
0604         dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
0605         freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
0606         break;
0607     default:
0608         dev_err(component->dev, "%s: Invalid DMIC Selection\n",
0609             __func__);
0610         return -EINVAL;
0611     }
0612 
0613     if (enable) {
0614         clk_div = va->dmic_clk_div;
0615         (*dmic_clk_cnt)++;
0616         if (*dmic_clk_cnt == 1) {
0617             snd_soc_component_update_bits(component,
0618                           CDC_VA_TOP_CSR_DMIC_CFG,
0619                           CDC_VA_RESET_ALL_DMICS_MASK,
0620                           CDC_VA_RESET_ALL_DMICS_DISABLE);
0621             snd_soc_component_update_bits(component, dmic_clk_reg,
0622                     CDC_VA_DMIC_CLK_SEL_MASK,
0623                     clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
0624             snd_soc_component_update_bits(component, dmic_clk_reg,
0625                               CDC_VA_DMIC_EN_MASK,
0626                               CDC_VA_DMIC_ENABLE);
0627         } else {
0628             if (*dmic_clk_div > clk_div) {
0629                 snd_soc_component_update_bits(component,
0630                         CDC_VA_TOP_CSR_DMIC_CFG,
0631                         freq_change_mask,
0632                         freq_change_mask);
0633                 snd_soc_component_update_bits(component, dmic_clk_reg,
0634                         CDC_VA_DMIC_CLK_SEL_MASK,
0635                         clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
0636                 snd_soc_component_update_bits(component,
0637                           CDC_VA_TOP_CSR_DMIC_CFG,
0638                           freq_change_mask,
0639                           CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
0640             } else {
0641                 clk_div = *dmic_clk_div;
0642             }
0643         }
0644         *dmic_clk_div = clk_div;
0645     } else {
0646         (*dmic_clk_cnt)--;
0647         if (*dmic_clk_cnt  == 0) {
0648             snd_soc_component_update_bits(component, dmic_clk_reg,
0649                               CDC_VA_DMIC_EN_MASK, 0);
0650             clk_div = 0;
0651             snd_soc_component_update_bits(component, dmic_clk_reg,
0652                         CDC_VA_DMIC_CLK_SEL_MASK,
0653                         clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
0654         } else {
0655             clk_div = va->dmic_clk_div;
0656             if (*dmic_clk_div > clk_div) {
0657                 clk_div = va->dmic_clk_div;
0658                 snd_soc_component_update_bits(component,
0659                             CDC_VA_TOP_CSR_DMIC_CFG,
0660                             freq_change_mask,
0661                             freq_change_mask);
0662                 snd_soc_component_update_bits(component, dmic_clk_reg,
0663                         CDC_VA_DMIC_CLK_SEL_MASK,
0664                         clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
0665                 snd_soc_component_update_bits(component,
0666                               CDC_VA_TOP_CSR_DMIC_CFG,
0667                               freq_change_mask,
0668                               CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
0669             } else {
0670                 clk_div = *dmic_clk_div;
0671             }
0672         }
0673         *dmic_clk_div = clk_div;
0674     }
0675 
0676     return 0;
0677 }
0678 
0679 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
0680                 struct snd_kcontrol *kcontrol, int event)
0681 {
0682     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
0683     unsigned int dmic = w->shift;
0684 
0685     switch (event) {
0686     case SND_SOC_DAPM_PRE_PMU:
0687         va_dmic_clk_enable(comp, dmic, true);
0688         break;
0689     case SND_SOC_DAPM_POST_PMD:
0690         va_dmic_clk_enable(comp, dmic, false);
0691         break;
0692     }
0693 
0694     return 0;
0695 }
0696 
0697 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
0698                    struct snd_kcontrol *kcontrol, int event)
0699 {
0700     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
0701     unsigned int decimator;
0702     u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
0703     u16 tx_gain_ctl_reg;
0704     u8 hpf_cut_off_freq;
0705 
0706     struct va_macro *va = snd_soc_component_get_drvdata(comp);
0707 
0708     decimator = w->shift;
0709 
0710     tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
0711                 VA_MACRO_TX_PATH_OFFSET * decimator;
0712     hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
0713                 VA_MACRO_TX_PATH_OFFSET * decimator;
0714     dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
0715                 VA_MACRO_TX_PATH_OFFSET * decimator;
0716     tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
0717                 VA_MACRO_TX_PATH_OFFSET * decimator;
0718 
0719     switch (event) {
0720     case SND_SOC_DAPM_PRE_PMU:
0721         snd_soc_component_update_bits(comp,
0722             dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
0723             va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
0724         /* Enable TX PGA Mute */
0725         break;
0726     case SND_SOC_DAPM_POST_PMU:
0727         /* Enable TX CLK */
0728         snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0729                           CDC_VA_TX_PATH_CLK_EN_MASK,
0730                           CDC_VA_TX_PATH_CLK_EN);
0731         snd_soc_component_update_bits(comp, hpf_gate_reg,
0732                           CDC_VA_TX_HPF_ZERO_GATE_MASK,
0733                           CDC_VA_TX_HPF_ZERO_GATE);
0734 
0735         usleep_range(1000, 1010);
0736         hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
0737                     TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
0738 
0739         if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
0740             snd_soc_component_update_bits(comp, dec_cfg_reg,
0741                               TX_HPF_CUT_OFF_FREQ_MASK,
0742                               CF_MIN_3DB_150HZ << 5);
0743 
0744             snd_soc_component_update_bits(comp, hpf_gate_reg,
0745                       CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
0746                       CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
0747 
0748             /*
0749              * Minimum 1 clk cycle delay is required as per HW spec
0750              */
0751             usleep_range(1000, 1010);
0752 
0753             snd_soc_component_update_bits(comp,
0754                 hpf_gate_reg,
0755                 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
0756                 0x0);
0757         }
0758 
0759 
0760         usleep_range(1000, 1010);
0761         snd_soc_component_update_bits(comp, hpf_gate_reg,
0762                           CDC_VA_TX_HPF_ZERO_GATE_MASK,
0763                           CDC_VA_TX_HPF_ZERO_NO_GATE);
0764         /*
0765          * 6ms delay is required as per HW spec
0766          */
0767         usleep_range(6000, 6010);
0768         /* apply gain after decimator is enabled */
0769         snd_soc_component_write(comp, tx_gain_ctl_reg,
0770             snd_soc_component_read(comp, tx_gain_ctl_reg));
0771         break;
0772     case SND_SOC_DAPM_POST_PMD:
0773         /* Disable TX CLK */
0774         snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0775                         CDC_VA_TX_PATH_CLK_EN_MASK,
0776                         CDC_VA_TX_PATH_CLK_DISABLE);
0777         break;
0778     }
0779     return 0;
0780 }
0781 
0782 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
0783                  struct snd_ctl_elem_value *ucontrol)
0784 {
0785     struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
0786     struct va_macro *va = snd_soc_component_get_drvdata(comp);
0787     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0788     int path = e->shift_l;
0789 
0790     ucontrol->value.enumerated.item[0] = va->dec_mode[path];
0791 
0792     return 0;
0793 }
0794 
0795 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
0796                  struct snd_ctl_elem_value *ucontrol)
0797 {
0798     struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
0799     int value = ucontrol->value.enumerated.item[0];
0800     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0801     int path = e->shift_l;
0802     struct va_macro *va = snd_soc_component_get_drvdata(comp);
0803 
0804     va->dec_mode[path] = value;
0805 
0806     return 0;
0807 }
0808 
0809 static int va_macro_hw_params(struct snd_pcm_substream *substream,
0810                   struct snd_pcm_hw_params *params,
0811                   struct snd_soc_dai *dai)
0812 {
0813     int tx_fs_rate;
0814     struct snd_soc_component *component = dai->component;
0815     u32 decimator, sample_rate;
0816     u16 tx_fs_reg;
0817     struct device *va_dev = component->dev;
0818     struct va_macro *va = snd_soc_component_get_drvdata(component);
0819 
0820     sample_rate = params_rate(params);
0821     switch (sample_rate) {
0822     case 8000:
0823         tx_fs_rate = 0;
0824         break;
0825     case 16000:
0826         tx_fs_rate = 1;
0827         break;
0828     case 32000:
0829         tx_fs_rate = 3;
0830         break;
0831     case 48000:
0832         tx_fs_rate = 4;
0833         break;
0834     case 96000:
0835         tx_fs_rate = 5;
0836         break;
0837     case 192000:
0838         tx_fs_rate = 6;
0839         break;
0840     case 384000:
0841         tx_fs_rate = 7;
0842         break;
0843     default:
0844         dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
0845             __func__, params_rate(params));
0846         return -EINVAL;
0847     }
0848 
0849     for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
0850              VA_MACRO_DEC_MAX) {
0851         tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
0852                 VA_MACRO_TX_PATH_OFFSET * decimator;
0853         snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
0854                           tx_fs_rate);
0855     }
0856     return 0;
0857 }
0858 
0859 static int va_macro_get_channel_map(struct snd_soc_dai *dai,
0860                     unsigned int *tx_num, unsigned int *tx_slot,
0861                     unsigned int *rx_num, unsigned int *rx_slot)
0862 {
0863     struct snd_soc_component *component = dai->component;
0864     struct device *va_dev = component->dev;
0865     struct va_macro *va = snd_soc_component_get_drvdata(component);
0866 
0867     switch (dai->id) {
0868     case VA_MACRO_AIF1_CAP:
0869     case VA_MACRO_AIF2_CAP:
0870     case VA_MACRO_AIF3_CAP:
0871         *tx_slot = va->active_ch_mask[dai->id];
0872         *tx_num = va->active_ch_cnt[dai->id];
0873         break;
0874     default:
0875         dev_err(va_dev, "%s: Invalid AIF\n", __func__);
0876         break;
0877     }
0878     return 0;
0879 }
0880 
0881 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
0882 {
0883     struct snd_soc_component *component = dai->component;
0884     struct va_macro *va = snd_soc_component_get_drvdata(component);
0885     u16 tx_vol_ctl_reg, decimator;
0886 
0887     for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
0888              VA_MACRO_DEC_MAX) {
0889         tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
0890                     VA_MACRO_TX_PATH_OFFSET * decimator;
0891         if (mute)
0892             snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0893                     CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
0894                     CDC_VA_TX_PATH_PGA_MUTE_EN);
0895         else
0896             snd_soc_component_update_bits(component, tx_vol_ctl_reg,
0897                     CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
0898                     CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
0899     }
0900 
0901     return 0;
0902 }
0903 
0904 static const struct snd_soc_dai_ops va_macro_dai_ops = {
0905     .hw_params = va_macro_hw_params,
0906     .get_channel_map = va_macro_get_channel_map,
0907     .mute_stream = va_macro_digital_mute,
0908 };
0909 
0910 static struct snd_soc_dai_driver va_macro_dais[] = {
0911     {
0912         .name = "va_macro_tx1",
0913         .id = VA_MACRO_AIF1_CAP,
0914         .capture = {
0915             .stream_name = "VA_AIF1 Capture",
0916             .rates = VA_MACRO_RATES,
0917             .formats = VA_MACRO_FORMATS,
0918             .rate_max = 192000,
0919             .rate_min = 8000,
0920             .channels_min = 1,
0921             .channels_max = 8,
0922         },
0923         .ops = &va_macro_dai_ops,
0924     },
0925     {
0926         .name = "va_macro_tx2",
0927         .id = VA_MACRO_AIF2_CAP,
0928         .capture = {
0929             .stream_name = "VA_AIF2 Capture",
0930             .rates = VA_MACRO_RATES,
0931             .formats = VA_MACRO_FORMATS,
0932             .rate_max = 192000,
0933             .rate_min = 8000,
0934             .channels_min = 1,
0935             .channels_max = 8,
0936         },
0937         .ops = &va_macro_dai_ops,
0938     },
0939     {
0940         .name = "va_macro_tx3",
0941         .id = VA_MACRO_AIF3_CAP,
0942         .capture = {
0943             .stream_name = "VA_AIF3 Capture",
0944             .rates = VA_MACRO_RATES,
0945             .formats = VA_MACRO_FORMATS,
0946             .rate_max = 192000,
0947             .rate_min = 8000,
0948             .channels_min = 1,
0949             .channels_max = 8,
0950         },
0951         .ops = &va_macro_dai_ops,
0952     },
0953 };
0954 
0955 static const char * const adc_mux_text[] = {
0956     "VA_DMIC", "SWR_MIC"
0957 };
0958 
0959 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
0960            0, adc_mux_text);
0961 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
0962            0, adc_mux_text);
0963 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
0964            0, adc_mux_text);
0965 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
0966            0, adc_mux_text);
0967 
0968 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
0969                                  va_dec0_enum);
0970 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
0971                                  va_dec1_enum);
0972 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
0973                                  va_dec2_enum);
0974 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
0975                                  va_dec3_enum);
0976 
0977 static const char * const dmic_mux_text[] = {
0978     "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
0979     "DMIC4", "DMIC5", "DMIC6", "DMIC7"
0980 };
0981 
0982 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
0983             4, dmic_mux_text);
0984 
0985 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
0986             4, dmic_mux_text);
0987 
0988 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
0989             4, dmic_mux_text);
0990 
0991 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
0992             4, dmic_mux_text);
0993 
0994 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
0995              va_dmic0_enum, snd_soc_dapm_get_enum_double,
0996              va_macro_put_dec_enum);
0997 
0998 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
0999              va_dmic1_enum, snd_soc_dapm_get_enum_double,
1000              va_macro_put_dec_enum);
1001 
1002 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
1003              va_dmic2_enum, snd_soc_dapm_get_enum_double,
1004              va_macro_put_dec_enum);
1005 
1006 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
1007              va_dmic3_enum, snd_soc_dapm_get_enum_double,
1008              va_macro_put_dec_enum);
1009 
1010 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
1011     SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1012             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1013     SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1014             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1015     SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1016             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1017     SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1018             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1019     SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1020             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1021     SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1022             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1023     SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1024             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1025     SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1026             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1027 };
1028 
1029 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
1030     SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1031             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1032     SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1033             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1034     SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1035             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1036     SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1037             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1038     SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1039             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1040     SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1041             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1042     SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1043             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1044     SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1045             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1046 };
1047 
1048 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
1049     SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1050             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1051     SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1052             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1053     SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1054             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1055     SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1056             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1057     SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1058             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1059     SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1060             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1061     SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1062             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1063     SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1064             va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1065 };
1066 
1067 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
1068     SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
1069         SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
1070 
1071     SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
1072         SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
1073 
1074     SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
1075         SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
1076 
1077     SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
1078         VA_MACRO_AIF1_CAP, 0,
1079         va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
1080 
1081     SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
1082         VA_MACRO_AIF2_CAP, 0,
1083         va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
1084 
1085     SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
1086         VA_MACRO_AIF3_CAP, 0,
1087         va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
1088 
1089     SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1090     SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1091     SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1092     SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1093 
1094     SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1095     SND_SOC_DAPM_INPUT("DMIC0 Pin"),
1096     SND_SOC_DAPM_INPUT("DMIC1 Pin"),
1097     SND_SOC_DAPM_INPUT("DMIC2 Pin"),
1098     SND_SOC_DAPM_INPUT("DMIC3 Pin"),
1099     SND_SOC_DAPM_INPUT("DMIC4 Pin"),
1100     SND_SOC_DAPM_INPUT("DMIC5 Pin"),
1101     SND_SOC_DAPM_INPUT("DMIC6 Pin"),
1102     SND_SOC_DAPM_INPUT("DMIC7 Pin"),
1103 
1104     SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1105         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1106         SND_SOC_DAPM_POST_PMD),
1107 
1108     SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1109         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1110         SND_SOC_DAPM_POST_PMD),
1111 
1112     SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1113         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1114         SND_SOC_DAPM_POST_PMD),
1115 
1116     SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1117         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1118         SND_SOC_DAPM_POST_PMD),
1119 
1120     SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1121         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1122         SND_SOC_DAPM_POST_PMD),
1123 
1124     SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1125         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1126         SND_SOC_DAPM_POST_PMD),
1127 
1128     SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1129         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1130         SND_SOC_DAPM_POST_PMD),
1131 
1132     SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1133         va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1134         SND_SOC_DAPM_POST_PMD),
1135 
1136     SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1137     SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1138     SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1139     SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1140     SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1141     SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1142     SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1143     SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1144     SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1145     SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1146     SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1147     SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1148 
1149     SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1150                &va_dec0_mux, va_macro_enable_dec,
1151                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1152                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1153 
1154     SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1155                &va_dec1_mux, va_macro_enable_dec,
1156                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1157                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1158 
1159     SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1160                &va_dec2_mux, va_macro_enable_dec,
1161                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1162                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1163 
1164     SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1165                &va_dec3_mux, va_macro_enable_dec,
1166                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1167                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1168 
1169     SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1170                   va_macro_mclk_event,
1171                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1172 };
1173 
1174 static const struct snd_soc_dapm_route va_audio_map[] = {
1175     {"VA_AIF1 CAP", NULL, "VA_MCLK"},
1176     {"VA_AIF2 CAP", NULL, "VA_MCLK"},
1177     {"VA_AIF3 CAP", NULL, "VA_MCLK"},
1178 
1179     {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
1180     {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
1181     {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
1182 
1183     {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1184     {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1185     {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1186     {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1187 
1188     {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1189     {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1190     {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1191     {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1192 
1193     {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1194     {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1195     {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1196     {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1197 
1198     {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1199     {"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1200     {"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1201     {"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1202     {"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1203     {"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1204     {"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1205     {"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1206     {"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1207 
1208     {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1209     {"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1210     {"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1211     {"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1212     {"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1213     {"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1214     {"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1215     {"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1216     {"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1217 
1218     {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1219     {"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1220     {"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1221     {"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1222     {"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1223     {"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1224     {"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1225     {"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1226     {"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1227 
1228     {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1229     {"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1230     {"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1231     {"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1232     {"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1233     {"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1234     {"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1235     {"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1236     {"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1237 
1238     { "VA DMIC0", NULL, "DMIC0 Pin" },
1239     { "VA DMIC1", NULL, "DMIC1 Pin" },
1240     { "VA DMIC2", NULL, "DMIC2 Pin" },
1241     { "VA DMIC3", NULL, "DMIC3 Pin" },
1242     { "VA DMIC4", NULL, "DMIC4 Pin" },
1243     { "VA DMIC5", NULL, "DMIC5 Pin" },
1244     { "VA DMIC6", NULL, "DMIC6 Pin" },
1245     { "VA DMIC7", NULL, "DMIC7 Pin" },
1246 };
1247 
1248 static const char * const dec_mode_mux_text[] = {
1249     "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1250 };
1251 
1252 static const struct soc_enum dec_mode_mux_enum[] = {
1253     SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1254             dec_mode_mux_text),
1255     SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1256             dec_mode_mux_text),
1257     SOC_ENUM_SINGLE(SND_SOC_NOPM, 2,  ARRAY_SIZE(dec_mode_mux_text),
1258             dec_mode_mux_text),
1259     SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1260             dec_mode_mux_text),
1261 };
1262 
1263 static const struct snd_kcontrol_new va_macro_snd_controls[] = {
1264     SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
1265               -84, 40, digital_gain),
1266     SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
1267               -84, 40, digital_gain),
1268     SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
1269               -84, 40, digital_gain),
1270     SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
1271               -84, 40, digital_gain),
1272 
1273     SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
1274              va_macro_dec_mode_get, va_macro_dec_mode_put),
1275     SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
1276              va_macro_dec_mode_get, va_macro_dec_mode_put),
1277     SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
1278              va_macro_dec_mode_get, va_macro_dec_mode_put),
1279     SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
1280              va_macro_dec_mode_get, va_macro_dec_mode_put),
1281 };
1282 
1283 static int va_macro_component_probe(struct snd_soc_component *component)
1284 {
1285     struct va_macro *va = snd_soc_component_get_drvdata(component);
1286 
1287     snd_soc_component_init_regmap(component, va->regmap);
1288 
1289     return 0;
1290 }
1291 
1292 static const struct snd_soc_component_driver va_macro_component_drv = {
1293     .name = "VA MACRO",
1294     .probe = va_macro_component_probe,
1295     .controls = va_macro_snd_controls,
1296     .num_controls = ARRAY_SIZE(va_macro_snd_controls),
1297     .dapm_widgets = va_macro_dapm_widgets,
1298     .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
1299     .dapm_routes = va_audio_map,
1300     .num_dapm_routes = ARRAY_SIZE(va_audio_map),
1301 };
1302 
1303 static int fsgen_gate_enable(struct clk_hw *hw)
1304 {
1305     return va_macro_mclk_enable(to_va_macro(hw), true);
1306 }
1307 
1308 static void fsgen_gate_disable(struct clk_hw *hw)
1309 {
1310     va_macro_mclk_enable(to_va_macro(hw), false);
1311 }
1312 
1313 static int fsgen_gate_is_enabled(struct clk_hw *hw)
1314 {
1315     struct va_macro *va = to_va_macro(hw);
1316     int val;
1317 
1318     regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1319 
1320     return  !!(val & CDC_VA_FS_BROADCAST_EN);
1321 }
1322 
1323 static const struct clk_ops fsgen_gate_ops = {
1324     .prepare = fsgen_gate_enable,
1325     .unprepare = fsgen_gate_disable,
1326     .is_enabled = fsgen_gate_is_enabled,
1327 };
1328 
1329 static int va_macro_register_fsgen_output(struct va_macro *va)
1330 {
1331     struct clk *parent = va->mclk;
1332     struct device *dev = va->dev;
1333     struct device_node *np = dev->of_node;
1334     const char *parent_clk_name;
1335     const char *clk_name = "fsgen";
1336     struct clk_init_data init;
1337     int ret;
1338 
1339     parent_clk_name = __clk_get_name(parent);
1340 
1341     of_property_read_string(np, "clock-output-names", &clk_name);
1342 
1343     init.name = clk_name;
1344     init.ops = &fsgen_gate_ops;
1345     init.flags = 0;
1346     init.parent_names = &parent_clk_name;
1347     init.num_parents = 1;
1348     va->hw.init = &init;
1349     ret = devm_clk_hw_register(va->dev, &va->hw);
1350     if (ret)
1351         return ret;
1352 
1353     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1354 }
1355 
1356 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
1357                           struct va_macro *va)
1358 {
1359     u32 div_factor;
1360     u32 mclk_rate = VA_MACRO_MCLK_FREQ;
1361 
1362     if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
1363         goto undefined_rate;
1364 
1365     div_factor = mclk_rate / dmic_sample_rate;
1366 
1367     switch (div_factor) {
1368     case 2:
1369         va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1370         break;
1371     case 3:
1372         va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1373         break;
1374     case 4:
1375         va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1376         break;
1377     case 6:
1378         va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1379         break;
1380     case 8:
1381         va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1382         break;
1383     case 16:
1384         va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1385         break;
1386     default:
1387         /* Any other DIV factor is invalid */
1388         goto undefined_rate;
1389     }
1390 
1391     return dmic_sample_rate;
1392 
1393 undefined_rate:
1394     dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1395         __func__, dmic_sample_rate, mclk_rate);
1396     dmic_sample_rate = 0;
1397 
1398     return dmic_sample_rate;
1399 }
1400 
1401 static int va_macro_probe(struct platform_device *pdev)
1402 {
1403     struct device *dev = &pdev->dev;
1404     struct va_macro *va;
1405     void __iomem *base;
1406     u32 sample_rate = 0;
1407     int ret;
1408 
1409     va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1410     if (!va)
1411         return -ENOMEM;
1412 
1413     va->dev = dev;
1414 
1415     va->macro = devm_clk_get_optional(dev, "macro");
1416     if (IS_ERR(va->macro))
1417         return PTR_ERR(va->macro);
1418 
1419     va->dcodec = devm_clk_get_optional(dev, "dcodec");
1420     if (IS_ERR(va->dcodec))
1421         return PTR_ERR(va->dcodec);
1422 
1423     va->mclk = devm_clk_get(dev, "mclk");
1424     if (IS_ERR(va->mclk))
1425         return PTR_ERR(va->mclk);
1426 
1427     va->pds = lpass_macro_pds_init(dev);
1428     if (IS_ERR(va->pds))
1429         return PTR_ERR(va->pds);
1430 
1431     ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1432                    &sample_rate);
1433     if (ret) {
1434         dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1435         va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1436     } else {
1437         ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1438         if (!ret) {
1439             ret = -EINVAL;
1440             goto err;
1441         }
1442     }
1443 
1444     base = devm_platform_ioremap_resource(pdev, 0);
1445     if (IS_ERR(base)) {
1446         ret = PTR_ERR(base);
1447         goto err;
1448     }
1449 
1450     va->regmap = devm_regmap_init_mmio(dev, base,  &va_regmap_config);
1451     if (IS_ERR(va->regmap)) {
1452         ret = -EINVAL;
1453         goto err;
1454     }
1455 
1456     dev_set_drvdata(dev, va);
1457 
1458     /* mclk rate */
1459     clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1460 
1461     ret = clk_prepare_enable(va->macro);
1462     if (ret)
1463         goto err;
1464 
1465     ret = clk_prepare_enable(va->dcodec);
1466     if (ret)
1467         goto err_dcodec;
1468 
1469     ret = clk_prepare_enable(va->mclk);
1470     if (ret)
1471         goto err_mclk;
1472 
1473     ret = va_macro_register_fsgen_output(va);
1474     if (ret)
1475         goto err_clkout;
1476 
1477     va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
1478     if (IS_ERR(va->fsgen)) {
1479         ret = PTR_ERR(va->fsgen);
1480         goto err_clkout;
1481     }
1482 
1483     ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
1484                           va_macro_dais,
1485                           ARRAY_SIZE(va_macro_dais));
1486     if (ret)
1487         goto err_clkout;
1488 
1489     pm_runtime_set_autosuspend_delay(dev, 3000);
1490     pm_runtime_use_autosuspend(dev);
1491     pm_runtime_mark_last_busy(dev);
1492     pm_runtime_set_active(dev);
1493     pm_runtime_enable(dev);
1494 
1495     return 0;
1496 
1497 err_clkout:
1498     clk_disable_unprepare(va->mclk);
1499 err_mclk:
1500     clk_disable_unprepare(va->dcodec);
1501 err_dcodec:
1502     clk_disable_unprepare(va->macro);
1503 err:
1504     lpass_macro_pds_exit(va->pds);
1505 
1506     return ret;
1507 }
1508 
1509 static int va_macro_remove(struct platform_device *pdev)
1510 {
1511     struct va_macro *va = dev_get_drvdata(&pdev->dev);
1512 
1513     clk_disable_unprepare(va->mclk);
1514     clk_disable_unprepare(va->dcodec);
1515     clk_disable_unprepare(va->macro);
1516 
1517     lpass_macro_pds_exit(va->pds);
1518 
1519     return 0;
1520 }
1521 
1522 static int __maybe_unused va_macro_runtime_suspend(struct device *dev)
1523 {
1524     struct va_macro *va = dev_get_drvdata(dev);
1525 
1526     regcache_cache_only(va->regmap, true);
1527     regcache_mark_dirty(va->regmap);
1528 
1529     clk_disable_unprepare(va->mclk);
1530 
1531     return 0;
1532 }
1533 
1534 static int __maybe_unused va_macro_runtime_resume(struct device *dev)
1535 {
1536     struct va_macro *va = dev_get_drvdata(dev);
1537     int ret;
1538 
1539     ret = clk_prepare_enable(va->mclk);
1540     if (ret) {
1541         dev_err(va->dev, "unable to prepare mclk\n");
1542         return ret;
1543     }
1544 
1545     regcache_cache_only(va->regmap, false);
1546     regcache_sync(va->regmap);
1547 
1548     return 0;
1549 }
1550 
1551 
1552 static const struct dev_pm_ops va_macro_pm_ops = {
1553     SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL)
1554 };
1555 
1556 static const struct of_device_id va_macro_dt_match[] = {
1557     { .compatible = "qcom,sc7280-lpass-va-macro" },
1558     { .compatible = "qcom,sm8250-lpass-va-macro" },
1559     {}
1560 };
1561 MODULE_DEVICE_TABLE(of, va_macro_dt_match);
1562 
1563 static struct platform_driver va_macro_driver = {
1564     .driver = {
1565         .name = "va_macro",
1566         .of_match_table = va_macro_dt_match,
1567         .suppress_bind_attrs = true,
1568         .pm = &va_macro_pm_ops,
1569     },
1570     .probe = va_macro_probe,
1571     .remove = va_macro_remove,
1572 };
1573 
1574 module_platform_driver(va_macro_driver);
1575 MODULE_DESCRIPTION("VA macro driver");
1576 MODULE_LICENSE("GPL");
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