0001
0002
0003
0004 #include <linux/module.h>
0005 #include <linux/init.h>
0006 #include <linux/clk.h>
0007 #include <linux/io.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pm_runtime.h>
0010 #include <linux/regmap.h>
0011 #include <sound/soc.h>
0012 #include <sound/soc-dapm.h>
0013 #include <sound/tlv.h>
0014 #include <linux/of_clk.h>
0015 #include <linux/clk-provider.h>
0016
0017 #include "lpass-macro-common.h"
0018
0019 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
0020 #define CDC_TX_MCLK_EN_MASK BIT(0)
0021 #define CDC_TX_MCLK_ENABLE BIT(0)
0022 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
0023 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
0024 #define CDC_TX_FS_CNT_ENABLE BIT(0)
0025 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
0026 #define CDC_TX_SWR_RESET_MASK BIT(1)
0027 #define CDC_TX_SWR_RESET_ENABLE BIT(1)
0028 #define CDC_TX_SWR_CLK_EN_MASK BIT(0)
0029 #define CDC_TX_SWR_CLK_ENABLE BIT(0)
0030 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
0031 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
0032 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
0033 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
0034 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
0035 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
0036 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
0037 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
0038 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
0039 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
0040 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
0041 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
0042 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
0043 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
0044 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
0045 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
0046 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
0047 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
0048 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
0049 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
0050 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
0051 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
0052 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
0053 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
0054 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
0055 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
0056 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
0057 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
0058 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
0059 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
0060 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
0061 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
0062 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
0063 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
0064 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
0065 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
0066 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
0067 #define CDC_TX_ANC0_MODE_1_CTL (0x0204)
0068 #define CDC_TX_ANC0_MODE_2_CTL (0x0208)
0069 #define CDC_TX_ANC0_FF_SHIFT (0x020C)
0070 #define CDC_TX_ANC0_FB_SHIFT (0x0210)
0071 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
0072 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
0073 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
0074 #define CDC_TX_ANC0_SMLPF_CTL (0x0220)
0075 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
0076 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
0077 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
0078 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
0079 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
0080 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
0081 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
0082 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
0083 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
0084 #define CDC_TXn_PGA_MUTE_MASK BIT(4)
0085 #define CDC_TXn_CLK_EN_MASK BIT(5)
0086 #define CDC_TX0_TX_PATH_CTL (0x0400)
0087 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
0088 #define CDC_TX0_TX_PATH_CFG0 (0x0404)
0089 #define CDC_TXn_PH_EN_MASK BIT(0)
0090 #define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
0091 #define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
0092 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
0093 #define CDC_TX0_TX_PATH_CFG1 (0x0408)
0094 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
0095 #define CDC_TX0_TX_VOL_CTL (0x040C)
0096 #define CDC_TX0_TX_PATH_SEC0 (0x0410)
0097 #define CDC_TX0_TX_PATH_SEC1 (0x0414)
0098 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
0099 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
0100 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
0101 #define CDC_TX0_TX_PATH_SEC2 (0x0418)
0102 #define CDC_TX0_TX_PATH_SEC3 (0x041C)
0103 #define CDC_TX0_TX_PATH_SEC4 (0x0420)
0104 #define CDC_TX0_TX_PATH_SEC5 (0x0424)
0105 #define CDC_TX0_TX_PATH_SEC6 (0x0428)
0106 #define CDC_TX0_TX_PATH_SEC7 (0x042C)
0107 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
0108 #define CDC_TX1_TX_PATH_CTL (0x0480)
0109 #define CDC_TX1_TX_PATH_CFG0 (0x0484)
0110 #define CDC_TX1_TX_PATH_CFG1 (0x0488)
0111 #define CDC_TX1_TX_VOL_CTL (0x048C)
0112 #define CDC_TX1_TX_PATH_SEC0 (0x0490)
0113 #define CDC_TX1_TX_PATH_SEC1 (0x0494)
0114 #define CDC_TX1_TX_PATH_SEC2 (0x0498)
0115 #define CDC_TX1_TX_PATH_SEC3 (0x049C)
0116 #define CDC_TX1_TX_PATH_SEC4 (0x04A0)
0117 #define CDC_TX1_TX_PATH_SEC5 (0x04A4)
0118 #define CDC_TX1_TX_PATH_SEC6 (0x04A8)
0119 #define CDC_TX2_TX_PATH_CTL (0x0500)
0120 #define CDC_TX2_TX_PATH_CFG0 (0x0504)
0121 #define CDC_TX2_TX_PATH_CFG1 (0x0508)
0122 #define CDC_TX2_TX_VOL_CTL (0x050C)
0123 #define CDC_TX2_TX_PATH_SEC0 (0x0510)
0124 #define CDC_TX2_TX_PATH_SEC1 (0x0514)
0125 #define CDC_TX2_TX_PATH_SEC2 (0x0518)
0126 #define CDC_TX2_TX_PATH_SEC3 (0x051C)
0127 #define CDC_TX2_TX_PATH_SEC4 (0x0520)
0128 #define CDC_TX2_TX_PATH_SEC5 (0x0524)
0129 #define CDC_TX2_TX_PATH_SEC6 (0x0528)
0130 #define CDC_TX3_TX_PATH_CTL (0x0580)
0131 #define CDC_TX3_TX_PATH_CFG0 (0x0584)
0132 #define CDC_TX3_TX_PATH_CFG1 (0x0588)
0133 #define CDC_TX3_TX_VOL_CTL (0x058C)
0134 #define CDC_TX3_TX_PATH_SEC0 (0x0590)
0135 #define CDC_TX3_TX_PATH_SEC1 (0x0594)
0136 #define CDC_TX3_TX_PATH_SEC2 (0x0598)
0137 #define CDC_TX3_TX_PATH_SEC3 (0x059C)
0138 #define CDC_TX3_TX_PATH_SEC4 (0x05A0)
0139 #define CDC_TX3_TX_PATH_SEC5 (0x05A4)
0140 #define CDC_TX3_TX_PATH_SEC6 (0x05A8)
0141 #define CDC_TX4_TX_PATH_CTL (0x0600)
0142 #define CDC_TX4_TX_PATH_CFG0 (0x0604)
0143 #define CDC_TX4_TX_PATH_CFG1 (0x0608)
0144 #define CDC_TX4_TX_VOL_CTL (0x060C)
0145 #define CDC_TX4_TX_PATH_SEC0 (0x0610)
0146 #define CDC_TX4_TX_PATH_SEC1 (0x0614)
0147 #define CDC_TX4_TX_PATH_SEC2 (0x0618)
0148 #define CDC_TX4_TX_PATH_SEC3 (0x061C)
0149 #define CDC_TX4_TX_PATH_SEC4 (0x0620)
0150 #define CDC_TX4_TX_PATH_SEC5 (0x0624)
0151 #define CDC_TX4_TX_PATH_SEC6 (0x0628)
0152 #define CDC_TX5_TX_PATH_CTL (0x0680)
0153 #define CDC_TX5_TX_PATH_CFG0 (0x0684)
0154 #define CDC_TX5_TX_PATH_CFG1 (0x0688)
0155 #define CDC_TX5_TX_VOL_CTL (0x068C)
0156 #define CDC_TX5_TX_PATH_SEC0 (0x0690)
0157 #define CDC_TX5_TX_PATH_SEC1 (0x0694)
0158 #define CDC_TX5_TX_PATH_SEC2 (0x0698)
0159 #define CDC_TX5_TX_PATH_SEC3 (0x069C)
0160 #define CDC_TX5_TX_PATH_SEC4 (0x06A0)
0161 #define CDC_TX5_TX_PATH_SEC5 (0x06A4)
0162 #define CDC_TX5_TX_PATH_SEC6 (0x06A8)
0163 #define CDC_TX6_TX_PATH_CTL (0x0700)
0164 #define CDC_TX6_TX_PATH_CFG0 (0x0704)
0165 #define CDC_TX6_TX_PATH_CFG1 (0x0708)
0166 #define CDC_TX6_TX_VOL_CTL (0x070C)
0167 #define CDC_TX6_TX_PATH_SEC0 (0x0710)
0168 #define CDC_TX6_TX_PATH_SEC1 (0x0714)
0169 #define CDC_TX6_TX_PATH_SEC2 (0x0718)
0170 #define CDC_TX6_TX_PATH_SEC3 (0x071C)
0171 #define CDC_TX6_TX_PATH_SEC4 (0x0720)
0172 #define CDC_TX6_TX_PATH_SEC5 (0x0724)
0173 #define CDC_TX6_TX_PATH_SEC6 (0x0728)
0174 #define CDC_TX7_TX_PATH_CTL (0x0780)
0175 #define CDC_TX7_TX_PATH_CFG0 (0x0784)
0176 #define CDC_TX7_TX_PATH_CFG1 (0x0788)
0177 #define CDC_TX7_TX_VOL_CTL (0x078C)
0178 #define CDC_TX7_TX_PATH_SEC0 (0x0790)
0179 #define CDC_TX7_TX_PATH_SEC1 (0x0794)
0180 #define CDC_TX7_TX_PATH_SEC2 (0x0798)
0181 #define CDC_TX7_TX_PATH_SEC3 (0x079C)
0182 #define CDC_TX7_TX_PATH_SEC4 (0x07A0)
0183 #define CDC_TX7_TX_PATH_SEC5 (0x07A4)
0184 #define CDC_TX7_TX_PATH_SEC6 (0x07A8)
0185 #define TX_MAX_OFFSET (0x07A8)
0186
0187 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0188 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
0189 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
0190 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0191 SNDRV_PCM_FMTBIT_S24_LE |\
0192 SNDRV_PCM_FMTBIT_S24_3LE)
0193
0194 #define CF_MIN_3DB_4HZ 0x0
0195 #define CF_MIN_3DB_75HZ 0x1
0196 #define CF_MIN_3DB_150HZ 0x2
0197 #define TX_ADC_MAX 5
0198 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
0199 #define NUM_DECIMATORS 8
0200 #define TX_NUM_CLKS_MAX 5
0201 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
0202 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
0203 #define TX_MACRO_DMIC_HPF_DELAY_MS 300
0204 #define TX_MACRO_AMIC_HPF_DELAY_MS 300
0205 #define MCLK_FREQ 9600000
0206
0207 enum {
0208 TX_MACRO_AIF_INVALID = 0,
0209 TX_MACRO_AIF1_CAP,
0210 TX_MACRO_AIF2_CAP,
0211 TX_MACRO_AIF3_CAP,
0212 TX_MACRO_MAX_DAIS
0213 };
0214
0215 enum {
0216 TX_MACRO_DEC0,
0217 TX_MACRO_DEC1,
0218 TX_MACRO_DEC2,
0219 TX_MACRO_DEC3,
0220 TX_MACRO_DEC4,
0221 TX_MACRO_DEC5,
0222 TX_MACRO_DEC6,
0223 TX_MACRO_DEC7,
0224 TX_MACRO_DEC_MAX,
0225 };
0226
0227 enum {
0228 TX_MACRO_CLK_DIV_2,
0229 TX_MACRO_CLK_DIV_3,
0230 TX_MACRO_CLK_DIV_4,
0231 TX_MACRO_CLK_DIV_6,
0232 TX_MACRO_CLK_DIV_8,
0233 TX_MACRO_CLK_DIV_16,
0234 };
0235
0236 enum {
0237 MSM_DMIC,
0238 SWR_MIC,
0239 ANC_FB_TUNE1
0240 };
0241
0242 struct tx_mute_work {
0243 struct tx_macro *tx;
0244 u32 decimator;
0245 struct delayed_work dwork;
0246 };
0247
0248 struct hpf_work {
0249 struct tx_macro *tx;
0250 u8 decimator;
0251 u8 hpf_cut_off_freq;
0252 struct delayed_work dwork;
0253 };
0254
0255 struct tx_macro {
0256 struct device *dev;
0257 struct snd_soc_component *component;
0258 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
0259 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
0260 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
0261 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
0262 unsigned long active_decimator[TX_MACRO_MAX_DAIS];
0263 struct regmap *regmap;
0264 struct clk *mclk;
0265 struct clk *npl;
0266 struct clk *macro;
0267 struct clk *dcodec;
0268 struct clk *fsgen;
0269 struct clk_hw hw;
0270 bool dec_active[NUM_DECIMATORS];
0271 bool reset_swr;
0272 int tx_mclk_users;
0273 u16 dmic_clk_div;
0274 bool bcs_enable;
0275 int dec_mode[NUM_DECIMATORS];
0276 struct lpass_macro *pds;
0277 bool bcs_clk_en;
0278 };
0279 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
0280
0281 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
0282
0283 static struct reg_default tx_defaults[] = {
0284
0285 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
0286 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
0287 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
0288 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
0289 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
0290 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
0291 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
0292 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
0293 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
0294 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
0295 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
0296 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
0297 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
0298 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
0299 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
0300 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
0301 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
0302 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
0303 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
0304 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
0305 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
0306 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
0307 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
0308 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
0309 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
0310 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
0311 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
0312 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
0313 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
0314 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
0315 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
0316 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
0317 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
0318 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
0319 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
0320 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
0321 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
0322 { CDC_TX_ANC0_FF_SHIFT, 0x00},
0323 { CDC_TX_ANC0_FB_SHIFT, 0x00},
0324 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
0325 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
0326 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
0327 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
0328 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
0329 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
0330 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
0331 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
0332 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
0333 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
0334 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
0335 { CDC_TX0_TX_PATH_CTL, 0x04},
0336 { CDC_TX0_TX_PATH_CFG0, 0x10},
0337 { CDC_TX0_TX_PATH_CFG1, 0x0B},
0338 { CDC_TX0_TX_VOL_CTL, 0x00},
0339 { CDC_TX0_TX_PATH_SEC0, 0x00},
0340 { CDC_TX0_TX_PATH_SEC1, 0x00},
0341 { CDC_TX0_TX_PATH_SEC2, 0x01},
0342 { CDC_TX0_TX_PATH_SEC3, 0x3C},
0343 { CDC_TX0_TX_PATH_SEC4, 0x20},
0344 { CDC_TX0_TX_PATH_SEC5, 0x00},
0345 { CDC_TX0_TX_PATH_SEC6, 0x00},
0346 { CDC_TX0_TX_PATH_SEC7, 0x25},
0347 { CDC_TX1_TX_PATH_CTL, 0x04},
0348 { CDC_TX1_TX_PATH_CFG0, 0x10},
0349 { CDC_TX1_TX_PATH_CFG1, 0x0B},
0350 { CDC_TX1_TX_VOL_CTL, 0x00},
0351 { CDC_TX1_TX_PATH_SEC0, 0x00},
0352 { CDC_TX1_TX_PATH_SEC1, 0x00},
0353 { CDC_TX1_TX_PATH_SEC2, 0x01},
0354 { CDC_TX1_TX_PATH_SEC3, 0x3C},
0355 { CDC_TX1_TX_PATH_SEC4, 0x20},
0356 { CDC_TX1_TX_PATH_SEC5, 0x00},
0357 { CDC_TX1_TX_PATH_SEC6, 0x00},
0358 { CDC_TX2_TX_PATH_CTL, 0x04},
0359 { CDC_TX2_TX_PATH_CFG0, 0x10},
0360 { CDC_TX2_TX_PATH_CFG1, 0x0B},
0361 { CDC_TX2_TX_VOL_CTL, 0x00},
0362 { CDC_TX2_TX_PATH_SEC0, 0x00},
0363 { CDC_TX2_TX_PATH_SEC1, 0x00},
0364 { CDC_TX2_TX_PATH_SEC2, 0x01},
0365 { CDC_TX2_TX_PATH_SEC3, 0x3C},
0366 { CDC_TX2_TX_PATH_SEC4, 0x20},
0367 { CDC_TX2_TX_PATH_SEC5, 0x00},
0368 { CDC_TX2_TX_PATH_SEC6, 0x00},
0369 { CDC_TX3_TX_PATH_CTL, 0x04},
0370 { CDC_TX3_TX_PATH_CFG0, 0x10},
0371 { CDC_TX3_TX_PATH_CFG1, 0x0B},
0372 { CDC_TX3_TX_VOL_CTL, 0x00},
0373 { CDC_TX3_TX_PATH_SEC0, 0x00},
0374 { CDC_TX3_TX_PATH_SEC1, 0x00},
0375 { CDC_TX3_TX_PATH_SEC2, 0x01},
0376 { CDC_TX3_TX_PATH_SEC3, 0x3C},
0377 { CDC_TX3_TX_PATH_SEC4, 0x20},
0378 { CDC_TX3_TX_PATH_SEC5, 0x00},
0379 { CDC_TX3_TX_PATH_SEC6, 0x00},
0380 { CDC_TX4_TX_PATH_CTL, 0x04},
0381 { CDC_TX4_TX_PATH_CFG0, 0x10},
0382 { CDC_TX4_TX_PATH_CFG1, 0x0B},
0383 { CDC_TX4_TX_VOL_CTL, 0x00},
0384 { CDC_TX4_TX_PATH_SEC0, 0x00},
0385 { CDC_TX4_TX_PATH_SEC1, 0x00},
0386 { CDC_TX4_TX_PATH_SEC2, 0x01},
0387 { CDC_TX4_TX_PATH_SEC3, 0x3C},
0388 { CDC_TX4_TX_PATH_SEC4, 0x20},
0389 { CDC_TX4_TX_PATH_SEC5, 0x00},
0390 { CDC_TX4_TX_PATH_SEC6, 0x00},
0391 { CDC_TX5_TX_PATH_CTL, 0x04},
0392 { CDC_TX5_TX_PATH_CFG0, 0x10},
0393 { CDC_TX5_TX_PATH_CFG1, 0x0B},
0394 { CDC_TX5_TX_VOL_CTL, 0x00},
0395 { CDC_TX5_TX_PATH_SEC0, 0x00},
0396 { CDC_TX5_TX_PATH_SEC1, 0x00},
0397 { CDC_TX5_TX_PATH_SEC2, 0x01},
0398 { CDC_TX5_TX_PATH_SEC3, 0x3C},
0399 { CDC_TX5_TX_PATH_SEC4, 0x20},
0400 { CDC_TX5_TX_PATH_SEC5, 0x00},
0401 { CDC_TX5_TX_PATH_SEC6, 0x00},
0402 { CDC_TX6_TX_PATH_CTL, 0x04},
0403 { CDC_TX6_TX_PATH_CFG0, 0x10},
0404 { CDC_TX6_TX_PATH_CFG1, 0x0B},
0405 { CDC_TX6_TX_VOL_CTL, 0x00},
0406 { CDC_TX6_TX_PATH_SEC0, 0x00},
0407 { CDC_TX6_TX_PATH_SEC1, 0x00},
0408 { CDC_TX6_TX_PATH_SEC2, 0x01},
0409 { CDC_TX6_TX_PATH_SEC3, 0x3C},
0410 { CDC_TX6_TX_PATH_SEC4, 0x20},
0411 { CDC_TX6_TX_PATH_SEC5, 0x00},
0412 { CDC_TX6_TX_PATH_SEC6, 0x00},
0413 { CDC_TX7_TX_PATH_CTL, 0x04},
0414 { CDC_TX7_TX_PATH_CFG0, 0x10},
0415 { CDC_TX7_TX_PATH_CFG1, 0x0B},
0416 { CDC_TX7_TX_VOL_CTL, 0x00},
0417 { CDC_TX7_TX_PATH_SEC0, 0x00},
0418 { CDC_TX7_TX_PATH_SEC1, 0x00},
0419 { CDC_TX7_TX_PATH_SEC2, 0x01},
0420 { CDC_TX7_TX_PATH_SEC3, 0x3C},
0421 { CDC_TX7_TX_PATH_SEC4, 0x20},
0422 { CDC_TX7_TX_PATH_SEC5, 0x00},
0423 { CDC_TX7_TX_PATH_SEC6, 0x00},
0424 };
0425
0426 static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
0427 {
0428
0429 switch (reg) {
0430 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
0431 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
0432 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
0433 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
0434 return true;
0435 }
0436 return false;
0437 }
0438
0439 static bool tx_is_rw_register(struct device *dev, unsigned int reg)
0440 {
0441 switch (reg) {
0442 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
0443 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
0444 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
0445 case CDC_TX_TOP_CSR_TOP_CFG0:
0446 case CDC_TX_TOP_CSR_ANC_CFG:
0447 case CDC_TX_TOP_CSR_SWR_CTRL:
0448 case CDC_TX_TOP_CSR_FREQ_MCLK:
0449 case CDC_TX_TOP_CSR_DEBUG_BUS:
0450 case CDC_TX_TOP_CSR_DEBUG_EN:
0451 case CDC_TX_TOP_CSR_TX_I2S_CTL:
0452 case CDC_TX_TOP_CSR_I2S_CLK:
0453 case CDC_TX_TOP_CSR_I2S_RESET:
0454 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
0455 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
0456 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
0457 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
0458 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
0459 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
0460 case CDC_TX_ANC0_CLK_RESET_CTL:
0461 case CDC_TX_ANC0_MODE_1_CTL:
0462 case CDC_TX_ANC0_MODE_2_CTL:
0463 case CDC_TX_ANC0_FF_SHIFT:
0464 case CDC_TX_ANC0_FB_SHIFT:
0465 case CDC_TX_ANC0_LPF_FF_A_CTL:
0466 case CDC_TX_ANC0_LPF_FF_B_CTL:
0467 case CDC_TX_ANC0_LPF_FB_CTL:
0468 case CDC_TX_ANC0_SMLPF_CTL:
0469 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
0470 case CDC_TX_ANC0_IIR_ADAPT_CTL:
0471 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
0472 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
0473 case CDC_TX_ANC0_FF_A_GAIN_CTL:
0474 case CDC_TX_ANC0_FF_B_GAIN_CTL:
0475 case CDC_TX_ANC0_FB_GAIN_CTL:
0476 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
0477 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
0478 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
0479 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
0480 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
0481 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
0482 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
0483 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
0484 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
0485 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
0486 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
0487 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
0488 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
0489 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
0490 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
0491 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
0492 case CDC_TX0_TX_PATH_CTL:
0493 case CDC_TX0_TX_PATH_CFG0:
0494 case CDC_TX0_TX_PATH_CFG1:
0495 case CDC_TX0_TX_VOL_CTL:
0496 case CDC_TX0_TX_PATH_SEC0:
0497 case CDC_TX0_TX_PATH_SEC1:
0498 case CDC_TX0_TX_PATH_SEC2:
0499 case CDC_TX0_TX_PATH_SEC3:
0500 case CDC_TX0_TX_PATH_SEC4:
0501 case CDC_TX0_TX_PATH_SEC5:
0502 case CDC_TX0_TX_PATH_SEC6:
0503 case CDC_TX0_TX_PATH_SEC7:
0504 case CDC_TX1_TX_PATH_CTL:
0505 case CDC_TX1_TX_PATH_CFG0:
0506 case CDC_TX1_TX_PATH_CFG1:
0507 case CDC_TX1_TX_VOL_CTL:
0508 case CDC_TX1_TX_PATH_SEC0:
0509 case CDC_TX1_TX_PATH_SEC1:
0510 case CDC_TX1_TX_PATH_SEC2:
0511 case CDC_TX1_TX_PATH_SEC3:
0512 case CDC_TX1_TX_PATH_SEC4:
0513 case CDC_TX1_TX_PATH_SEC5:
0514 case CDC_TX1_TX_PATH_SEC6:
0515 case CDC_TX2_TX_PATH_CTL:
0516 case CDC_TX2_TX_PATH_CFG0:
0517 case CDC_TX2_TX_PATH_CFG1:
0518 case CDC_TX2_TX_VOL_CTL:
0519 case CDC_TX2_TX_PATH_SEC0:
0520 case CDC_TX2_TX_PATH_SEC1:
0521 case CDC_TX2_TX_PATH_SEC2:
0522 case CDC_TX2_TX_PATH_SEC3:
0523 case CDC_TX2_TX_PATH_SEC4:
0524 case CDC_TX2_TX_PATH_SEC5:
0525 case CDC_TX2_TX_PATH_SEC6:
0526 case CDC_TX3_TX_PATH_CTL:
0527 case CDC_TX3_TX_PATH_CFG0:
0528 case CDC_TX3_TX_PATH_CFG1:
0529 case CDC_TX3_TX_VOL_CTL:
0530 case CDC_TX3_TX_PATH_SEC0:
0531 case CDC_TX3_TX_PATH_SEC1:
0532 case CDC_TX3_TX_PATH_SEC2:
0533 case CDC_TX3_TX_PATH_SEC3:
0534 case CDC_TX3_TX_PATH_SEC4:
0535 case CDC_TX3_TX_PATH_SEC5:
0536 case CDC_TX3_TX_PATH_SEC6:
0537 case CDC_TX4_TX_PATH_CTL:
0538 case CDC_TX4_TX_PATH_CFG0:
0539 case CDC_TX4_TX_PATH_CFG1:
0540 case CDC_TX4_TX_VOL_CTL:
0541 case CDC_TX4_TX_PATH_SEC0:
0542 case CDC_TX4_TX_PATH_SEC1:
0543 case CDC_TX4_TX_PATH_SEC2:
0544 case CDC_TX4_TX_PATH_SEC3:
0545 case CDC_TX4_TX_PATH_SEC4:
0546 case CDC_TX4_TX_PATH_SEC5:
0547 case CDC_TX4_TX_PATH_SEC6:
0548 case CDC_TX5_TX_PATH_CTL:
0549 case CDC_TX5_TX_PATH_CFG0:
0550 case CDC_TX5_TX_PATH_CFG1:
0551 case CDC_TX5_TX_VOL_CTL:
0552 case CDC_TX5_TX_PATH_SEC0:
0553 case CDC_TX5_TX_PATH_SEC1:
0554 case CDC_TX5_TX_PATH_SEC2:
0555 case CDC_TX5_TX_PATH_SEC3:
0556 case CDC_TX5_TX_PATH_SEC4:
0557 case CDC_TX5_TX_PATH_SEC5:
0558 case CDC_TX5_TX_PATH_SEC6:
0559 case CDC_TX6_TX_PATH_CTL:
0560 case CDC_TX6_TX_PATH_CFG0:
0561 case CDC_TX6_TX_PATH_CFG1:
0562 case CDC_TX6_TX_VOL_CTL:
0563 case CDC_TX6_TX_PATH_SEC0:
0564 case CDC_TX6_TX_PATH_SEC1:
0565 case CDC_TX6_TX_PATH_SEC2:
0566 case CDC_TX6_TX_PATH_SEC3:
0567 case CDC_TX6_TX_PATH_SEC4:
0568 case CDC_TX6_TX_PATH_SEC5:
0569 case CDC_TX6_TX_PATH_SEC6:
0570 case CDC_TX7_TX_PATH_CTL:
0571 case CDC_TX7_TX_PATH_CFG0:
0572 case CDC_TX7_TX_PATH_CFG1:
0573 case CDC_TX7_TX_VOL_CTL:
0574 case CDC_TX7_TX_PATH_SEC0:
0575 case CDC_TX7_TX_PATH_SEC1:
0576 case CDC_TX7_TX_PATH_SEC2:
0577 case CDC_TX7_TX_PATH_SEC3:
0578 case CDC_TX7_TX_PATH_SEC4:
0579 case CDC_TX7_TX_PATH_SEC5:
0580 case CDC_TX7_TX_PATH_SEC6:
0581 return true;
0582 }
0583
0584 return false;
0585 }
0586
0587 static const struct regmap_config tx_regmap_config = {
0588 .name = "tx_macro",
0589 .reg_bits = 16,
0590 .val_bits = 32,
0591 .reg_stride = 4,
0592 .cache_type = REGCACHE_FLAT,
0593 .max_register = TX_MAX_OFFSET,
0594 .reg_defaults = tx_defaults,
0595 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
0596 .writeable_reg = tx_is_rw_register,
0597 .volatile_reg = tx_is_volatile_register,
0598 .readable_reg = tx_is_rw_register,
0599 };
0600
0601 static int tx_macro_mclk_enable(struct tx_macro *tx,
0602 bool mclk_enable)
0603 {
0604 struct regmap *regmap = tx->regmap;
0605
0606 if (mclk_enable) {
0607 if (tx->tx_mclk_users == 0) {
0608
0609 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
0610 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
0611 CDC_TX_MCLK_EN_MASK,
0612 CDC_TX_MCLK_ENABLE);
0613 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
0614 CDC_TX_FS_CNT_EN_MASK,
0615 CDC_TX_FS_CNT_ENABLE);
0616 regcache_mark_dirty(regmap);
0617 regcache_sync(regmap);
0618 }
0619 tx->tx_mclk_users++;
0620 } else {
0621 if (tx->tx_mclk_users <= 0) {
0622 dev_err(tx->dev, "clock already disabled\n");
0623 tx->tx_mclk_users = 0;
0624 goto exit;
0625 }
0626 tx->tx_mclk_users--;
0627 if (tx->tx_mclk_users == 0) {
0628 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
0629 CDC_TX_FS_CNT_EN_MASK, 0x0);
0630 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
0631 CDC_TX_MCLK_EN_MASK, 0x0);
0632 }
0633 }
0634 exit:
0635 return 0;
0636 }
0637
0638 static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
0639 {
0640 u16 adc_mux_reg, adc_reg, adc_n;
0641
0642 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
0643
0644 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
0645 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
0646 adc_n = snd_soc_component_read_field(component, adc_reg,
0647 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
0648 if (adc_n < TX_ADC_MAX)
0649 return true;
0650 }
0651
0652 return false;
0653 }
0654
0655 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
0656 {
0657 struct delayed_work *hpf_delayed_work;
0658 struct hpf_work *hpf_work;
0659 struct tx_macro *tx;
0660 struct snd_soc_component *component;
0661 u16 dec_cfg_reg, hpf_gate_reg;
0662 u8 hpf_cut_off_freq;
0663
0664 hpf_delayed_work = to_delayed_work(work);
0665 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
0666 tx = hpf_work->tx;
0667 component = tx->component;
0668 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
0669
0670 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
0671 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
0672
0673 if (is_amic_enabled(component, hpf_work->decimator)) {
0674 snd_soc_component_write_field(component,
0675 dec_cfg_reg,
0676 CDC_TXn_HPF_CUT_FREQ_MASK,
0677 hpf_cut_off_freq);
0678 snd_soc_component_update_bits(component, hpf_gate_reg,
0679 CDC_TXn_HPF_F_CHANGE_MASK |
0680 CDC_TXn_HPF_ZERO_GATE_MASK,
0681 0x02);
0682 snd_soc_component_update_bits(component, hpf_gate_reg,
0683 CDC_TXn_HPF_F_CHANGE_MASK |
0684 CDC_TXn_HPF_ZERO_GATE_MASK,
0685 0x01);
0686 } else {
0687 snd_soc_component_write_field(component, dec_cfg_reg,
0688 CDC_TXn_HPF_CUT_FREQ_MASK,
0689 hpf_cut_off_freq);
0690 snd_soc_component_write_field(component, hpf_gate_reg,
0691 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
0692
0693 usleep_range(1000, 1010);
0694 snd_soc_component_write_field(component, hpf_gate_reg,
0695 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
0696 }
0697 }
0698
0699 static void tx_macro_mute_update_callback(struct work_struct *work)
0700 {
0701 struct tx_mute_work *tx_mute_dwork;
0702 struct snd_soc_component *component;
0703 struct tx_macro *tx;
0704 struct delayed_work *delayed_work;
0705 u8 decimator;
0706
0707 delayed_work = to_delayed_work(work);
0708 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
0709 tx = tx_mute_dwork->tx;
0710 component = tx->component;
0711 decimator = tx_mute_dwork->decimator;
0712
0713 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
0714 CDC_TXn_PGA_MUTE_MASK, 0x0);
0715 }
0716
0717 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
0718 struct snd_kcontrol *kcontrol, int event)
0719 {
0720 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0721 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
0722
0723 switch (event) {
0724 case SND_SOC_DAPM_PRE_PMU:
0725 tx_macro_mclk_enable(tx, true);
0726 break;
0727 case SND_SOC_DAPM_POST_PMD:
0728 tx_macro_mclk_enable(tx, false);
0729 break;
0730 default:
0731 break;
0732 }
0733
0734 return 0;
0735 }
0736
0737 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
0738 struct snd_ctl_elem_value *ucontrol)
0739 {
0740 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
0741 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
0742 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0743 unsigned int val, dmic;
0744 u16 mic_sel_reg;
0745 u16 dmic_clk_reg;
0746 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
0747
0748 val = ucontrol->value.enumerated.item[0];
0749
0750 switch (e->reg) {
0751 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
0752 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
0753 break;
0754 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
0755 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
0756 break;
0757 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
0758 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
0759 break;
0760 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
0761 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
0762 break;
0763 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
0764 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
0765 break;
0766 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
0767 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
0768 break;
0769 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
0770 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
0771 break;
0772 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
0773 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
0774 break;
0775 }
0776
0777 if (val != 0) {
0778 if (val < 5) {
0779 snd_soc_component_write_field(component, mic_sel_reg,
0780 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
0781 } else {
0782 snd_soc_component_write_field(component, mic_sel_reg,
0783 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
0784 dmic = TX_ADC_TO_DMIC(val);
0785 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
0786 snd_soc_component_write_field(component, dmic_clk_reg,
0787 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
0788 tx->dmic_clk_div);
0789 }
0790 }
0791
0792 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
0793 }
0794
0795 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
0796 struct snd_ctl_elem_value *ucontrol)
0797 {
0798 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
0799 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
0800 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
0801 u32 dai_id = widget->shift;
0802 u32 dec_id = mc->shift;
0803 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
0804
0805 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
0806 ucontrol->value.integer.value[0] = 1;
0807 else
0808 ucontrol->value.integer.value[0] = 0;
0809
0810 return 0;
0811 }
0812
0813 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
0814 struct snd_ctl_elem_value *ucontrol)
0815 {
0816 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
0817 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
0818 struct snd_soc_dapm_update *update = NULL;
0819 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
0820 u32 dai_id = widget->shift;
0821 u32 dec_id = mc->shift;
0822 u32 enable = ucontrol->value.integer.value[0];
0823 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
0824
0825 if (enable) {
0826 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
0827 tx->active_ch_cnt[dai_id]++;
0828 tx->active_decimator[dai_id] = dec_id;
0829 } else {
0830 tx->active_ch_cnt[dai_id]--;
0831 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
0832 tx->active_decimator[dai_id] = -1;
0833 }
0834 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
0835
0836 return 0;
0837 }
0838
0839 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
0840 struct snd_kcontrol *kcontrol, int event)
0841 {
0842 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0843 unsigned int decimator;
0844 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
0845 u8 hpf_cut_off_freq;
0846 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
0847 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
0848 u16 adc_mux_reg, adc_reg, adc_n, dmic;
0849 u16 dmic_clk_reg;
0850 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
0851
0852 decimator = w->shift;
0853 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
0854 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
0855 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
0856 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
0857
0858 switch (event) {
0859 case SND_SOC_DAPM_PRE_PMU:
0860 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
0861 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
0862 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
0863 adc_n = snd_soc_component_read(component, adc_reg) &
0864 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
0865 if (adc_n >= TX_ADC_MAX) {
0866 dmic = TX_ADC_TO_DMIC(adc_n);
0867 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
0868
0869 snd_soc_component_write_field(component, dmic_clk_reg,
0870 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
0871 tx->dmic_clk_div);
0872 }
0873 }
0874 snd_soc_component_write_field(component, dec_cfg_reg,
0875 CDC_TXn_ADC_MODE_MASK,
0876 tx->dec_mode[decimator]);
0877
0878 snd_soc_component_write_field(component, tx_vol_ctl_reg,
0879 CDC_TXn_PGA_MUTE_MASK, 0x1);
0880 break;
0881 case SND_SOC_DAPM_POST_PMU:
0882 snd_soc_component_write_field(component, tx_vol_ctl_reg,
0883 CDC_TXn_CLK_EN_MASK, 0x1);
0884 if (!is_amic_enabled(component, decimator)) {
0885 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
0886
0887 usleep_range(1000, 1010);
0888 }
0889 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
0890 CDC_TXn_HPF_CUT_FREQ_MASK);
0891
0892 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
0893 hpf_cut_off_freq;
0894
0895 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
0896 snd_soc_component_write_field(component, dec_cfg_reg,
0897 CDC_TXn_HPF_CUT_FREQ_MASK,
0898 CF_MIN_3DB_150HZ);
0899
0900 if (is_amic_enabled(component, decimator)) {
0901 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
0902 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
0903 }
0904
0905 queue_delayed_work(system_freezable_wq,
0906 &tx->tx_mute_dwork[decimator].dwork,
0907 msecs_to_jiffies(unmute_delay));
0908 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
0909 queue_delayed_work(system_freezable_wq,
0910 &tx->tx_hpf_work[decimator].dwork,
0911 msecs_to_jiffies(hpf_delay));
0912 snd_soc_component_update_bits(component, hpf_gate_reg,
0913 CDC_TXn_HPF_F_CHANGE_MASK |
0914 CDC_TXn_HPF_ZERO_GATE_MASK,
0915 0x02);
0916 if (!is_amic_enabled(component, decimator))
0917 snd_soc_component_update_bits(component, hpf_gate_reg,
0918 CDC_TXn_HPF_F_CHANGE_MASK |
0919 CDC_TXn_HPF_ZERO_GATE_MASK,
0920 0x00);
0921 snd_soc_component_update_bits(component, hpf_gate_reg,
0922 CDC_TXn_HPF_F_CHANGE_MASK |
0923 CDC_TXn_HPF_ZERO_GATE_MASK,
0924 0x01);
0925
0926
0927
0928
0929 usleep_range(6000, 6010);
0930 }
0931
0932 snd_soc_component_write(component, tx_gain_ctl_reg,
0933 snd_soc_component_read(component,
0934 tx_gain_ctl_reg));
0935 if (tx->bcs_enable) {
0936 snd_soc_component_update_bits(component, dec_cfg_reg,
0937 0x01, 0x01);
0938 tx->bcs_clk_en = true;
0939 }
0940 break;
0941 case SND_SOC_DAPM_PRE_PMD:
0942 hpf_cut_off_freq =
0943 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
0944 snd_soc_component_write_field(component, tx_vol_ctl_reg,
0945 CDC_TXn_PGA_MUTE_MASK, 0x1);
0946 if (cancel_delayed_work_sync(
0947 &tx->tx_hpf_work[decimator].dwork)) {
0948 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
0949 snd_soc_component_write_field(
0950 component, dec_cfg_reg,
0951 CDC_TXn_HPF_CUT_FREQ_MASK,
0952 hpf_cut_off_freq);
0953 if (is_amic_enabled(component, decimator))
0954 snd_soc_component_update_bits(component,
0955 hpf_gate_reg,
0956 CDC_TXn_HPF_F_CHANGE_MASK |
0957 CDC_TXn_HPF_ZERO_GATE_MASK,
0958 0x02);
0959 else
0960 snd_soc_component_update_bits(component,
0961 hpf_gate_reg,
0962 CDC_TXn_HPF_F_CHANGE_MASK |
0963 CDC_TXn_HPF_ZERO_GATE_MASK,
0964 0x03);
0965
0966
0967
0968
0969
0970 usleep_range(1000, 1010);
0971 snd_soc_component_update_bits(component, hpf_gate_reg,
0972 CDC_TXn_HPF_F_CHANGE_MASK |
0973 CDC_TXn_HPF_ZERO_GATE_MASK,
0974 0x1);
0975 }
0976 }
0977 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
0978 break;
0979 case SND_SOC_DAPM_POST_PMD:
0980 snd_soc_component_write_field(component, tx_vol_ctl_reg,
0981 CDC_TXn_CLK_EN_MASK, 0x0);
0982 snd_soc_component_write_field(component, dec_cfg_reg,
0983 CDC_TXn_ADC_MODE_MASK, 0x0);
0984 snd_soc_component_write_field(component, tx_vol_ctl_reg,
0985 CDC_TXn_PGA_MUTE_MASK, 0x0);
0986 if (tx->bcs_enable) {
0987 snd_soc_component_write_field(component, dec_cfg_reg,
0988 CDC_TXn_PH_EN_MASK, 0x0);
0989 snd_soc_component_write_field(component,
0990 CDC_TX0_TX_PATH_SEC7,
0991 CDC_TX0_MBHC_CTL_EN_MASK,
0992 0x0);
0993 tx->bcs_clk_en = false;
0994 }
0995 break;
0996 }
0997 return 0;
0998 }
0999
1000 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1002 {
1003 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1004 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1005 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1006 int path = e->shift_l;
1007
1008 ucontrol->value.integer.value[0] = tx->dec_mode[path];
1009
1010 return 0;
1011 }
1012
1013 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1014 struct snd_ctl_elem_value *ucontrol)
1015 {
1016 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1017 int value = ucontrol->value.integer.value[0];
1018 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1019 int path = e->shift_l;
1020 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1021
1022 tx->dec_mode[path] = value;
1023
1024 return 0;
1025 }
1026
1027 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1028 struct snd_ctl_elem_value *ucontrol)
1029 {
1030 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1031 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1032
1033 ucontrol->value.integer.value[0] = tx->bcs_enable;
1034
1035 return 0;
1036 }
1037
1038 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_value *ucontrol)
1040 {
1041 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1042 int value = ucontrol->value.integer.value[0];
1043 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1044
1045 tx->bcs_enable = value;
1046
1047 return 0;
1048 }
1049
1050 static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1051 struct snd_pcm_hw_params *params,
1052 struct snd_soc_dai *dai)
1053 {
1054 struct snd_soc_component *component = dai->component;
1055 u32 decimator, sample_rate;
1056 int tx_fs_rate;
1057 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1058
1059 sample_rate = params_rate(params);
1060 switch (sample_rate) {
1061 case 8000:
1062 tx_fs_rate = 0;
1063 break;
1064 case 16000:
1065 tx_fs_rate = 1;
1066 break;
1067 case 32000:
1068 tx_fs_rate = 3;
1069 break;
1070 case 48000:
1071 tx_fs_rate = 4;
1072 break;
1073 case 96000:
1074 tx_fs_rate = 5;
1075 break;
1076 case 192000:
1077 tx_fs_rate = 6;
1078 break;
1079 case 384000:
1080 tx_fs_rate = 7;
1081 break;
1082 default:
1083 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1084 __func__, params_rate(params));
1085 return -EINVAL;
1086 }
1087
1088 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1089 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1090 CDC_TXn_PCM_RATE_MASK,
1091 tx_fs_rate);
1092 return 0;
1093 }
1094
1095 static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1096 unsigned int *tx_num, unsigned int *tx_slot,
1097 unsigned int *rx_num, unsigned int *rx_slot)
1098 {
1099 struct snd_soc_component *component = dai->component;
1100 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1101
1102 switch (dai->id) {
1103 case TX_MACRO_AIF1_CAP:
1104 case TX_MACRO_AIF2_CAP:
1105 case TX_MACRO_AIF3_CAP:
1106 *tx_slot = tx->active_ch_mask[dai->id];
1107 *tx_num = tx->active_ch_cnt[dai->id];
1108 break;
1109 default:
1110 break;
1111 }
1112 return 0;
1113 }
1114
1115 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1116 {
1117 struct snd_soc_component *component = dai->component;
1118 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1119 u16 decimator;
1120
1121 decimator = tx->active_decimator[dai->id];
1122
1123 if (mute)
1124 snd_soc_component_write_field(component,
1125 CDC_TXn_TX_PATH_CTL(decimator),
1126 CDC_TXn_PGA_MUTE_MASK, 0x1);
1127 else
1128 snd_soc_component_update_bits(component,
1129 CDC_TXn_TX_PATH_CTL(decimator),
1130 CDC_TXn_PGA_MUTE_MASK, 0x0);
1131
1132 return 0;
1133 }
1134
1135 static const struct snd_soc_dai_ops tx_macro_dai_ops = {
1136 .hw_params = tx_macro_hw_params,
1137 .get_channel_map = tx_macro_get_channel_map,
1138 .mute_stream = tx_macro_digital_mute,
1139 };
1140
1141 static struct snd_soc_dai_driver tx_macro_dai[] = {
1142 {
1143 .name = "tx_macro_tx1",
1144 .id = TX_MACRO_AIF1_CAP,
1145 .capture = {
1146 .stream_name = "TX_AIF1 Capture",
1147 .rates = TX_MACRO_RATES,
1148 .formats = TX_MACRO_FORMATS,
1149 .rate_max = 192000,
1150 .rate_min = 8000,
1151 .channels_min = 1,
1152 .channels_max = 8,
1153 },
1154 .ops = &tx_macro_dai_ops,
1155 },
1156 {
1157 .name = "tx_macro_tx2",
1158 .id = TX_MACRO_AIF2_CAP,
1159 .capture = {
1160 .stream_name = "TX_AIF2 Capture",
1161 .rates = TX_MACRO_RATES,
1162 .formats = TX_MACRO_FORMATS,
1163 .rate_max = 192000,
1164 .rate_min = 8000,
1165 .channels_min = 1,
1166 .channels_max = 8,
1167 },
1168 .ops = &tx_macro_dai_ops,
1169 },
1170 {
1171 .name = "tx_macro_tx3",
1172 .id = TX_MACRO_AIF3_CAP,
1173 .capture = {
1174 .stream_name = "TX_AIF3 Capture",
1175 .rates = TX_MACRO_RATES,
1176 .formats = TX_MACRO_FORMATS,
1177 .rate_max = 192000,
1178 .rate_min = 8000,
1179 .channels_min = 1,
1180 .channels_max = 8,
1181 },
1182 .ops = &tx_macro_dai_ops,
1183 },
1184 };
1185
1186 static const char * const adc_mux_text[] = {
1187 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1188 };
1189
1190 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1191 0, adc_mux_text);
1192 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1193 0, adc_mux_text);
1194 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1195 0, adc_mux_text);
1196 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1197 0, adc_mux_text);
1198 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1199 0, adc_mux_text);
1200 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1201 0, adc_mux_text);
1202 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1203 0, adc_mux_text);
1204 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1205 0, adc_mux_text);
1206
1207 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1208 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1209 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1210 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1211 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1212 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1213 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1214 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1215
1216 static const char * const smic_mux_text[] = {
1217 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1218 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1219 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1220 };
1221
1222 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1223 0, smic_mux_text);
1224
1225 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1226 0, smic_mux_text);
1227
1228 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1229 0, smic_mux_text);
1230
1231 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1232 0, smic_mux_text);
1233
1234 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1235 0, smic_mux_text);
1236
1237 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1238 0, smic_mux_text);
1239
1240 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1241 0, smic_mux_text);
1242
1243 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1244 0, smic_mux_text);
1245
1246 static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1247 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1248 static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1249 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1250 static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1251 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1252 static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1253 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1254 static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1255 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1256 static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1257 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1258 static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1259 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1260 static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1261 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1262
1263 static const char * const dec_mode_mux_text[] = {
1264 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1265 };
1266
1267 static const struct soc_enum dec_mode_mux_enum[] = {
1268 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1269 dec_mode_mux_text),
1270 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1271 dec_mode_mux_text),
1272 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1273 dec_mode_mux_text),
1274 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1275 dec_mode_mux_text),
1276 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1277 dec_mode_mux_text),
1278 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1279 dec_mode_mux_text),
1280 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1281 dec_mode_mux_text),
1282 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1283 dec_mode_mux_text),
1284 };
1285
1286 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1287 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1288 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1289 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1290 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1291 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1292 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1293 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1294 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1295 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1296 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1297 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1298 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1299 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1300 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1301 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1302 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1303 };
1304
1305 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1306 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1307 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1308 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1309 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1310 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1311 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1312 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1313 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1314 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1315 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1316 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1317 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1318 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1319 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1320 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1321 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1322 };
1323
1324 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1325 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1326 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1327 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1328 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1329 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1330 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1331 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1332 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1333 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1334 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1335 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1336 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1337 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1338 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1339 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1340 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1341 };
1342
1343 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1344 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1345 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1346
1347 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1348 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1349
1350 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1351 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1352
1353 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1354 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1355
1356 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1357 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1358
1359 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1360 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1361
1362 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1363 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1364 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1365 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1366 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1367 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1368 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1369 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1370
1371 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1372 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1373 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1374 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1375 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1376 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1377 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1378 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1379 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1380 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1381 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1382 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1383
1384 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1385 TX_MACRO_DEC0, 0,
1386 &tx_dec0_mux, tx_macro_enable_dec,
1387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1388 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1389
1390 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1391 TX_MACRO_DEC1, 0,
1392 &tx_dec1_mux, tx_macro_enable_dec,
1393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1394 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1395
1396 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1397 TX_MACRO_DEC2, 0,
1398 &tx_dec2_mux, tx_macro_enable_dec,
1399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1400 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1401
1402 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1403 TX_MACRO_DEC3, 0,
1404 &tx_dec3_mux, tx_macro_enable_dec,
1405 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1406 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1407
1408 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1409 TX_MACRO_DEC4, 0,
1410 &tx_dec4_mux, tx_macro_enable_dec,
1411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1412 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1413
1414 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1415 TX_MACRO_DEC5, 0,
1416 &tx_dec5_mux, tx_macro_enable_dec,
1417 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1418 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1419
1420 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1421 TX_MACRO_DEC6, 0,
1422 &tx_dec6_mux, tx_macro_enable_dec,
1423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1424 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1425
1426 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1427 TX_MACRO_DEC7, 0,
1428 &tx_dec7_mux, tx_macro_enable_dec,
1429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1430 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1431
1432 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1433 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1434
1435 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1436
1437 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1438 NULL, 0),
1439 };
1440
1441 static const struct snd_soc_dapm_route tx_audio_map[] = {
1442 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1443 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1444 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1445
1446 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1447 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1448 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1449
1450 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1451 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1452 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1453 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1454 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1455 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1456 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1457 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1458
1459 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1460 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1461 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1462 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1463 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1464 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1465 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1466 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1467
1468 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1469 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1470 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1471 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1472 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1473 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1474 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1475 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1476
1477 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1478 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1479 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1480 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1481 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1482 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1483 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1484 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1485
1486 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1487 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1488 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1489 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1490 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1491 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1492 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1493 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1494 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1495 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1496 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1497 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1498 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1499 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1500
1501 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1502 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1503 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1504 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1505 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1506 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1507 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1508 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1509 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1510 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1511 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1512 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1513 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1514 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1515
1516 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1517 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1518 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1519 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1520 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1521 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1522 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1523 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1524 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1525 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1526 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1527 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1528 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1529 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1530
1531 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1532 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1533 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1534 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1535 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1536 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1537 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1538 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1539 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1540 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1541 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1542 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1543 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1544 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1545
1546 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1547 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1548 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1549 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1550 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1551 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1552 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1553 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1554 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1555 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1556 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1557 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1558 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1559 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1560
1561 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1562 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1563 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1564 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1565 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1566 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1567 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1568 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1569 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1570 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1571 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1572 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1573 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1574 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1575
1576 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1577 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1578 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1579 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1580 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1581 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1582 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1583 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1584 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1585 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1586 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1587 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1588 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1589 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1590
1591 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1592 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1593 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1594 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1595 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1596 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1597 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1598 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1599 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1600 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1601 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1602 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1603 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1604 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1605 };
1606
1607 static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1608 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1609 CDC_TX0_TX_VOL_CTL,
1610 -84, 40, digital_gain),
1611 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1612 CDC_TX1_TX_VOL_CTL,
1613 -84, 40, digital_gain),
1614 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1615 CDC_TX2_TX_VOL_CTL,
1616 -84, 40, digital_gain),
1617 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1618 CDC_TX3_TX_VOL_CTL,
1619 -84, 40, digital_gain),
1620 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1621 CDC_TX4_TX_VOL_CTL,
1622 -84, 40, digital_gain),
1623 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1624 CDC_TX5_TX_VOL_CTL,
1625 -84, 40, digital_gain),
1626 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1627 CDC_TX6_TX_VOL_CTL,
1628 -84, 40, digital_gain),
1629 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1630 CDC_TX7_TX_VOL_CTL,
1631 -84, 40, digital_gain),
1632
1633 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1634 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1635
1636 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1637 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1638
1639 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1640 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1641
1642 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1643 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1644
1645 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1646 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1647
1648 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1649 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1650
1651 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1652 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1653
1654 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1655 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1656
1657 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1658 tx_macro_get_bcs, tx_macro_set_bcs),
1659 };
1660
1661 static int tx_macro_component_probe(struct snd_soc_component *comp)
1662 {
1663 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1664 int i;
1665
1666 snd_soc_component_init_regmap(comp, tx->regmap);
1667
1668 for (i = 0; i < NUM_DECIMATORS; i++) {
1669 tx->tx_hpf_work[i].tx = tx;
1670 tx->tx_hpf_work[i].decimator = i;
1671 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1672 tx_macro_tx_hpf_corner_freq_callback);
1673 }
1674
1675 for (i = 0; i < NUM_DECIMATORS; i++) {
1676 tx->tx_mute_dwork[i].tx = tx;
1677 tx->tx_mute_dwork[i].decimator = i;
1678 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1679 tx_macro_mute_update_callback);
1680 }
1681 tx->component = comp;
1682
1683 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1684 0x0A);
1685
1686 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1687 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
1688
1689 return 0;
1690 }
1691
1692 static int swclk_gate_enable(struct clk_hw *hw)
1693 {
1694 struct tx_macro *tx = to_tx_macro(hw);
1695 struct regmap *regmap = tx->regmap;
1696 int ret;
1697
1698 ret = clk_prepare_enable(tx->mclk);
1699 if (ret) {
1700 dev_err(tx->dev, "failed to enable mclk\n");
1701 return ret;
1702 }
1703
1704 tx_macro_mclk_enable(tx, true);
1705 if (tx->reset_swr)
1706 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1707 CDC_TX_SWR_RESET_MASK,
1708 CDC_TX_SWR_RESET_ENABLE);
1709
1710 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1711 CDC_TX_SWR_CLK_EN_MASK,
1712 CDC_TX_SWR_CLK_ENABLE);
1713 if (tx->reset_swr)
1714 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1715 CDC_TX_SWR_RESET_MASK, 0x0);
1716 tx->reset_swr = false;
1717
1718 return 0;
1719 }
1720
1721 static void swclk_gate_disable(struct clk_hw *hw)
1722 {
1723 struct tx_macro *tx = to_tx_macro(hw);
1724 struct regmap *regmap = tx->regmap;
1725
1726 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1727 CDC_TX_SWR_CLK_EN_MASK, 0x0);
1728
1729 tx_macro_mclk_enable(tx, false);
1730 clk_disable_unprepare(tx->mclk);
1731 }
1732
1733 static int swclk_gate_is_enabled(struct clk_hw *hw)
1734 {
1735 struct tx_macro *tx = to_tx_macro(hw);
1736 int ret, val;
1737
1738 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1739 ret = val & BIT(0);
1740
1741 return ret;
1742 }
1743
1744 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1745 unsigned long parent_rate)
1746 {
1747 return parent_rate / 2;
1748 }
1749
1750 static const struct clk_ops swclk_gate_ops = {
1751 .prepare = swclk_gate_enable,
1752 .unprepare = swclk_gate_disable,
1753 .is_enabled = swclk_gate_is_enabled,
1754 .recalc_rate = swclk_recalc_rate,
1755
1756 };
1757
1758 static int tx_macro_register_mclk_output(struct tx_macro *tx)
1759 {
1760 struct device *dev = tx->dev;
1761 const char *parent_clk_name = NULL;
1762 const char *clk_name = "lpass-tx-mclk";
1763 struct clk_hw *hw;
1764 struct clk_init_data init;
1765 int ret;
1766
1767 parent_clk_name = __clk_get_name(tx->npl);
1768
1769 init.name = clk_name;
1770 init.ops = &swclk_gate_ops;
1771 init.flags = 0;
1772 init.parent_names = &parent_clk_name;
1773 init.num_parents = 1;
1774 tx->hw.init = &init;
1775 hw = &tx->hw;
1776 ret = devm_clk_hw_register(dev, hw);
1777 if (ret)
1778 return ret;
1779
1780 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
1781 }
1782
1783 static const struct snd_soc_component_driver tx_macro_component_drv = {
1784 .name = "RX-MACRO",
1785 .probe = tx_macro_component_probe,
1786 .controls = tx_macro_snd_controls,
1787 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
1788 .dapm_widgets = tx_macro_dapm_widgets,
1789 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1790 .dapm_routes = tx_audio_map,
1791 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
1792 };
1793
1794 static int tx_macro_probe(struct platform_device *pdev)
1795 {
1796 struct device *dev = &pdev->dev;
1797 struct device_node *np = dev->of_node;
1798 struct tx_macro *tx;
1799 void __iomem *base;
1800 int ret, reg;
1801
1802 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1803 if (!tx)
1804 return -ENOMEM;
1805
1806 tx->macro = devm_clk_get_optional(dev, "macro");
1807 if (IS_ERR(tx->macro))
1808 return PTR_ERR(tx->macro);
1809
1810 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1811 if (IS_ERR(tx->dcodec))
1812 return PTR_ERR(tx->dcodec);
1813
1814 tx->mclk = devm_clk_get(dev, "mclk");
1815 if (IS_ERR(tx->mclk))
1816 return PTR_ERR(tx->mclk);
1817
1818 tx->npl = devm_clk_get(dev, "npl");
1819 if (IS_ERR(tx->npl))
1820 return PTR_ERR(tx->npl);
1821
1822 tx->fsgen = devm_clk_get(dev, "fsgen");
1823 if (IS_ERR(tx->fsgen))
1824 return PTR_ERR(tx->fsgen);
1825
1826 tx->pds = lpass_macro_pds_init(dev);
1827 if (IS_ERR(tx->pds))
1828 return PTR_ERR(tx->pds);
1829
1830 base = devm_platform_ioremap_resource(pdev, 0);
1831 if (IS_ERR(base)) {
1832 ret = PTR_ERR(base);
1833 goto err;
1834 }
1835
1836
1837 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
1838 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
1839 switch (tx_defaults[reg].reg) {
1840 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
1841 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
1842 tx_defaults[reg].def = 0x0E;
1843 break;
1844 default:
1845 break;
1846 }
1847 }
1848 }
1849
1850 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
1851 if (IS_ERR(tx->regmap)) {
1852 ret = PTR_ERR(tx->regmap);
1853 goto err;
1854 }
1855
1856 dev_set_drvdata(dev, tx);
1857
1858 tx->reset_swr = true;
1859 tx->dev = dev;
1860
1861
1862 clk_set_rate(tx->mclk, MCLK_FREQ);
1863 clk_set_rate(tx->npl, 2 * MCLK_FREQ);
1864
1865 ret = clk_prepare_enable(tx->macro);
1866 if (ret)
1867 goto err;
1868
1869 ret = clk_prepare_enable(tx->dcodec);
1870 if (ret)
1871 goto err_dcodec;
1872
1873 ret = clk_prepare_enable(tx->mclk);
1874 if (ret)
1875 goto err_mclk;
1876
1877 ret = clk_prepare_enable(tx->npl);
1878 if (ret)
1879 goto err_npl;
1880
1881 ret = clk_prepare_enable(tx->fsgen);
1882 if (ret)
1883 goto err_fsgen;
1884
1885 ret = tx_macro_register_mclk_output(tx);
1886 if (ret)
1887 goto err_clkout;
1888
1889 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
1890 tx_macro_dai,
1891 ARRAY_SIZE(tx_macro_dai));
1892 if (ret)
1893 goto err_clkout;
1894
1895 pm_runtime_set_autosuspend_delay(dev, 3000);
1896 pm_runtime_use_autosuspend(dev);
1897 pm_runtime_mark_last_busy(dev);
1898 pm_runtime_set_active(dev);
1899 pm_runtime_enable(dev);
1900
1901 return 0;
1902
1903 err_clkout:
1904 clk_disable_unprepare(tx->fsgen);
1905 err_fsgen:
1906 clk_disable_unprepare(tx->npl);
1907 err_npl:
1908 clk_disable_unprepare(tx->mclk);
1909 err_mclk:
1910 clk_disable_unprepare(tx->dcodec);
1911 err_dcodec:
1912 clk_disable_unprepare(tx->macro);
1913 err:
1914 lpass_macro_pds_exit(tx->pds);
1915
1916 return ret;
1917 }
1918
1919 static int tx_macro_remove(struct platform_device *pdev)
1920 {
1921 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
1922
1923 clk_disable_unprepare(tx->macro);
1924 clk_disable_unprepare(tx->dcodec);
1925 clk_disable_unprepare(tx->mclk);
1926 clk_disable_unprepare(tx->npl);
1927 clk_disable_unprepare(tx->fsgen);
1928
1929 lpass_macro_pds_exit(tx->pds);
1930
1931 return 0;
1932 }
1933
1934 static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
1935 {
1936 struct tx_macro *tx = dev_get_drvdata(dev);
1937
1938 regcache_cache_only(tx->regmap, true);
1939 regcache_mark_dirty(tx->regmap);
1940
1941 clk_disable_unprepare(tx->mclk);
1942 clk_disable_unprepare(tx->npl);
1943 clk_disable_unprepare(tx->fsgen);
1944
1945 return 0;
1946 }
1947
1948 static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
1949 {
1950 struct tx_macro *tx = dev_get_drvdata(dev);
1951 int ret;
1952
1953 ret = clk_prepare_enable(tx->mclk);
1954 if (ret) {
1955 dev_err(dev, "unable to prepare mclk\n");
1956 return ret;
1957 }
1958
1959 ret = clk_prepare_enable(tx->npl);
1960 if (ret) {
1961 dev_err(dev, "unable to prepare npl\n");
1962 goto err_npl;
1963 }
1964
1965 ret = clk_prepare_enable(tx->fsgen);
1966 if (ret) {
1967 dev_err(dev, "unable to prepare fsgen\n");
1968 goto err_fsgen;
1969 }
1970
1971 regcache_cache_only(tx->regmap, false);
1972 regcache_sync(tx->regmap);
1973 tx->reset_swr = true;
1974
1975 return 0;
1976 err_fsgen:
1977 clk_disable_unprepare(tx->npl);
1978 err_npl:
1979 clk_disable_unprepare(tx->mclk);
1980
1981 return ret;
1982 }
1983
1984 static const struct dev_pm_ops tx_macro_pm_ops = {
1985 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
1986 };
1987
1988 static const struct of_device_id tx_macro_dt_match[] = {
1989 { .compatible = "qcom,sc7280-lpass-tx-macro" },
1990 { .compatible = "qcom,sm8250-lpass-tx-macro" },
1991 { }
1992 };
1993 MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
1994 static struct platform_driver tx_macro_driver = {
1995 .driver = {
1996 .name = "tx_macro",
1997 .of_match_table = tx_macro_dt_match,
1998 .suppress_bind_attrs = true,
1999 .pm = &tx_macro_pm_ops,
2000 },
2001 .probe = tx_macro_probe,
2002 .remove = tx_macro_remove,
2003 };
2004
2005 module_platform_driver(tx_macro_driver);
2006
2007 MODULE_DESCRIPTION("TX macro driver");
2008 MODULE_LICENSE("GPL");
