0001
0002
0003
0004
0005
0006
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/slab.h>
0011 #include <linux/io.h>
0012 #include <linux/regmap.h>
0013
0014 #include <linux/delay.h>
0015
0016 #include <sound/core.h>
0017 #include <sound/pcm.h>
0018 #include <sound/pcm_params.h>
0019 #include <sound/initval.h>
0020 #include <sound/soc.h>
0021 #include <sound/tlv.h>
0022
0023 #define JZ4740_REG_CODEC_1 0x0
0024 #define JZ4740_REG_CODEC_2 0x4
0025
0026 #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
0027 #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
0028 #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
0029 #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
0030 #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
0031 #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
0032 #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
0033 #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
0034 #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
0035 #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
0036 #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
0037 #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
0038 #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
0039 #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
0040 #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
0041 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
0042 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
0043 #define JZ4740_CODEC_1_SUSPEND BIT(1)
0044 #define JZ4740_CODEC_1_RESET BIT(0)
0045
0046 #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
0047 #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
0048 #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
0049 #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
0050 #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
0051 #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
0052 #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
0053 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
0054
0055 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
0056 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
0057 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
0058 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
0059
0060 #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
0061 #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
0062 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
0063 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
0064
0065 static const struct reg_default jz4740_codec_reg_defaults[] = {
0066 { JZ4740_REG_CODEC_1, 0x021b2302 },
0067 { JZ4740_REG_CODEC_2, 0x00170803 },
0068 };
0069
0070 struct jz4740_codec {
0071 struct regmap *regmap;
0072 };
0073
0074 static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
0075 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
0076 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
0077 );
0078
0079 static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
0080 static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
0081
0082 static const struct snd_kcontrol_new jz4740_codec_controls[] = {
0083 SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
0084 JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
0085 jz4740_out_tlv),
0086 SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
0087 JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
0088 jz4740_in_tlv),
0089 SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
0090 JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
0091 SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
0092 JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
0093 jz4740_mic_tlv),
0094 };
0095
0096 static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
0097 SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
0098 JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
0099 SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
0100 JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
0101 };
0102
0103 static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
0104 SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
0105 JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
0106 SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
0107 JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
0108 };
0109
0110 static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
0111 SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
0112 JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
0113 SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
0114 JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
0115
0116 SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
0117 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
0118 jz4740_codec_output_controls,
0119 ARRAY_SIZE(jz4740_codec_output_controls)),
0120
0121 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
0122 jz4740_codec_input_controls,
0123 ARRAY_SIZE(jz4740_codec_input_controls)),
0124 SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
0125
0126 SND_SOC_DAPM_OUTPUT("LOUT"),
0127 SND_SOC_DAPM_OUTPUT("ROUT"),
0128
0129 SND_SOC_DAPM_INPUT("MIC"),
0130 SND_SOC_DAPM_INPUT("LIN"),
0131 SND_SOC_DAPM_INPUT("RIN"),
0132 };
0133
0134 static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
0135 {"Line Input", NULL, "LIN"},
0136 {"Line Input", NULL, "RIN"},
0137
0138 {"Input Mixer", "Line Capture Switch", "Line Input"},
0139 {"Input Mixer", "Mic Capture Switch", "MIC"},
0140
0141 {"ADC", NULL, "Input Mixer"},
0142
0143 {"Output Mixer", "Bypass Switch", "Input Mixer"},
0144 {"Output Mixer", "DAC Switch", "DAC"},
0145
0146 {"LOUT", NULL, "Output Mixer"},
0147 {"ROUT", NULL, "Output Mixer"},
0148 };
0149
0150 static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
0151 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0152 {
0153 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
0154 uint32_t val;
0155
0156 switch (params_rate(params)) {
0157 case 8000:
0158 val = 0;
0159 break;
0160 case 11025:
0161 val = 1;
0162 break;
0163 case 12000:
0164 val = 2;
0165 break;
0166 case 16000:
0167 val = 3;
0168 break;
0169 case 22050:
0170 val = 4;
0171 break;
0172 case 24000:
0173 val = 5;
0174 break;
0175 case 32000:
0176 val = 6;
0177 break;
0178 case 44100:
0179 val = 7;
0180 break;
0181 case 48000:
0182 val = 8;
0183 break;
0184 default:
0185 return -EINVAL;
0186 }
0187
0188 val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
0189
0190 regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
0191 JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
0192
0193 return 0;
0194 }
0195
0196 static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
0197 .hw_params = jz4740_codec_hw_params,
0198 };
0199
0200 static struct snd_soc_dai_driver jz4740_codec_dai = {
0201 .name = "jz4740-hifi",
0202 .playback = {
0203 .stream_name = "Playback",
0204 .channels_min = 2,
0205 .channels_max = 2,
0206 .rates = SNDRV_PCM_RATE_8000_48000,
0207 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
0208 },
0209 .capture = {
0210 .stream_name = "Capture",
0211 .channels_min = 2,
0212 .channels_max = 2,
0213 .rates = SNDRV_PCM_RATE_8000_48000,
0214 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
0215 },
0216 .ops = &jz4740_codec_dai_ops,
0217 .symmetric_rate = 1,
0218 };
0219
0220 static void jz4740_codec_wakeup(struct regmap *regmap)
0221 {
0222 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, JZ4740_CODEC_1_RESET);
0223 udelay(2);
0224
0225 regmap_clear_bits(regmap, JZ4740_REG_CODEC_1,
0226 JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET);
0227
0228 regcache_sync(regmap);
0229 }
0230
0231 static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
0232 enum snd_soc_bias_level level)
0233 {
0234 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
0235 struct regmap *regmap = jz4740_codec->regmap;
0236 unsigned int mask;
0237
0238 switch (level) {
0239 case SND_SOC_BIAS_ON:
0240 break;
0241 case SND_SOC_BIAS_PREPARE:
0242 mask = JZ4740_CODEC_1_VREF_DISABLE |
0243 JZ4740_CODEC_1_VREF_AMP_DISABLE |
0244 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
0245
0246 regmap_clear_bits(regmap, JZ4740_REG_CODEC_1, mask);
0247 break;
0248 case SND_SOC_BIAS_STANDBY:
0249
0250 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
0251 jz4740_codec_wakeup(regmap);
0252
0253 mask = JZ4740_CODEC_1_VREF_DISABLE |
0254 JZ4740_CODEC_1_VREF_AMP_DISABLE |
0255 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
0256
0257 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
0258 break;
0259 case SND_SOC_BIAS_OFF:
0260 mask = JZ4740_CODEC_1_SUSPEND;
0261 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask);
0262 regcache_mark_dirty(regmap);
0263 break;
0264 default:
0265 break;
0266 }
0267
0268 return 0;
0269 }
0270
0271 static int jz4740_codec_dev_probe(struct snd_soc_component *component)
0272 {
0273 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
0274
0275 regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
0276 JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
0277
0278 return 0;
0279 }
0280
0281 static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
0282 .probe = jz4740_codec_dev_probe,
0283 .set_bias_level = jz4740_codec_set_bias_level,
0284 .controls = jz4740_codec_controls,
0285 .num_controls = ARRAY_SIZE(jz4740_codec_controls),
0286 .dapm_widgets = jz4740_codec_dapm_widgets,
0287 .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
0288 .dapm_routes = jz4740_codec_dapm_routes,
0289 .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
0290 .suspend_bias_off = 1,
0291 .idle_bias_on = 1,
0292 .use_pmdown_time = 1,
0293 .endianness = 1,
0294 };
0295
0296 static const struct regmap_config jz4740_codec_regmap_config = {
0297 .reg_bits = 32,
0298 .reg_stride = 4,
0299 .val_bits = 32,
0300 .max_register = JZ4740_REG_CODEC_2,
0301
0302 .reg_defaults = jz4740_codec_reg_defaults,
0303 .num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
0304 .cache_type = REGCACHE_RBTREE,
0305 };
0306
0307 static int jz4740_codec_probe(struct platform_device *pdev)
0308 {
0309 int ret;
0310 struct jz4740_codec *jz4740_codec;
0311 void __iomem *base;
0312
0313 jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
0314 GFP_KERNEL);
0315 if (!jz4740_codec)
0316 return -ENOMEM;
0317
0318 base = devm_platform_ioremap_resource(pdev, 0);
0319 if (IS_ERR(base))
0320 return PTR_ERR(base);
0321
0322 jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
0323 &jz4740_codec_regmap_config);
0324 if (IS_ERR(jz4740_codec->regmap))
0325 return PTR_ERR(jz4740_codec->regmap);
0326
0327 platform_set_drvdata(pdev, jz4740_codec);
0328
0329 ret = devm_snd_soc_register_component(&pdev->dev,
0330 &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
0331 if (ret)
0332 dev_err(&pdev->dev, "Failed to register codec\n");
0333
0334 return ret;
0335 }
0336
0337 static const struct of_device_id jz4740_codec_of_matches[] = {
0338 { .compatible = "ingenic,jz4740-codec", },
0339 { }
0340 };
0341 MODULE_DEVICE_TABLE(of, jz4740_codec_of_matches);
0342
0343 static struct platform_driver jz4740_codec_driver = {
0344 .probe = jz4740_codec_probe,
0345 .driver = {
0346 .name = "jz4740-codec",
0347 .of_match_table = jz4740_codec_of_matches,
0348 },
0349 };
0350
0351 module_platform_driver(jz4740_codec_driver);
0352
0353 MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
0354 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0355 MODULE_LICENSE("GPL v2");
0356 MODULE_ALIAS("platform:jz4740-codec");
