soc/codecs/inno_rk3036.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Driver of Inno Codec for rk3036 by Rockchip Inc.
0004  *
0005  * Author: Zheng ShunQian<zhengsq@rock-chips.com>
0006  */
0007
0008 #ifndef _INNO_RK3036_CODEC_H
0009 #define _INNO_RK3036_CODEC_H
0010
0011 /* codec registers */
0012 #define INNO_R00    0x00
0013 #define INNO_R01    0x0c
0014 #define INNO_R02    0x10
0015 #define INNO_R03    0x14
0016 #define INNO_R04    0x88
0017 #define INNO_R05    0x8c
0018 #define INNO_R06    0x90
0019 #define INNO_R07    0x94
0020 #define INNO_R08    0x98
0021 #define INNO_R09    0x9c
0022 #define INNO_R10    0xa0
0023
0024 /* register bit filed */
0025 #define INNO_R00_CSR_RESET      (0x0 << 0) /*codec system reset*/
0026 #define INNO_R00_CSR_WORK       (0x1 << 0)
0027 #define INNO_R00_CDCR_RESET     (0x0 << 1) /*codec digital core reset*/
0028 #define INNO_R00_CDCR_WORK      (0x1 << 1)
0029 #define INNO_R00_PRB_DISABLE        (0x0 << 6) /*power reset bypass*/
0030 #define INNO_R00_PRB_ENABLE     (0x1 << 6)
0031
0032 #define INNO_R01_I2SMODE_MSK        (0x1 << 4)
0033 #define INNO_R01_I2SMODE_SLAVE      (0x0 << 4)
0034 #define INNO_R01_I2SMODE_MASTER     (0x1 << 4)
0035 #define INNO_R01_PINDIR_MSK     (0x1 << 5)
0036 #define INNO_R01_PINDIR_IN_SLAVE    (0x0 << 5) /*direction of pin*/
0037 #define INNO_R01_PINDIR_OUT_MASTER  (0x1 << 5)
0038
0039 #define INNO_R02_LRS_MSK        (0x1 << 2)
0040 #define INNO_R02_LRS_NORMAL     (0x0 << 2) /*DAC Left Right Swap*/
0041 #define INNO_R02_LRS_SWAP       (0x1 << 2)
0042 #define INNO_R02_DACM_MSK       (0x3 << 3)
0043 #define INNO_R02_DACM_PCM       (0x3 << 3) /*DAC Mode*/
0044 #define INNO_R02_DACM_I2S       (0x2 << 3)
0045 #define INNO_R02_DACM_LJM       (0x1 << 3)
0046 #define INNO_R02_DACM_RJM       (0x0 << 3)
0047 #define INNO_R02_VWL_MSK        (0x3 << 5)
0048 #define INNO_R02_VWL_32BIT      (0x3 << 5) /*1/2Frame Valid Word Len*/
0049 #define INNO_R02_VWL_24BIT      (0x2 << 5)
0050 #define INNO_R02_VWL_20BIT      (0x1 << 5)
0051 #define INNO_R02_VWL_16BIT      (0x0 << 5)
0052 #define INNO_R02_LRCP_MSK       (0x1 << 7)
0053 #define INNO_R02_LRCP_NORMAL        (0x0 << 7) /*Left Right Polarity*/
0054 #define INNO_R02_LRCP_REVERSAL      (0x1 << 7)
0055
0056 #define INNO_R03_BCP_MSK        (0x1 << 0)
0057 #define INNO_R03_BCP_NORMAL     (0x0 << 0) /*DAC bit clock polarity*/
0058 #define INNO_R03_BCP_REVERSAL       (0x1 << 0)
0059 #define INNO_R03_DACR_MSK       (0x1 << 1)
0060 #define INNO_R03_DACR_RESET     (0x0 << 1) /*DAC Reset*/
0061 #define INNO_R03_DACR_WORK      (0x1 << 1)
0062 #define INNO_R03_FWL_MSK        (0x3 << 2)
0063 #define INNO_R03_FWL_32BIT      (0x3 << 2) /*1/2Frame Word Length*/
0064 #define INNO_R03_FWL_24BIT      (0x2 << 2)
0065 #define INNO_R03_FWL_20BIT      (0x1 << 2)
0066 #define INNO_R03_FWL_16BIT      (0x0 << 2)
0067
0068 #define INNO_R04_DACR_SW_SHIFT      0
0069 #define INNO_R04_DACL_SW_SHIFT      1
0070 #define INNO_R04_DACR_CLK_SHIFT     2
0071 #define INNO_R04_DACL_CLK_SHIFT     3
0072 #define INNO_R04_DACR_VREF_SHIFT    4
0073 #define INNO_R04_DACL_VREF_SHIFT    5
0074
0075 #define INNO_R05_HPR_EN_SHIFT       0
0076 #define INNO_R05_HPL_EN_SHIFT       1
0077 #define INNO_R05_HPR_WORK_SHIFT     2
0078 #define INNO_R05_HPL_WORK_SHIFT     3
0079
0080 #define INNO_R06_VOUTR_CZ_SHIFT     0
0081 #define INNO_R06_VOUTL_CZ_SHIFT     1
0082 #define INNO_R06_DACR_HILO_VREF_SHIFT   2
0083 #define INNO_R06_DACL_HILO_VREF_SHIFT   3
0084 #define INNO_R06_DAC_EN_SHIFT       5
0085
0086 #define INNO_R06_DAC_PRECHARGE      (0x0 << 4) /*PreCharge control for DAC*/
0087 #define INNO_R06_DAC_DISCHARGE      (0x1 << 4)
0088
0089 #define INNO_HP_GAIN_SHIFT      0
0090 /* Gain of output, 1.5db step: -39db(0x0) ~ 0db(0x1a) ~ 6db(0x1f) */
0091 #define INNO_HP_GAIN_0DB        0x1a
0092 #define INNO_HP_GAIN_N39DB      0x0
0093
0094 #define INNO_R09_HP_ANTIPOP_MSK     0x3
0095 #define INNO_R09_HP_ANTIPOP_OFF     0x1
0096 #define INNO_R09_HP_ANTIPOP_ON      0x2
0097 #define INNO_R09_HPR_ANITPOP_SHIFT  0
0098 #define INNO_R09_HPL_ANITPOP_SHIFT  2
0099 #define INNO_R09_HPR_MUTE_SHIFT     4
0100 #define INNO_R09_HPL_MUTE_SHIFT     5
0101 #define INNO_R09_DACR_SWITCH_SHIFT  6
0102 #define INNO_R09_DACL_SWITCH_SHIFT  7
0103
0104 #define INNO_R10_CHARGE_SEL_CUR_400I_YES    (0x0 << 0)
0105 #define INNO_R10_CHARGE_SEL_CUR_400I_NO     (0x1 << 0)
0106 #define INNO_R10_CHARGE_SEL_CUR_260I_YES    (0x0 << 1)
0107 #define INNO_R10_CHARGE_SEL_CUR_260I_NO     (0x1 << 1)
0108 #define INNO_R10_CHARGE_SEL_CUR_130I_YES    (0x0 << 2)
0109 #define INNO_R10_CHARGE_SEL_CUR_130I_NO     (0x1 << 2)
0110 #define INNO_R10_CHARGE_SEL_CUR_100I_YES    (0x0 << 3)
0111 #define INNO_R10_CHARGE_SEL_CUR_100I_NO     (0x1 << 3)
0112 #define INNO_R10_CHARGE_SEL_CUR_050I_YES    (0x0 << 4)
0113 #define INNO_R10_CHARGE_SEL_CUR_050I_NO     (0x1 << 4)
0114 #define INNO_R10_CHARGE_SEL_CUR_027I_YES    (0x0 << 5)
0115 #define INNO_R10_CHARGE_SEL_CUR_027I_NO     (0x1 << 5)
0116
0117 #define INNO_R10_MAX_CUR (INNO_R10_CHARGE_SEL_CUR_400I_YES | \
0118               INNO_R10_CHARGE_SEL_CUR_260I_YES | \
0119               INNO_R10_CHARGE_SEL_CUR_130I_YES | \
0120               INNO_R10_CHARGE_SEL_CUR_100I_YES | \
0121               INNO_R10_CHARGE_SEL_CUR_050I_YES | \
0122               INNO_R10_CHARGE_SEL_CUR_027I_YES)
0123
0124 #endif