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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * es8328.c  --  ES8328 ALSA SoC Audio driver
0004  *
0005  * Copyright 2014 Sutajio Ko-Usagi PTE LTD
0006  *
0007  * Author: Sean Cross <xobs@kosagi.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/of_device.h>
0013 #include <linux/module.h>
0014 #include <linux/pm.h>
0015 #include <linux/regmap.h>
0016 #include <linux/slab.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <sound/core.h>
0019 #include <sound/initval.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/tlv.h>
0024 #include "es8328.h"
0025 
0026 static const unsigned int rates_12288[] = {
0027     8000, 12000, 16000, 24000, 32000, 48000, 96000,
0028 };
0029 
0030 static const int ratios_12288[] = {
0031     10, 7, 6, 4, 3, 2, 0,
0032 };
0033 
0034 static const struct snd_pcm_hw_constraint_list constraints_12288 = {
0035     .count  = ARRAY_SIZE(rates_12288),
0036     .list   = rates_12288,
0037 };
0038 
0039 static const unsigned int rates_11289[] = {
0040     8018, 11025, 22050, 44100, 88200,
0041 };
0042 
0043 static const int ratios_11289[] = {
0044     9, 7, 4, 2, 0,
0045 };
0046 
0047 static const struct snd_pcm_hw_constraint_list constraints_11289 = {
0048     .count  = ARRAY_SIZE(rates_11289),
0049     .list   = rates_11289,
0050 };
0051 
0052 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
0053 enum sgtl5000_regulator_supplies {
0054     DVDD,
0055     AVDD,
0056     PVDD,
0057     HPVDD,
0058     ES8328_SUPPLY_NUM
0059 };
0060 
0061 /* vddd is optional supply */
0062 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
0063     "DVDD",
0064     "AVDD",
0065     "PVDD",
0066     "HPVDD",
0067 };
0068 
0069 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
0070         SNDRV_PCM_RATE_96000 | \
0071         SNDRV_PCM_RATE_88200 | \
0072         SNDRV_PCM_RATE_8000_48000)
0073 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0074         SNDRV_PCM_FMTBIT_S18_3LE | \
0075         SNDRV_PCM_FMTBIT_S20_3LE | \
0076         SNDRV_PCM_FMTBIT_S24_LE | \
0077         SNDRV_PCM_FMTBIT_S32_LE)
0078 
0079 struct es8328_priv {
0080     struct regmap *regmap;
0081     struct clk *clk;
0082     int playback_fs;
0083     bool deemph;
0084     int mclkdiv2;
0085     const struct snd_pcm_hw_constraint_list *sysclk_constraints;
0086     const int *mclk_ratios;
0087     bool provider;
0088     struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
0089 };
0090 
0091 /*
0092  * ES8328 Controls
0093  */
0094 
0095 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
0096                       "L + R Invert"};
0097 static SOC_ENUM_SINGLE_DECL(adcpol,
0098                 ES8328_ADCCONTROL6, 6, adcpol_txt);
0099 
0100 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
0101 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
0102 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
0103 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
0104 
0105 static const struct {
0106     int rate;
0107     unsigned int val;
0108 } deemph_settings[] = {
0109     { 0,     ES8328_DACCONTROL6_DEEMPH_OFF },
0110     { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
0111     { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
0112     { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
0113 };
0114 
0115 static int es8328_set_deemph(struct snd_soc_component *component)
0116 {
0117     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0118     int val, i, best;
0119 
0120     /*
0121      * If we're using deemphasis select the nearest available sample
0122      * rate.
0123      */
0124     if (es8328->deemph) {
0125         best = 0;
0126         for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
0127             if (abs(deemph_settings[i].rate - es8328->playback_fs) <
0128                 abs(deemph_settings[best].rate - es8328->playback_fs))
0129                 best = i;
0130         }
0131 
0132         val = deemph_settings[best].val;
0133     } else {
0134         val = ES8328_DACCONTROL6_DEEMPH_OFF;
0135     }
0136 
0137     dev_dbg(component->dev, "Set deemphasis %d\n", val);
0138 
0139     return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
0140             ES8328_DACCONTROL6_DEEMPH_MASK, val);
0141 }
0142 
0143 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
0144                  struct snd_ctl_elem_value *ucontrol)
0145 {
0146     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0147     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0148 
0149     ucontrol->value.integer.value[0] = es8328->deemph;
0150     return 0;
0151 }
0152 
0153 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
0154                  struct snd_ctl_elem_value *ucontrol)
0155 {
0156     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0157     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0158     unsigned int deemph = ucontrol->value.integer.value[0];
0159     int ret;
0160 
0161     if (deemph > 1)
0162         return -EINVAL;
0163 
0164     if (es8328->deemph == deemph)
0165         return 0;
0166 
0167     ret = es8328_set_deemph(component);
0168     if (ret < 0)
0169         return ret;
0170 
0171     es8328->deemph = deemph;
0172 
0173     return 1;
0174 }
0175 
0176 
0177 
0178 static const struct snd_kcontrol_new es8328_snd_controls[] = {
0179     SOC_DOUBLE_R_TLV("Capture Digital Volume",
0180         ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
0181          0, 0xc0, 1, dac_adc_tlv),
0182     SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
0183 
0184     SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
0185             es8328_get_deemph, es8328_put_deemph),
0186 
0187     SOC_ENUM("Capture Polarity", adcpol),
0188 
0189     SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
0190             ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
0191     SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
0192             ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
0193     SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
0194             ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
0195     SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
0196             ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
0197 
0198     SOC_DOUBLE_R_TLV("PCM Volume",
0199             ES8328_LDACVOL, ES8328_RDACVOL,
0200             0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
0201 
0202     SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
0203             ES8328_LOUT1VOL, ES8328_ROUT1VOL,
0204             0, ES8328_OUT1VOL_MAX, 0, play_tlv),
0205 
0206     SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
0207             ES8328_LOUT2VOL, ES8328_ROUT2VOL,
0208             0, ES8328_OUT2VOL_MAX, 0, play_tlv),
0209 
0210     SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
0211             4, 0, 8, 0, mic_tlv),
0212 };
0213 
0214 /*
0215  * DAPM Controls
0216  */
0217 
0218 static const char * const es8328_line_texts[] = {
0219     "Line 1", "Line 2", "PGA", "Differential"};
0220 
0221 static const struct soc_enum es8328_lline_enum =
0222     SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
0223                   ARRAY_SIZE(es8328_line_texts),
0224                   es8328_line_texts);
0225 static const struct snd_kcontrol_new es8328_left_line_controls =
0226     SOC_DAPM_ENUM("Route", es8328_lline_enum);
0227 
0228 static const struct soc_enum es8328_rline_enum =
0229     SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
0230                   ARRAY_SIZE(es8328_line_texts),
0231                   es8328_line_texts);
0232 static const struct snd_kcontrol_new es8328_right_line_controls =
0233     SOC_DAPM_ENUM("Route", es8328_rline_enum);
0234 
0235 /* Left Mixer */
0236 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
0237     SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
0238     SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
0239     SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
0240     SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
0241 };
0242 
0243 /* Right Mixer */
0244 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
0245     SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
0246     SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
0247     SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
0248     SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
0249 };
0250 
0251 static const char * const es8328_pga_sel[] = {
0252     "Line 1", "Line 2", "Line 3", "Differential"};
0253 
0254 /* Left PGA Mux */
0255 static const struct soc_enum es8328_lpga_enum =
0256     SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
0257                   ARRAY_SIZE(es8328_pga_sel),
0258                   es8328_pga_sel);
0259 static const struct snd_kcontrol_new es8328_left_pga_controls =
0260     SOC_DAPM_ENUM("Route", es8328_lpga_enum);
0261 
0262 /* Right PGA Mux */
0263 static const struct soc_enum es8328_rpga_enum =
0264     SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
0265                   ARRAY_SIZE(es8328_pga_sel),
0266                   es8328_pga_sel);
0267 static const struct snd_kcontrol_new es8328_right_pga_controls =
0268     SOC_DAPM_ENUM("Route", es8328_rpga_enum);
0269 
0270 /* Differential Mux */
0271 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
0272 static SOC_ENUM_SINGLE_DECL(diffmux,
0273                 ES8328_ADCCONTROL3, 7, es8328_diff_sel);
0274 static const struct snd_kcontrol_new es8328_diffmux_controls =
0275     SOC_DAPM_ENUM("Route", diffmux);
0276 
0277 /* Mono ADC Mux */
0278 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
0279     "Mono (Right)", "Digital Mono"};
0280 static SOC_ENUM_SINGLE_DECL(monomux,
0281                 ES8328_ADCCONTROL3, 3, es8328_mono_mux);
0282 static const struct snd_kcontrol_new es8328_monomux_controls =
0283     SOC_DAPM_ENUM("Route", monomux);
0284 
0285 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
0286     SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
0287         &es8328_diffmux_controls),
0288     SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
0289         &es8328_monomux_controls),
0290     SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
0291         &es8328_monomux_controls),
0292 
0293     SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
0294             ES8328_ADCPOWER_AINL_OFF, 1,
0295             &es8328_left_pga_controls),
0296     SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
0297             ES8328_ADCPOWER_AINR_OFF, 1,
0298             &es8328_right_pga_controls),
0299 
0300     SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
0301         &es8328_left_line_controls),
0302     SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
0303         &es8328_right_line_controls),
0304 
0305     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
0306             ES8328_ADCPOWER_ADCR_OFF, 1),
0307     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
0308             ES8328_ADCPOWER_ADCL_OFF, 1),
0309 
0310     SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
0311             ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
0312     SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
0313             ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
0314 
0315     SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
0316             ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
0317     SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
0318             ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
0319 
0320     SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
0321             ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
0322     SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
0323             ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
0324 
0325     SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
0326             ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
0327     SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
0328             ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
0329 
0330     SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
0331             ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
0332     SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
0333             ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
0334 
0335     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
0336             ES8328_DACPOWER_RDAC_OFF, 1),
0337     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
0338             ES8328_DACPOWER_LDAC_OFF, 1),
0339 
0340     SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
0341         &es8328_left_mixer_controls[0],
0342         ARRAY_SIZE(es8328_left_mixer_controls)),
0343     SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
0344         &es8328_right_mixer_controls[0],
0345         ARRAY_SIZE(es8328_right_mixer_controls)),
0346 
0347     SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
0348             ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
0349     SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
0350             ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
0351     SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
0352             ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
0353     SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
0354             ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
0355 
0356     SND_SOC_DAPM_OUTPUT("LOUT1"),
0357     SND_SOC_DAPM_OUTPUT("ROUT1"),
0358     SND_SOC_DAPM_OUTPUT("LOUT2"),
0359     SND_SOC_DAPM_OUTPUT("ROUT2"),
0360 
0361     SND_SOC_DAPM_INPUT("LINPUT1"),
0362     SND_SOC_DAPM_INPUT("LINPUT2"),
0363     SND_SOC_DAPM_INPUT("RINPUT1"),
0364     SND_SOC_DAPM_INPUT("RINPUT2"),
0365 };
0366 
0367 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
0368 
0369     { "Left Line Mux", "Line 1", "LINPUT1" },
0370     { "Left Line Mux", "Line 2", "LINPUT2" },
0371     { "Left Line Mux", "PGA", "Left PGA Mux" },
0372     { "Left Line Mux", "Differential", "Differential Mux" },
0373 
0374     { "Right Line Mux", "Line 1", "RINPUT1" },
0375     { "Right Line Mux", "Line 2", "RINPUT2" },
0376     { "Right Line Mux", "PGA", "Right PGA Mux" },
0377     { "Right Line Mux", "Differential", "Differential Mux" },
0378 
0379     { "Left PGA Mux", "Line 1", "LINPUT1" },
0380     { "Left PGA Mux", "Line 2", "LINPUT2" },
0381     { "Left PGA Mux", "Differential", "Differential Mux" },
0382 
0383     { "Right PGA Mux", "Line 1", "RINPUT1" },
0384     { "Right PGA Mux", "Line 2", "RINPUT2" },
0385     { "Right PGA Mux", "Differential", "Differential Mux" },
0386 
0387     { "Differential Mux", "Line 1", "LINPUT1" },
0388     { "Differential Mux", "Line 1", "RINPUT1" },
0389     { "Differential Mux", "Line 2", "LINPUT2" },
0390     { "Differential Mux", "Line 2", "RINPUT2" },
0391 
0392     { "Left ADC Mux", "Stereo", "Left PGA Mux" },
0393     { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
0394     { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
0395 
0396     { "Right ADC Mux", "Stereo", "Right PGA Mux" },
0397     { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
0398     { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
0399 
0400     { "Left ADC", NULL, "Left ADC Mux" },
0401     { "Right ADC", NULL, "Right ADC Mux" },
0402 
0403     { "ADC DIG", NULL, "ADC STM" },
0404     { "ADC DIG", NULL, "ADC Vref" },
0405     { "ADC DIG", NULL, "ADC DLL" },
0406 
0407     { "Left ADC", NULL, "ADC DIG" },
0408     { "Right ADC", NULL, "ADC DIG" },
0409 
0410     { "Mic Bias", NULL, "Mic Bias Gen" },
0411 
0412     { "Left Line Mux", "Line 1", "LINPUT1" },
0413     { "Left Line Mux", "Line 2", "LINPUT2" },
0414     { "Left Line Mux", "PGA", "Left PGA Mux" },
0415     { "Left Line Mux", "Differential", "Differential Mux" },
0416 
0417     { "Right Line Mux", "Line 1", "RINPUT1" },
0418     { "Right Line Mux", "Line 2", "RINPUT2" },
0419     { "Right Line Mux", "PGA", "Right PGA Mux" },
0420     { "Right Line Mux", "Differential", "Differential Mux" },
0421 
0422     { "Left Out 1", NULL, "Left DAC" },
0423     { "Right Out 1", NULL, "Right DAC" },
0424     { "Left Out 2", NULL, "Left DAC" },
0425     { "Right Out 2", NULL, "Right DAC" },
0426 
0427     { "Left Mixer", "Playback Switch", "Left DAC" },
0428     { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
0429     { "Left Mixer", "Right Playback Switch", "Right DAC" },
0430     { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
0431 
0432     { "Right Mixer", "Left Playback Switch", "Left DAC" },
0433     { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
0434     { "Right Mixer", "Playback Switch", "Right DAC" },
0435     { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
0436 
0437     { "DAC DIG", NULL, "DAC STM" },
0438     { "DAC DIG", NULL, "DAC Vref" },
0439     { "DAC DIG", NULL, "DAC DLL" },
0440 
0441     { "Left DAC", NULL, "DAC DIG" },
0442     { "Right DAC", NULL, "DAC DIG" },
0443 
0444     { "Left Out 1", NULL, "Left Mixer" },
0445     { "LOUT1", NULL, "Left Out 1" },
0446     { "Right Out 1", NULL, "Right Mixer" },
0447     { "ROUT1", NULL, "Right Out 1" },
0448 
0449     { "Left Out 2", NULL, "Left Mixer" },
0450     { "LOUT2", NULL, "Left Out 2" },
0451     { "Right Out 2", NULL, "Right Mixer" },
0452     { "ROUT2", NULL, "Right Out 2" },
0453 };
0454 
0455 static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
0456 {
0457     return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
0458             ES8328_DACCONTROL3_DACMUTE,
0459             mute ? ES8328_DACCONTROL3_DACMUTE : 0);
0460 }
0461 
0462 static int es8328_startup(struct snd_pcm_substream *substream,
0463               struct snd_soc_dai *dai)
0464 {
0465     struct snd_soc_component *component = dai->component;
0466     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0467 
0468     if (es8328->provider && es8328->sysclk_constraints)
0469         snd_pcm_hw_constraint_list(substream->runtime, 0,
0470                 SNDRV_PCM_HW_PARAM_RATE,
0471                 es8328->sysclk_constraints);
0472 
0473     return 0;
0474 }
0475 
0476 static int es8328_hw_params(struct snd_pcm_substream *substream,
0477     struct snd_pcm_hw_params *params,
0478     struct snd_soc_dai *dai)
0479 {
0480     struct snd_soc_component *component = dai->component;
0481     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0482     int i;
0483     int reg;
0484     int wl;
0485     int ratio;
0486 
0487     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0488         reg = ES8328_DACCONTROL2;
0489     else
0490         reg = ES8328_ADCCONTROL5;
0491 
0492     if (es8328->provider) {
0493         if (!es8328->sysclk_constraints) {
0494             dev_err(component->dev, "No MCLK configured\n");
0495             return -EINVAL;
0496         }
0497 
0498         for (i = 0; i < es8328->sysclk_constraints->count; i++)
0499             if (es8328->sysclk_constraints->list[i] ==
0500                 params_rate(params))
0501                 break;
0502 
0503         if (i == es8328->sysclk_constraints->count) {
0504             dev_err(component->dev,
0505                 "LRCLK %d unsupported with current clock\n",
0506                 params_rate(params));
0507             return -EINVAL;
0508         }
0509         ratio = es8328->mclk_ratios[i];
0510     } else {
0511         ratio = 0;
0512         es8328->mclkdiv2 = 0;
0513     }
0514 
0515     snd_soc_component_update_bits(component, ES8328_MASTERMODE,
0516             ES8328_MASTERMODE_MCLKDIV2,
0517             es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
0518 
0519     switch (params_width(params)) {
0520     case 16:
0521         wl = 3;
0522         break;
0523     case 18:
0524         wl = 2;
0525         break;
0526     case 20:
0527         wl = 1;
0528         break;
0529     case 24:
0530         wl = 0;
0531         break;
0532     case 32:
0533         wl = 4;
0534         break;
0535     default:
0536         return -EINVAL;
0537     }
0538 
0539     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0540         snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
0541                 ES8328_DACCONTROL1_DACWL_MASK,
0542                 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
0543 
0544         es8328->playback_fs = params_rate(params);
0545         es8328_set_deemph(component);
0546     } else
0547         snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
0548                 ES8328_ADCCONTROL4_ADCWL_MASK,
0549                 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
0550 
0551     return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
0552 }
0553 
0554 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
0555         int clk_id, unsigned int freq, int dir)
0556 {
0557     struct snd_soc_component *component = codec_dai->component;
0558     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0559     int mclkdiv2 = 0;
0560 
0561     switch (freq) {
0562     case 0:
0563         es8328->sysclk_constraints = NULL;
0564         es8328->mclk_ratios = NULL;
0565         break;
0566     case 22579200:
0567         mclkdiv2 = 1;
0568         fallthrough;
0569     case 11289600:
0570         es8328->sysclk_constraints = &constraints_11289;
0571         es8328->mclk_ratios = ratios_11289;
0572         break;
0573     case 24576000:
0574         mclkdiv2 = 1;
0575         fallthrough;
0576     case 12288000:
0577         es8328->sysclk_constraints = &constraints_12288;
0578         es8328->mclk_ratios = ratios_12288;
0579         break;
0580     default:
0581         return -EINVAL;
0582     }
0583 
0584     es8328->mclkdiv2 = mclkdiv2;
0585     return 0;
0586 }
0587 
0588 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
0589         unsigned int fmt)
0590 {
0591     struct snd_soc_component *component = codec_dai->component;
0592     struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
0593     u8 dac_mode = 0;
0594     u8 adc_mode = 0;
0595 
0596     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0597     case SND_SOC_DAIFMT_CBP_CFP:
0598         /* Master serial port mode, with BCLK generated automatically */
0599         snd_soc_component_update_bits(component, ES8328_MASTERMODE,
0600                     ES8328_MASTERMODE_MSC,
0601                     ES8328_MASTERMODE_MSC);
0602         es8328->provider = true;
0603         break;
0604     case SND_SOC_DAIFMT_CBC_CFC:
0605         /* Slave serial port mode */
0606         snd_soc_component_update_bits(component, ES8328_MASTERMODE,
0607                     ES8328_MASTERMODE_MSC, 0);
0608         es8328->provider = false;
0609         break;
0610     default:
0611         return -EINVAL;
0612     }
0613 
0614     /* interface format */
0615     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0616     case SND_SOC_DAIFMT_I2S:
0617         dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
0618         adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
0619         break;
0620     case SND_SOC_DAIFMT_RIGHT_J:
0621         dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
0622         adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
0623         break;
0624     case SND_SOC_DAIFMT_LEFT_J:
0625         dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
0626         adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
0627         break;
0628     default:
0629         return -EINVAL;
0630     }
0631 
0632     /* clock inversion */
0633     if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
0634         return -EINVAL;
0635 
0636     snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
0637             ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
0638     snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
0639             ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
0640 
0641     return 0;
0642 }
0643 
0644 static int es8328_set_bias_level(struct snd_soc_component *component,
0645                  enum snd_soc_bias_level level)
0646 {
0647     switch (level) {
0648     case SND_SOC_BIAS_ON:
0649         break;
0650 
0651     case SND_SOC_BIAS_PREPARE:
0652         /* VREF, VMID=2x50k, digital enabled */
0653         snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
0654         snd_soc_component_update_bits(component, ES8328_CONTROL1,
0655                 ES8328_CONTROL1_VMIDSEL_MASK |
0656                 ES8328_CONTROL1_ENREF,
0657                 ES8328_CONTROL1_VMIDSEL_50k |
0658                 ES8328_CONTROL1_ENREF);
0659         break;
0660 
0661     case SND_SOC_BIAS_STANDBY:
0662         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0663             snd_soc_component_update_bits(component, ES8328_CONTROL1,
0664                     ES8328_CONTROL1_VMIDSEL_MASK |
0665                     ES8328_CONTROL1_ENREF,
0666                     ES8328_CONTROL1_VMIDSEL_5k |
0667                     ES8328_CONTROL1_ENREF);
0668 
0669             /* Charge caps */
0670             msleep(100);
0671         }
0672 
0673         snd_soc_component_write(component, ES8328_CONTROL2,
0674                 ES8328_CONTROL2_OVERCURRENT_ON |
0675                 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
0676 
0677         /* VREF, VMID=2*500k, digital stopped */
0678         snd_soc_component_update_bits(component, ES8328_CONTROL1,
0679                 ES8328_CONTROL1_VMIDSEL_MASK |
0680                 ES8328_CONTROL1_ENREF,
0681                 ES8328_CONTROL1_VMIDSEL_500k |
0682                 ES8328_CONTROL1_ENREF);
0683         break;
0684 
0685     case SND_SOC_BIAS_OFF:
0686         snd_soc_component_update_bits(component, ES8328_CONTROL1,
0687                 ES8328_CONTROL1_VMIDSEL_MASK |
0688                 ES8328_CONTROL1_ENREF,
0689                 0);
0690         break;
0691     }
0692     return 0;
0693 }
0694 
0695 static const struct snd_soc_dai_ops es8328_dai_ops = {
0696     .startup    = es8328_startup,
0697     .hw_params  = es8328_hw_params,
0698     .mute_stream    = es8328_mute,
0699     .set_sysclk = es8328_set_sysclk,
0700     .set_fmt    = es8328_set_dai_fmt,
0701     .no_capture_mute = 1,
0702 };
0703 
0704 static struct snd_soc_dai_driver es8328_dai = {
0705     .name = "es8328-hifi-analog",
0706     .playback = {
0707         .stream_name = "Playback",
0708         .channels_min = 2,
0709         .channels_max = 2,
0710         .rates = ES8328_RATES,
0711         .formats = ES8328_FORMATS,
0712     },
0713     .capture = {
0714         .stream_name = "Capture",
0715         .channels_min = 2,
0716         .channels_max = 2,
0717         .rates = ES8328_RATES,
0718         .formats = ES8328_FORMATS,
0719     },
0720     .ops = &es8328_dai_ops,
0721     .symmetric_rate = 1,
0722 };
0723 
0724 static int es8328_suspend(struct snd_soc_component *component)
0725 {
0726     struct es8328_priv *es8328;
0727     int ret;
0728 
0729     es8328 = snd_soc_component_get_drvdata(component);
0730 
0731     clk_disable_unprepare(es8328->clk);
0732 
0733     ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
0734             es8328->supplies);
0735     if (ret) {
0736         dev_err(component->dev, "unable to disable regulators\n");
0737         return ret;
0738     }
0739     return 0;
0740 }
0741 
0742 static int es8328_resume(struct snd_soc_component *component)
0743 {
0744     struct regmap *regmap = dev_get_regmap(component->dev, NULL);
0745     struct es8328_priv *es8328;
0746     int ret;
0747 
0748     es8328 = snd_soc_component_get_drvdata(component);
0749 
0750     ret = clk_prepare_enable(es8328->clk);
0751     if (ret) {
0752         dev_err(component->dev, "unable to enable clock\n");
0753         return ret;
0754     }
0755 
0756     ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
0757                     es8328->supplies);
0758     if (ret) {
0759         dev_err(component->dev, "unable to enable regulators\n");
0760         return ret;
0761     }
0762 
0763     regcache_mark_dirty(regmap);
0764     ret = regcache_sync(regmap);
0765     if (ret) {
0766         dev_err(component->dev, "unable to sync regcache\n");
0767         return ret;
0768     }
0769 
0770     return 0;
0771 }
0772 
0773 static int es8328_component_probe(struct snd_soc_component *component)
0774 {
0775     struct es8328_priv *es8328;
0776     int ret;
0777 
0778     es8328 = snd_soc_component_get_drvdata(component);
0779 
0780     ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
0781                     es8328->supplies);
0782     if (ret) {
0783         dev_err(component->dev, "unable to enable regulators\n");
0784         return ret;
0785     }
0786 
0787     /* Setup clocks */
0788     es8328->clk = devm_clk_get(component->dev, NULL);
0789     if (IS_ERR(es8328->clk)) {
0790         dev_err(component->dev, "codec clock missing or invalid\n");
0791         ret = PTR_ERR(es8328->clk);
0792         goto clk_fail;
0793     }
0794 
0795     ret = clk_prepare_enable(es8328->clk);
0796     if (ret) {
0797         dev_err(component->dev, "unable to prepare codec clk\n");
0798         goto clk_fail;
0799     }
0800 
0801     return 0;
0802 
0803 clk_fail:
0804     regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
0805                    es8328->supplies);
0806     return ret;
0807 }
0808 
0809 static void es8328_remove(struct snd_soc_component *component)
0810 {
0811     struct es8328_priv *es8328;
0812 
0813     es8328 = snd_soc_component_get_drvdata(component);
0814 
0815     clk_disable_unprepare(es8328->clk);
0816 
0817     regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
0818                    es8328->supplies);
0819 }
0820 
0821 const struct regmap_config es8328_regmap_config = {
0822     .reg_bits   = 8,
0823     .val_bits   = 8,
0824     .max_register   = ES8328_REG_MAX,
0825     .cache_type = REGCACHE_RBTREE,
0826     .use_single_read = true,
0827     .use_single_write = true,
0828 };
0829 EXPORT_SYMBOL_GPL(es8328_regmap_config);
0830 
0831 static const struct snd_soc_component_driver es8328_component_driver = {
0832     .probe          = es8328_component_probe,
0833     .remove         = es8328_remove,
0834     .suspend        = es8328_suspend,
0835     .resume         = es8328_resume,
0836     .set_bias_level     = es8328_set_bias_level,
0837     .controls       = es8328_snd_controls,
0838     .num_controls       = ARRAY_SIZE(es8328_snd_controls),
0839     .dapm_widgets       = es8328_dapm_widgets,
0840     .num_dapm_widgets   = ARRAY_SIZE(es8328_dapm_widgets),
0841     .dapm_routes        = es8328_dapm_routes,
0842     .num_dapm_routes    = ARRAY_SIZE(es8328_dapm_routes),
0843     .suspend_bias_off   = 1,
0844     .idle_bias_on       = 1,
0845     .use_pmdown_time    = 1,
0846     .endianness     = 1,
0847 };
0848 
0849 int es8328_probe(struct device *dev, struct regmap *regmap)
0850 {
0851     struct es8328_priv *es8328;
0852     int ret;
0853     int i;
0854 
0855     if (IS_ERR(regmap))
0856         return PTR_ERR(regmap);
0857 
0858     es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
0859     if (es8328 == NULL)
0860         return -ENOMEM;
0861 
0862     es8328->regmap = regmap;
0863 
0864     for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
0865         es8328->supplies[i].supply = supply_names[i];
0866 
0867     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
0868                 es8328->supplies);
0869     if (ret) {
0870         dev_err(dev, "unable to get regulators\n");
0871         return ret;
0872     }
0873 
0874     dev_set_drvdata(dev, es8328);
0875 
0876     return devm_snd_soc_register_component(dev,
0877             &es8328_component_driver, &es8328_dai, 1);
0878 }
0879 EXPORT_SYMBOL_GPL(es8328_probe);
0880 
0881 MODULE_DESCRIPTION("ASoC ES8328 driver");
0882 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
0883 MODULE_LICENSE("GPL");
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