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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * DA9055 ALSA Soc codec driver
0004  *
0005  * Copyright (c) 2012 Dialog Semiconductor
0006  *
0007  * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
0008  * Written by David Chen <david.chen@diasemi.com> and
0009  * Ashish Chavan <ashish.chavan@kpitcummins.com>
0010  */
0011 
0012 #include <linux/delay.h>
0013 #include <linux/i2c.h>
0014 #include <linux/regmap.h>
0015 #include <linux/slab.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022 #include <sound/initval.h>
0023 #include <sound/tlv.h>
0024 #include <sound/da9055.h>
0025 
0026 /* DA9055 register space */
0027 
0028 /* Status Registers */
0029 #define DA9055_STATUS1          0x02
0030 #define DA9055_PLL_STATUS       0x03
0031 #define DA9055_AUX_L_GAIN_STATUS    0x04
0032 #define DA9055_AUX_R_GAIN_STATUS    0x05
0033 #define DA9055_MIC_L_GAIN_STATUS    0x06
0034 #define DA9055_MIC_R_GAIN_STATUS    0x07
0035 #define DA9055_MIXIN_L_GAIN_STATUS  0x08
0036 #define DA9055_MIXIN_R_GAIN_STATUS  0x09
0037 #define DA9055_ADC_L_GAIN_STATUS    0x0A
0038 #define DA9055_ADC_R_GAIN_STATUS    0x0B
0039 #define DA9055_DAC_L_GAIN_STATUS    0x0C
0040 #define DA9055_DAC_R_GAIN_STATUS    0x0D
0041 #define DA9055_HP_L_GAIN_STATUS     0x0E
0042 #define DA9055_HP_R_GAIN_STATUS     0x0F
0043 #define DA9055_LINE_GAIN_STATUS     0x10
0044 
0045 /* System Initialisation Registers */
0046 #define DA9055_CIF_CTRL         0x20
0047 #define DA9055_DIG_ROUTING_AIF      0X21
0048 #define DA9055_SR           0x22
0049 #define DA9055_REFERENCES       0x23
0050 #define DA9055_PLL_FRAC_TOP     0x24
0051 #define DA9055_PLL_FRAC_BOT     0x25
0052 #define DA9055_PLL_INTEGER      0x26
0053 #define DA9055_PLL_CTRL         0x27
0054 #define DA9055_AIF_CLK_MODE     0x28
0055 #define DA9055_AIF_CTRL         0x29
0056 #define DA9055_DIG_ROUTING_DAC      0x2A
0057 #define DA9055_ALC_CTRL1        0x2B
0058 
0059 /* Input - Gain, Select and Filter Registers */
0060 #define DA9055_AUX_L_GAIN       0x30
0061 #define DA9055_AUX_R_GAIN       0x31
0062 #define DA9055_MIXIN_L_SELECT       0x32
0063 #define DA9055_MIXIN_R_SELECT       0x33
0064 #define DA9055_MIXIN_L_GAIN     0x34
0065 #define DA9055_MIXIN_R_GAIN     0x35
0066 #define DA9055_ADC_L_GAIN       0x36
0067 #define DA9055_ADC_R_GAIN       0x37
0068 #define DA9055_ADC_FILTERS1     0x38
0069 #define DA9055_MIC_L_GAIN       0x39
0070 #define DA9055_MIC_R_GAIN       0x3A
0071 
0072 /* Output - Gain, Select and Filter Registers */
0073 #define DA9055_DAC_FILTERS5     0x40
0074 #define DA9055_DAC_FILTERS2     0x41
0075 #define DA9055_DAC_FILTERS3     0x42
0076 #define DA9055_DAC_FILTERS4     0x43
0077 #define DA9055_DAC_FILTERS1     0x44
0078 #define DA9055_DAC_L_GAIN       0x45
0079 #define DA9055_DAC_R_GAIN       0x46
0080 #define DA9055_CP_CTRL          0x47
0081 #define DA9055_HP_L_GAIN        0x48
0082 #define DA9055_HP_R_GAIN        0x49
0083 #define DA9055_LINE_GAIN        0x4A
0084 #define DA9055_MIXOUT_L_SELECT      0x4B
0085 #define DA9055_MIXOUT_R_SELECT      0x4C
0086 
0087 /* System Controller Registers */
0088 #define DA9055_SYSTEM_MODES_INPUT   0x50
0089 #define DA9055_SYSTEM_MODES_OUTPUT  0x51
0090 
0091 /* Control Registers */
0092 #define DA9055_AUX_L_CTRL       0x60
0093 #define DA9055_AUX_R_CTRL       0x61
0094 #define DA9055_MIC_BIAS_CTRL        0x62
0095 #define DA9055_MIC_L_CTRL       0x63
0096 #define DA9055_MIC_R_CTRL       0x64
0097 #define DA9055_MIXIN_L_CTRL     0x65
0098 #define DA9055_MIXIN_R_CTRL     0x66
0099 #define DA9055_ADC_L_CTRL       0x67
0100 #define DA9055_ADC_R_CTRL       0x68
0101 #define DA9055_DAC_L_CTRL       0x69
0102 #define DA9055_DAC_R_CTRL       0x6A
0103 #define DA9055_HP_L_CTRL        0x6B
0104 #define DA9055_HP_R_CTRL        0x6C
0105 #define DA9055_LINE_CTRL        0x6D
0106 #define DA9055_MIXOUT_L_CTRL        0x6E
0107 #define DA9055_MIXOUT_R_CTRL        0x6F
0108 
0109 /* Configuration Registers */
0110 #define DA9055_LDO_CTRL         0x90
0111 #define DA9055_IO_CTRL          0x91
0112 #define DA9055_GAIN_RAMP_CTRL       0x92
0113 #define DA9055_MIC_CONFIG       0x93
0114 #define DA9055_PC_COUNT         0x94
0115 #define DA9055_CP_VOL_THRESHOLD1    0x95
0116 #define DA9055_CP_DELAY         0x96
0117 #define DA9055_CP_DETECTOR      0x97
0118 #define DA9055_AIF_OFFSET       0x98
0119 #define DA9055_DIG_CTRL         0x99
0120 #define DA9055_ALC_CTRL2        0x9A
0121 #define DA9055_ALC_CTRL3        0x9B
0122 #define DA9055_ALC_NOISE        0x9C
0123 #define DA9055_ALC_TARGET_MIN       0x9D
0124 #define DA9055_ALC_TARGET_MAX       0x9E
0125 #define DA9055_ALC_GAIN_LIMITS      0x9F
0126 #define DA9055_ALC_ANA_GAIN_LIMITS  0xA0
0127 #define DA9055_ALC_ANTICLIP_CTRL    0xA1
0128 #define DA9055_ALC_ANTICLIP_LEVEL   0xA2
0129 #define DA9055_ALC_OFFSET_OP2M_L    0xA6
0130 #define DA9055_ALC_OFFSET_OP2U_L    0xA7
0131 #define DA9055_ALC_OFFSET_OP2M_R    0xAB
0132 #define DA9055_ALC_OFFSET_OP2U_R    0xAC
0133 #define DA9055_ALC_CIC_OP_LVL_CTRL  0xAD
0134 #define DA9055_ALC_CIC_OP_LVL_DATA  0xAE
0135 #define DA9055_DAC_NG_SETUP_TIME    0xAF
0136 #define DA9055_DAC_NG_OFF_THRESHOLD 0xB0
0137 #define DA9055_DAC_NG_ON_THRESHOLD  0xB1
0138 #define DA9055_DAC_NG_CTRL      0xB2
0139 
0140 /* SR bit fields */
0141 #define DA9055_SR_8000          (0x1 << 0)
0142 #define DA9055_SR_11025         (0x2 << 0)
0143 #define DA9055_SR_12000         (0x3 << 0)
0144 #define DA9055_SR_16000         (0x5 << 0)
0145 #define DA9055_SR_22050         (0x6 << 0)
0146 #define DA9055_SR_24000         (0x7 << 0)
0147 #define DA9055_SR_32000         (0x9 << 0)
0148 #define DA9055_SR_44100         (0xA << 0)
0149 #define DA9055_SR_48000         (0xB << 0)
0150 #define DA9055_SR_88200         (0xE << 0)
0151 #define DA9055_SR_96000         (0xF << 0)
0152 
0153 /* REFERENCES bit fields */
0154 #define DA9055_BIAS_EN          (1 << 3)
0155 #define DA9055_VMID_EN          (1 << 7)
0156 
0157 /* PLL_CTRL bit fields */
0158 #define DA9055_PLL_INDIV_10_20_MHZ  (1 << 2)
0159 #define DA9055_PLL_SRM_EN       (1 << 6)
0160 #define DA9055_PLL_EN           (1 << 7)
0161 
0162 /* AIF_CLK_MODE bit fields */
0163 #define DA9055_AIF_BCLKS_PER_WCLK_32    (0 << 0)
0164 #define DA9055_AIF_BCLKS_PER_WCLK_64    (1 << 0)
0165 #define DA9055_AIF_BCLKS_PER_WCLK_128   (2 << 0)
0166 #define DA9055_AIF_BCLKS_PER_WCLK_256   (3 << 0)
0167 #define DA9055_AIF_CLK_EN_SLAVE_MODE    (0 << 7)
0168 #define DA9055_AIF_CLK_EN_MASTER_MODE   (1 << 7)
0169 
0170 /* AIF_CTRL bit fields */
0171 #define DA9055_AIF_FORMAT_I2S_MODE  (0 << 0)
0172 #define DA9055_AIF_FORMAT_LEFT_J    (1 << 0)
0173 #define DA9055_AIF_FORMAT_RIGHT_J   (2 << 0)
0174 #define DA9055_AIF_FORMAT_DSP       (3 << 0)
0175 #define DA9055_AIF_WORD_S16_LE      (0 << 2)
0176 #define DA9055_AIF_WORD_S20_3LE     (1 << 2)
0177 #define DA9055_AIF_WORD_S24_LE      (2 << 2)
0178 #define DA9055_AIF_WORD_S32_LE      (3 << 2)
0179 
0180 /* MIC_L_CTRL bit fields */
0181 #define DA9055_MIC_L_MUTE_EN        (1 << 6)
0182 
0183 /* MIC_R_CTRL bit fields */
0184 #define DA9055_MIC_R_MUTE_EN        (1 << 6)
0185 
0186 /* MIXIN_L_CTRL bit fields */
0187 #define DA9055_MIXIN_L_MIX_EN       (1 << 3)
0188 
0189 /* MIXIN_R_CTRL bit fields */
0190 #define DA9055_MIXIN_R_MIX_EN       (1 << 3)
0191 
0192 /* ADC_L_CTRL bit fields */
0193 #define DA9055_ADC_L_EN         (1 << 7)
0194 
0195 /* ADC_R_CTRL bit fields */
0196 #define DA9055_ADC_R_EN         (1 << 7)
0197 
0198 /* DAC_L_CTRL bit fields */
0199 #define DA9055_DAC_L_MUTE_EN        (1 << 6)
0200 
0201 /* DAC_R_CTRL bit fields */
0202 #define DA9055_DAC_R_MUTE_EN        (1 << 6)
0203 
0204 /* HP_L_CTRL bit fields */
0205 #define DA9055_HP_L_AMP_OE      (1 << 3)
0206 
0207 /* HP_R_CTRL bit fields */
0208 #define DA9055_HP_R_AMP_OE      (1 << 3)
0209 
0210 /* LINE_CTRL bit fields */
0211 #define DA9055_LINE_AMP_OE      (1 << 3)
0212 
0213 /* MIXOUT_L_CTRL bit fields */
0214 #define DA9055_MIXOUT_L_MIX_EN      (1 << 3)
0215 
0216 /* MIXOUT_R_CTRL bit fields */
0217 #define DA9055_MIXOUT_R_MIX_EN      (1 << 3)
0218 
0219 /* MIC bias select bit fields */
0220 #define DA9055_MICBIAS2_EN      (1 << 6)
0221 
0222 /* ALC_CIC_OP_LEVEL_CTRL bit fields */
0223 #define DA9055_ALC_DATA_MIDDLE      (2 << 0)
0224 #define DA9055_ALC_DATA_TOP     (3 << 0)
0225 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT  (0 << 7)
0226 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
0227 
0228 #define DA9055_AIF_BCLK_MASK        (3 << 0)
0229 #define DA9055_AIF_CLK_MODE_MASK    (1 << 7)
0230 #define DA9055_AIF_FORMAT_MASK      (3 << 0)
0231 #define DA9055_AIF_WORD_LENGTH_MASK (3 << 2)
0232 #define DA9055_GAIN_RAMPING_EN      (1 << 5)
0233 #define DA9055_MICBIAS_LEVEL_MASK   (3 << 4)
0234 
0235 #define DA9055_ALC_OFFSET_15_8      0x00FF00
0236 #define DA9055_ALC_OFFSET_17_16     0x030000
0237 #define DA9055_ALC_AVG_ITERATIONS   5
0238 
0239 struct pll_div {
0240     int fref;
0241     int fout;
0242     u8 frac_top;
0243     u8 frac_bot;
0244     u8 integer;
0245     u8 mode;    /* 0 = slave, 1 = master */
0246 };
0247 
0248 /* PLL divisor table */
0249 static const struct pll_div da9055_pll_div[] = {
0250     /* for MASTER mode, fs = 44.1Khz and its harmonics */
0251     {11289600, 2822400, 0x00, 0x00, 0x20, 1},   /* MCLK=11.2896Mhz */
0252     {12000000, 2822400, 0x03, 0x61, 0x1E, 1},   /* MCLK=12Mhz */
0253     {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1},   /* MCLK=12.288Mhz */
0254     {13000000, 2822400, 0x19, 0x45, 0x1B, 1},   /* MCLK=13Mhz */
0255     {13500000, 2822400, 0x18, 0x56, 0x1A, 1},   /* MCLK=13.5Mhz */
0256     {14400000, 2822400, 0x02, 0xD0, 0x19, 1},   /* MCLK=14.4Mhz */
0257     {19200000, 2822400, 0x1A, 0x1C, 0x12, 1},   /* MCLK=19.2Mhz */
0258     {19680000, 2822400, 0x0B, 0x6D, 0x12, 1},   /* MCLK=19.68Mhz */
0259     {19800000, 2822400, 0x07, 0xDD, 0x12, 1},   /* MCLK=19.8Mhz */
0260     /* for MASTER mode, fs = 48Khz and its harmonics */
0261     {11289600, 3072000, 0x1A, 0x8E, 0x22, 1},   /* MCLK=11.2896Mhz */
0262     {12000000, 3072000, 0x18, 0x93, 0x20, 1},   /* MCLK=12Mhz */
0263     {12288000, 3072000, 0x00, 0x00, 0x20, 1},   /* MCLK=12.288Mhz */
0264     {13000000, 3072000, 0x07, 0xEA, 0x1E, 1},   /* MCLK=13Mhz */
0265     {13500000, 3072000, 0x04, 0x11, 0x1D, 1},   /* MCLK=13.5Mhz */
0266     {14400000, 3072000, 0x09, 0xD0, 0x1B, 1},   /* MCLK=14.4Mhz */
0267     {19200000, 3072000, 0x0F, 0x5C, 0x14, 1},   /* MCLK=19.2Mhz */
0268     {19680000, 3072000, 0x1F, 0x60, 0x13, 1},   /* MCLK=19.68Mhz */
0269     {19800000, 3072000, 0x1B, 0x80, 0x13, 1},   /* MCLK=19.8Mhz */
0270     /* for SLAVE mode with SRM */
0271     {11289600, 2822400, 0x0D, 0x47, 0x21, 0},   /* MCLK=11.2896Mhz */
0272     {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0},   /* MCLK=12Mhz */
0273     {12288000, 2822400, 0x16, 0x66, 0x1E, 0},   /* MCLK=12.288Mhz */
0274     {13000000, 2822400, 0x00, 0x98, 0x1D, 0},   /* MCLK=13Mhz */
0275     {13500000, 2822400, 0x1E, 0x33, 0x1B, 0},   /* MCLK=13.5Mhz */
0276     {14400000, 2822400, 0x06, 0x50, 0x1A, 0},   /* MCLK=14.4Mhz */
0277     {19200000, 2822400, 0x14, 0xBC, 0x13, 0},   /* MCLK=19.2Mhz */
0278     {19680000, 2822400, 0x05, 0x66, 0x13, 0},   /* MCLK=19.68Mhz */
0279     {19800000, 2822400, 0x01, 0xAE, 0x13, 0},   /* MCLK=19.8Mhz  */
0280 };
0281 
0282 enum clk_src {
0283     DA9055_CLKSRC_MCLK
0284 };
0285 
0286 /* Gain and Volume */
0287 
0288 static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
0289     0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
0290     /* -54dB to 15dB */
0291     0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
0292 );
0293 
0294 static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
0295     0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
0296     /* -78dB to 12dB */
0297     0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
0298 );
0299 
0300 static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
0301     0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
0302     /* 0dB to 36dB */
0303     0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
0304 );
0305 
0306 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
0307 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
0308 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
0309 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
0310 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
0311 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
0312 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
0313 
0314 /* ADC and DAC high pass filter cutoff value */
0315 static const char * const da9055_hpf_cutoff_txt[] = {
0316     "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
0317 };
0318 
0319 static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff,
0320                 DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt);
0321 
0322 static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff,
0323                 DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt);
0324 
0325 /* ADC and DAC voice mode (8kHz) high pass cutoff value */
0326 static const char * const da9055_vf_cutoff_txt[] = {
0327     "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
0328 };
0329 
0330 static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff,
0331                 DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt);
0332 
0333 static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff,
0334                 DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt);
0335 
0336 /* Gain ramping rate value */
0337 static const char * const da9055_gain_ramping_txt[] = {
0338     "nominal rate", "nominal rate * 4", "nominal rate * 8",
0339     "nominal rate / 8"
0340 };
0341 
0342 static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate,
0343                 DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt);
0344 
0345 /* DAC noise gate setup time value */
0346 static const char * const da9055_dac_ng_setup_time_txt[] = {
0347     "256 samples", "512 samples", "1024 samples", "2048 samples"
0348 };
0349 
0350 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time,
0351                 DA9055_DAC_NG_SETUP_TIME, 0,
0352                 da9055_dac_ng_setup_time_txt);
0353 
0354 /* DAC noise gate rampup rate value */
0355 static const char * const da9055_dac_ng_rampup_txt[] = {
0356     "0.02 ms/dB", "0.16 ms/dB"
0357 };
0358 
0359 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate,
0360                 DA9055_DAC_NG_SETUP_TIME, 2,
0361                 da9055_dac_ng_rampup_txt);
0362 
0363 /* DAC noise gate rampdown rate value */
0364 static const char * const da9055_dac_ng_rampdown_txt[] = {
0365     "0.64 ms/dB", "20.48 ms/dB"
0366 };
0367 
0368 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate,
0369                 DA9055_DAC_NG_SETUP_TIME, 3,
0370                 da9055_dac_ng_rampdown_txt);
0371 
0372 /* DAC soft mute rate value */
0373 static const char * const da9055_dac_soft_mute_rate_txt[] = {
0374     "1", "2", "4", "8", "16", "32", "64"
0375 };
0376 
0377 static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate,
0378                 DA9055_DAC_FILTERS5, 4,
0379                 da9055_dac_soft_mute_rate_txt);
0380 
0381 /* DAC routing select */
0382 static const char * const da9055_dac_src_txt[] = {
0383     "ADC output left", "ADC output right", "AIF input left",
0384     "AIF input right"
0385 };
0386 
0387 static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src,
0388                 DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt);
0389 
0390 static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src,
0391                 DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt);
0392 
0393 /* MIC PGA Left source select */
0394 static const char * const da9055_mic_l_src_txt[] = {
0395     "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
0396 };
0397 
0398 static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src,
0399                 DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt);
0400 
0401 /* MIC PGA Right source select */
0402 static const char * const da9055_mic_r_src_txt[] = {
0403     "MIC2_R_L", "MIC2_R", "MIC2_L"
0404 };
0405 
0406 static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src,
0407                 DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt);
0408 
0409 /* ALC Input Signal Tracking rate select */
0410 static const char * const da9055_signal_tracking_rate_txt[] = {
0411     "1/4", "1/16", "1/256", "1/65536"
0412 };
0413 
0414 static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate,
0415                 DA9055_ALC_CTRL3, 4,
0416                 da9055_signal_tracking_rate_txt);
0417 
0418 static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate,
0419                 DA9055_ALC_CTRL3, 6,
0420                 da9055_signal_tracking_rate_txt);
0421 
0422 /* ALC Attack Rate select */
0423 static const char * const da9055_attack_rate_txt[] = {
0424     "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
0425     "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
0426 };
0427 
0428 static SOC_ENUM_SINGLE_DECL(da9055_attack_rate,
0429                 DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt);
0430 
0431 /* ALC Release Rate select */
0432 static const char * const da9055_release_rate_txt[] = {
0433     "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
0434     "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
0435 };
0436 
0437 static SOC_ENUM_SINGLE_DECL(da9055_release_rate,
0438                 DA9055_ALC_CTRL2, 4, da9055_release_rate_txt);
0439 
0440 /* ALC Hold Time select */
0441 static const char * const da9055_hold_time_txt[] = {
0442     "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
0443     "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
0444     "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
0445 };
0446 
0447 static SOC_ENUM_SINGLE_DECL(da9055_hold_time,
0448                 DA9055_ALC_CTRL3, 0, da9055_hold_time_txt);
0449 
0450 static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val)
0451 {
0452     int mid_data, top_data;
0453     int sum = 0;
0454     u8 iteration;
0455 
0456     for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
0457          iteration++) {
0458         /* Select the left or right channel and capture data */
0459         snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
0460 
0461         /* Select middle 8 bits for read back from data register */
0462         snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
0463                   reg_val | DA9055_ALC_DATA_MIDDLE);
0464         mid_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
0465 
0466         /* Select top 8 bits for read back from data register */
0467         snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
0468                   reg_val | DA9055_ALC_DATA_TOP);
0469         top_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
0470 
0471         sum += ((mid_data << 8) | (top_data << 16));
0472     }
0473 
0474     return sum / DA9055_ALC_AVG_ITERATIONS;
0475 }
0476 
0477 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
0478                  struct snd_ctl_elem_value *ucontrol)
0479 {
0480     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0481     u8 reg_val, adc_left, adc_right, mic_left, mic_right;
0482     int avg_left_data, avg_right_data, offset_l, offset_r;
0483 
0484     if (ucontrol->value.integer.value[0]) {
0485         /*
0486          * While enabling ALC (or ALC sync mode), calibration of the DC
0487          * offsets must be done first
0488          */
0489 
0490         /* Save current values from Mic control registers */
0491         mic_left = snd_soc_component_read(component, DA9055_MIC_L_CTRL);
0492         mic_right = snd_soc_component_read(component, DA9055_MIC_R_CTRL);
0493 
0494         /* Mute Mic PGA Left and Right */
0495         snd_soc_component_update_bits(component, DA9055_MIC_L_CTRL,
0496                     DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
0497         snd_soc_component_update_bits(component, DA9055_MIC_R_CTRL,
0498                     DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
0499 
0500         /* Save current values from ADC control registers */
0501         adc_left = snd_soc_component_read(component, DA9055_ADC_L_CTRL);
0502         adc_right = snd_soc_component_read(component, DA9055_ADC_R_CTRL);
0503 
0504         /* Enable ADC Left and Right */
0505         snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
0506                     DA9055_ADC_L_EN, DA9055_ADC_L_EN);
0507         snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
0508                     DA9055_ADC_R_EN, DA9055_ADC_R_EN);
0509 
0510         /* Calculate average for Left and Right data */
0511         /* Left Data */
0512         avg_left_data = da9055_get_alc_data(component,
0513                 DA9055_ALC_CIC_OP_CHANNEL_LEFT);
0514         /* Right Data */
0515         avg_right_data = da9055_get_alc_data(component,
0516                  DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
0517 
0518         /* Calculate DC offset */
0519         offset_l = -avg_left_data;
0520         offset_r = -avg_right_data;
0521 
0522         reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
0523         snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val);
0524         reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
0525         snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val);
0526 
0527         reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
0528         snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val);
0529         reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
0530         snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val);
0531 
0532         /* Restore original values of ADC control registers */
0533         snd_soc_component_write(component, DA9055_ADC_L_CTRL, adc_left);
0534         snd_soc_component_write(component, DA9055_ADC_R_CTRL, adc_right);
0535 
0536         /* Restore original values of Mic control registers */
0537         snd_soc_component_write(component, DA9055_MIC_L_CTRL, mic_left);
0538         snd_soc_component_write(component, DA9055_MIC_R_CTRL, mic_right);
0539     }
0540 
0541     return snd_soc_put_volsw(kcontrol, ucontrol);
0542 }
0543 
0544 static const struct snd_kcontrol_new da9055_snd_controls[] = {
0545 
0546     /* Volume controls */
0547     SOC_DOUBLE_R_TLV("Mic Volume",
0548              DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
0549              0, 0x7, 0, mic_vol_tlv),
0550     SOC_DOUBLE_R_TLV("Aux Volume",
0551              DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
0552              0, 0x3f, 0, aux_vol_tlv),
0553     SOC_DOUBLE_R_TLV("Mixin PGA Volume",
0554              DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
0555              0, 0xf, 0, mixin_gain_tlv),
0556     SOC_DOUBLE_R_TLV("ADC Volume",
0557              DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
0558              0, 0x7f, 0, digital_gain_tlv),
0559 
0560     SOC_DOUBLE_R_TLV("DAC Volume",
0561              DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
0562              0, 0x7f, 0, digital_gain_tlv),
0563     SOC_DOUBLE_R_TLV("Headphone Volume",
0564              DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
0565              0, 0x3f, 0, hp_vol_tlv),
0566     SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
0567                lineout_vol_tlv),
0568 
0569     /* DAC Equalizer controls */
0570     SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
0571     SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
0572                eq_gain_tlv),
0573     SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
0574                eq_gain_tlv),
0575     SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
0576                eq_gain_tlv),
0577     SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
0578                eq_gain_tlv),
0579     SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
0580                eq_gain_tlv),
0581 
0582     /* High Pass Filter and Voice Mode controls */
0583     SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
0584     SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
0585     SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
0586     SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
0587 
0588     SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
0589     SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
0590     SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
0591     SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
0592 
0593     /* Mute controls */
0594     SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
0595              DA9055_MIC_R_CTRL, 6, 1, 0),
0596     SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
0597              DA9055_AUX_R_CTRL, 6, 1, 0),
0598     SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
0599              DA9055_MIXIN_R_CTRL, 6, 1, 0),
0600     SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
0601              DA9055_ADC_R_CTRL, 6, 1, 0),
0602     SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
0603              DA9055_HP_R_CTRL, 6, 1, 0),
0604     SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
0605     SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
0606     SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
0607 
0608     /* Zero Cross controls */
0609     SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
0610              DA9055_AUX_R_CTRL, 4, 1, 0),
0611     SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
0612              DA9055_MIXIN_R_CTRL, 4, 1, 0),
0613     SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
0614              DA9055_HP_R_CTRL, 4, 1, 0),
0615     SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
0616 
0617     /* Gain Ramping controls */
0618     SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
0619              DA9055_AUX_R_CTRL, 5, 1, 0),
0620     SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
0621              DA9055_MIXIN_R_CTRL, 5, 1, 0),
0622     SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
0623              DA9055_ADC_R_CTRL, 5, 1, 0),
0624     SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
0625              DA9055_DAC_R_CTRL, 5, 1, 0),
0626     SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
0627              DA9055_HP_R_CTRL, 5, 1, 0),
0628     SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
0629     SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
0630 
0631     /* DAC Noise Gate controls */
0632     SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
0633     SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
0634            0, 0x7, 0),
0635     SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
0636            0, 0x7, 0),
0637     SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
0638     SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
0639     SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
0640 
0641     /* DAC Invertion control */
0642     SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
0643     SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
0644 
0645     /* DMIC controls */
0646     SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
0647              DA9055_MIXIN_R_SELECT, 7, 1, 0),
0648 
0649     /* ALC Controls */
0650     SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
0651                snd_soc_get_volsw, da9055_put_alc_sw),
0652     SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
0653                snd_soc_get_volsw, da9055_put_alc_sw),
0654     SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
0655     SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
0656            7, 1, 0),
0657     SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
0658            0, 0x7f, 0),
0659     SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
0660                0, 0x3f, 1, alc_threshold_tlv),
0661     SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
0662                0, 0x3f, 1, alc_threshold_tlv),
0663     SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
0664                0, 0x3f, 1, alc_threshold_tlv),
0665     SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
0666                4, 0xf, 0, alc_gain_tlv),
0667     SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
0668                0, 0xf, 0, alc_gain_tlv),
0669     SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
0670                DA9055_ALC_ANA_GAIN_LIMITS,
0671                0, 0x7, 0, alc_analog_gain_tlv),
0672     SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
0673                DA9055_ALC_ANA_GAIN_LIMITS,
0674                4, 0x7, 0, alc_analog_gain_tlv),
0675     SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
0676     SOC_ENUM("ALC Release Rate", da9055_release_rate),
0677     SOC_ENUM("ALC Hold Time", da9055_hold_time),
0678     /*
0679      * Rate at which input signal envelope is tracked as the signal gets
0680      * larger
0681      */
0682     SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
0683     /*
0684      * Rate at which input signal envelope is tracked as the signal gets
0685      * smaller
0686      */
0687     SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
0688 };
0689 
0690 /* DAPM Controls */
0691 
0692 /* Mic PGA Left Source */
0693 static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
0694 SOC_DAPM_ENUM("Route", da9055_mic_l_src);
0695 
0696 /* Mic PGA Right Source */
0697 static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
0698 SOC_DAPM_ENUM("Route", da9055_mic_r_src);
0699 
0700 /* In Mixer Left */
0701 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
0702     SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
0703     SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
0704     SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
0705 };
0706 
0707 /* In Mixer Right */
0708 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
0709     SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
0710     SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
0711     SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
0712     SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
0713 };
0714 
0715 /* DAC Left Source */
0716 static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
0717 SOC_DAPM_ENUM("Route", da9055_dac_l_src);
0718 
0719 /* DAC Right Source */
0720 static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
0721 SOC_DAPM_ENUM("Route", da9055_dac_r_src);
0722 
0723 /* Out Mixer Left */
0724 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
0725     SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
0726     SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
0727     SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
0728     SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
0729     SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
0730             4, 1, 0),
0731     SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
0732             5, 1, 0),
0733     SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
0734             6, 1, 0),
0735 };
0736 
0737 /* Out Mixer Right */
0738 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
0739     SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
0740     SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
0741     SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
0742     SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
0743     SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
0744             4, 1, 0),
0745     SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
0746             5, 1, 0),
0747     SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
0748             6, 1, 0),
0749 };
0750 
0751 /* Headphone Output Enable */
0752 static const struct snd_kcontrol_new da9055_dapm_hp_l_control =
0753 SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0);
0754 
0755 static const struct snd_kcontrol_new da9055_dapm_hp_r_control =
0756 SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0);
0757 
0758 /* Lineout Output Enable */
0759 static const struct snd_kcontrol_new da9055_dapm_lineout_control =
0760 SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0);
0761 
0762 /* DAPM widgets */
0763 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
0764     /* Input Side */
0765 
0766     /* Input Lines */
0767     SND_SOC_DAPM_INPUT("MIC1"),
0768     SND_SOC_DAPM_INPUT("MIC2"),
0769     SND_SOC_DAPM_INPUT("AUXL"),
0770     SND_SOC_DAPM_INPUT("AUXR"),
0771 
0772     /* MUXs for Mic PGA source selection */
0773     SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
0774              &da9055_mic_l_mux_controls),
0775     SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
0776              &da9055_mic_r_mux_controls),
0777 
0778     /* Input PGAs */
0779     SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
0780     SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
0781     SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
0782     SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
0783     SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
0784     SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
0785 
0786     SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
0787     SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
0788     SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
0789 
0790     /* Input Mixers */
0791     SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
0792                &da9055_dapm_mixinl_controls[0],
0793                ARRAY_SIZE(da9055_dapm_mixinl_controls)),
0794     SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
0795                &da9055_dapm_mixinr_controls[0],
0796                ARRAY_SIZE(da9055_dapm_mixinr_controls)),
0797 
0798     /* ADCs */
0799     SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
0800     SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
0801 
0802     /* Output Side */
0803 
0804     /* MUXs for DAC source selection */
0805     SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
0806              &da9055_dac_l_mux_controls),
0807     SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
0808              &da9055_dac_r_mux_controls),
0809 
0810     /* AIF input */
0811     SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
0812     SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
0813 
0814     /* DACs */
0815     SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
0816     SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
0817 
0818     /* Output Mixers */
0819     SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
0820                &da9055_dapm_mixoutl_controls[0],
0821                ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
0822     SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
0823                &da9055_dapm_mixoutr_controls[0],
0824                ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
0825 
0826     /* Output Enable Switches */
0827     SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
0828                 &da9055_dapm_hp_l_control),
0829     SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
0830                 &da9055_dapm_hp_r_control),
0831     SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
0832                 &da9055_dapm_lineout_control),
0833 
0834     /* Output PGAs */
0835     SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
0836     SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
0837     SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
0838     SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
0839     SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
0840 
0841     /* Output Lines */
0842     SND_SOC_DAPM_OUTPUT("HPL"),
0843     SND_SOC_DAPM_OUTPUT("HPR"),
0844     SND_SOC_DAPM_OUTPUT("LINE"),
0845 };
0846 
0847 /* DAPM audio route definition */
0848 static const struct snd_soc_dapm_route da9055_audio_map[] = {
0849     /* Dest       Connecting Widget    source */
0850 
0851     /* Input path */
0852     {"Mic Left Source", "MIC1_P_N", "MIC1"},
0853     {"Mic Left Source", "MIC1_P", "MIC1"},
0854     {"Mic Left Source", "MIC1_N", "MIC1"},
0855     {"Mic Left Source", "MIC2_L", "MIC2"},
0856 
0857     {"Mic Right Source", "MIC2_R_L", "MIC2"},
0858     {"Mic Right Source", "MIC2_R", "MIC2"},
0859     {"Mic Right Source", "MIC2_L", "MIC2"},
0860 
0861     {"Mic Left", NULL, "Mic Left Source"},
0862     {"Mic Right", NULL, "Mic Right Source"},
0863 
0864     {"Aux Left", NULL, "AUXL"},
0865     {"Aux Right", NULL, "AUXR"},
0866 
0867     {"In Mixer Left", "Mic Left Switch", "Mic Left"},
0868     {"In Mixer Left", "Mic Right Switch", "Mic Right"},
0869     {"In Mixer Left", "Aux Left Switch", "Aux Left"},
0870 
0871     {"In Mixer Right", "Mic Right Switch", "Mic Right"},
0872     {"In Mixer Right", "Mic Left Switch", "Mic Left"},
0873     {"In Mixer Right", "Aux Right Switch", "Aux Right"},
0874     {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
0875 
0876     {"MIXIN Left", NULL, "In Mixer Left"},
0877     {"ADC Left", NULL, "MIXIN Left"},
0878 
0879     {"MIXIN Right", NULL, "In Mixer Right"},
0880     {"ADC Right", NULL, "MIXIN Right"},
0881 
0882     {"ADC Left", NULL, "AIF"},
0883     {"ADC Right", NULL, "AIF"},
0884 
0885     /* Output path */
0886     {"AIFIN Left", NULL, "AIF"},
0887     {"AIFIN Right", NULL, "AIF"},
0888 
0889     {"DAC Left Source", "ADC output left", "ADC Left"},
0890     {"DAC Left Source", "ADC output right", "ADC Right"},
0891     {"DAC Left Source", "AIF input left", "AIFIN Left"},
0892     {"DAC Left Source", "AIF input right", "AIFIN Right"},
0893 
0894     {"DAC Right Source", "ADC output left", "ADC Left"},
0895     {"DAC Right Source", "ADC output right", "ADC Right"},
0896     {"DAC Right Source", "AIF input left", "AIFIN Left"},
0897     {"DAC Right Source", "AIF input right", "AIFIN Right"},
0898 
0899     {"DAC Left", NULL, "DAC Left Source"},
0900     {"DAC Right", NULL, "DAC Right Source"},
0901 
0902     {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
0903     {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
0904     {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
0905     {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
0906     {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
0907     {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
0908     {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
0909 
0910     {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
0911     {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
0912     {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
0913     {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
0914     {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
0915     {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
0916     {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
0917 
0918     {"MIXOUT Left", NULL, "Out Mixer Left"},
0919     {"Headphone Left Enable", "Switch", "MIXOUT Left"},
0920     {"Headphone Left", NULL, "Headphone Left Enable"},
0921     {"Headphone Left", NULL, "Charge Pump"},
0922     {"HPL", NULL, "Headphone Left"},
0923 
0924     {"MIXOUT Right", NULL, "Out Mixer Right"},
0925     {"Headphone Right Enable", "Switch", "MIXOUT Right"},
0926     {"Headphone Right", NULL, "Headphone Right Enable"},
0927     {"Headphone Right", NULL, "Charge Pump"},
0928     {"HPR", NULL, "Headphone Right"},
0929 
0930     {"MIXOUT Right", NULL, "Out Mixer Right"},
0931     {"Lineout Enable", "Switch", "MIXOUT Right"},
0932     {"Lineout", NULL, "Lineout Enable"},
0933     {"LINE", NULL, "Lineout"},
0934 };
0935 
0936 /* Codec private data */
0937 struct da9055_priv {
0938     struct regmap *regmap;
0939     unsigned int mclk_rate;
0940     int master;
0941     struct da9055_platform_data *pdata;
0942 };
0943 
0944 static const struct reg_default da9055_reg_defaults[] = {
0945     { 0x21, 0x10 },
0946     { 0x22, 0x0A },
0947     { 0x23, 0x00 },
0948     { 0x24, 0x00 },
0949     { 0x25, 0x00 },
0950     { 0x26, 0x00 },
0951     { 0x27, 0x0C },
0952     { 0x28, 0x01 },
0953     { 0x29, 0x08 },
0954     { 0x2A, 0x32 },
0955     { 0x2B, 0x00 },
0956     { 0x30, 0x35 },
0957     { 0x31, 0x35 },
0958     { 0x32, 0x00 },
0959     { 0x33, 0x00 },
0960     { 0x34, 0x03 },
0961     { 0x35, 0x03 },
0962     { 0x36, 0x6F },
0963     { 0x37, 0x6F },
0964     { 0x38, 0x80 },
0965     { 0x39, 0x01 },
0966     { 0x3A, 0x01 },
0967     { 0x40, 0x00 },
0968     { 0x41, 0x88 },
0969     { 0x42, 0x88 },
0970     { 0x43, 0x08 },
0971     { 0x44, 0x80 },
0972     { 0x45, 0x6F },
0973     { 0x46, 0x6F },
0974     { 0x47, 0x61 },
0975     { 0x48, 0x35 },
0976     { 0x49, 0x35 },
0977     { 0x4A, 0x35 },
0978     { 0x4B, 0x00 },
0979     { 0x4C, 0x00 },
0980     { 0x60, 0x44 },
0981     { 0x61, 0x44 },
0982     { 0x62, 0x00 },
0983     { 0x63, 0x40 },
0984     { 0x64, 0x40 },
0985     { 0x65, 0x40 },
0986     { 0x66, 0x40 },
0987     { 0x67, 0x40 },
0988     { 0x68, 0x40 },
0989     { 0x69, 0x48 },
0990     { 0x6A, 0x40 },
0991     { 0x6B, 0x41 },
0992     { 0x6C, 0x40 },
0993     { 0x6D, 0x40 },
0994     { 0x6E, 0x10 },
0995     { 0x6F, 0x10 },
0996     { 0x90, 0x80 },
0997     { 0x92, 0x02 },
0998     { 0x93, 0x00 },
0999     { 0x99, 0x00 },
1000     { 0x9A, 0x00 },
1001     { 0x9B, 0x00 },
1002     { 0x9C, 0x3F },
1003     { 0x9D, 0x00 },
1004     { 0x9E, 0x3F },
1005     { 0x9F, 0xFF },
1006     { 0xA0, 0x71 },
1007     { 0xA1, 0x00 },
1008     { 0xA2, 0x00 },
1009     { 0xA6, 0x00 },
1010     { 0xA7, 0x00 },
1011     { 0xAB, 0x00 },
1012     { 0xAC, 0x00 },
1013     { 0xAD, 0x00 },
1014     { 0xAF, 0x08 },
1015     { 0xB0, 0x00 },
1016     { 0xB1, 0x00 },
1017     { 0xB2, 0x00 },
1018 };
1019 
1020 static bool da9055_volatile_register(struct device *dev,
1021                      unsigned int reg)
1022 {
1023     switch (reg) {
1024     case DA9055_STATUS1:
1025     case DA9055_PLL_STATUS:
1026     case DA9055_AUX_L_GAIN_STATUS:
1027     case DA9055_AUX_R_GAIN_STATUS:
1028     case DA9055_MIC_L_GAIN_STATUS:
1029     case DA9055_MIC_R_GAIN_STATUS:
1030     case DA9055_MIXIN_L_GAIN_STATUS:
1031     case DA9055_MIXIN_R_GAIN_STATUS:
1032     case DA9055_ADC_L_GAIN_STATUS:
1033     case DA9055_ADC_R_GAIN_STATUS:
1034     case DA9055_DAC_L_GAIN_STATUS:
1035     case DA9055_DAC_R_GAIN_STATUS:
1036     case DA9055_HP_L_GAIN_STATUS:
1037     case DA9055_HP_R_GAIN_STATUS:
1038     case DA9055_LINE_GAIN_STATUS:
1039     case DA9055_ALC_CIC_OP_LVL_DATA:
1040         return true;
1041     default:
1042         return false;
1043     }
1044 }
1045 
1046 /* Set DAI word length */
1047 static int da9055_hw_params(struct snd_pcm_substream *substream,
1048                 struct snd_pcm_hw_params *params,
1049                 struct snd_soc_dai *dai)
1050 {
1051     struct snd_soc_component *component = dai->component;
1052     struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1053     u8 aif_ctrl, fs;
1054     u32 sysclk;
1055 
1056     switch (params_width(params)) {
1057     case 16:
1058         aif_ctrl = DA9055_AIF_WORD_S16_LE;
1059         break;
1060     case 20:
1061         aif_ctrl = DA9055_AIF_WORD_S20_3LE;
1062         break;
1063     case 24:
1064         aif_ctrl = DA9055_AIF_WORD_S24_LE;
1065         break;
1066     case 32:
1067         aif_ctrl = DA9055_AIF_WORD_S32_LE;
1068         break;
1069     default:
1070         return -EINVAL;
1071     }
1072 
1073     /* Set AIF format */
1074     snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
1075                 aif_ctrl);
1076 
1077     switch (params_rate(params)) {
1078     case 8000:
1079         fs      = DA9055_SR_8000;
1080         sysclk      = 3072000;
1081         break;
1082     case 11025:
1083         fs      = DA9055_SR_11025;
1084         sysclk      = 2822400;
1085         break;
1086     case 12000:
1087         fs      = DA9055_SR_12000;
1088         sysclk      = 3072000;
1089         break;
1090     case 16000:
1091         fs      = DA9055_SR_16000;
1092         sysclk      = 3072000;
1093         break;
1094     case 22050:
1095         fs      = DA9055_SR_22050;
1096         sysclk      = 2822400;
1097         break;
1098     case 32000:
1099         fs      = DA9055_SR_32000;
1100         sysclk      = 3072000;
1101         break;
1102     case 44100:
1103         fs      = DA9055_SR_44100;
1104         sysclk      = 2822400;
1105         break;
1106     case 48000:
1107         fs      = DA9055_SR_48000;
1108         sysclk      = 3072000;
1109         break;
1110     case 88200:
1111         fs      = DA9055_SR_88200;
1112         sysclk      = 2822400;
1113         break;
1114     case 96000:
1115         fs      = DA9055_SR_96000;
1116         sysclk      = 3072000;
1117         break;
1118     default:
1119         return -EINVAL;
1120     }
1121 
1122     if (da9055->mclk_rate) {
1123         /* PLL Mode, Write actual FS */
1124         snd_soc_component_write(component, DA9055_SR, fs);
1125     } else {
1126         /*
1127          * Non-PLL Mode
1128          * When PLL is bypassed, chip assumes constant MCLK of
1129          * 12.288MHz and uses sample rate value to divide this MCLK
1130          * to derive its sys clk. As sys clk has to be 256 * Fs, we
1131          * need to write constant sample rate i.e. 48KHz.
1132          */
1133         snd_soc_component_write(component, DA9055_SR, DA9055_SR_48000);
1134     }
1135 
1136     if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
1137         /* PLL Mode */
1138         if (!da9055->master) {
1139             /* PLL slave mode, enable PLL and also SRM */
1140             snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
1141                         DA9055_PLL_EN | DA9055_PLL_SRM_EN,
1142                         DA9055_PLL_EN | DA9055_PLL_SRM_EN);
1143         } else {
1144             /* PLL master mode, only enable PLL */
1145             snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
1146                         DA9055_PLL_EN, DA9055_PLL_EN);
1147         }
1148     } else {
1149         /* Non PLL Mode, disable PLL */
1150         snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1151     }
1152 
1153     return 0;
1154 }
1155 
1156 /* Set DAI mode and Format */
1157 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1158 {
1159     struct snd_soc_component *component = codec_dai->component;
1160     struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1161     u8 aif_clk_mode, aif_ctrl, mode;
1162 
1163     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1164     case SND_SOC_DAIFMT_CBM_CFM:
1165         /* DA9055 in I2S Master Mode */
1166         mode = 1;
1167         aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
1168         break;
1169     case SND_SOC_DAIFMT_CBS_CFS:
1170         /* DA9055 in I2S Slave Mode */
1171         mode = 0;
1172         aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
1173         break;
1174     default:
1175         return -EINVAL;
1176     }
1177 
1178     /* Don't allow change of mode if PLL is enabled */
1179     if ((snd_soc_component_read(component, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
1180         (da9055->master != mode))
1181         return -EINVAL;
1182 
1183     da9055->master = mode;
1184 
1185     /* Only I2S is supported */
1186     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1187     case SND_SOC_DAIFMT_I2S:
1188         aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
1189         break;
1190     case SND_SOC_DAIFMT_LEFT_J:
1191         aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
1192         break;
1193     case SND_SOC_DAIFMT_RIGHT_J:
1194         aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
1195         break;
1196     case SND_SOC_DAIFMT_DSP_A:
1197         aif_ctrl = DA9055_AIF_FORMAT_DSP;
1198         break;
1199     default:
1200         return -EINVAL;
1201     }
1202 
1203     /* By default only 32 BCLK per WCLK is supported */
1204     aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
1205 
1206     snd_soc_component_update_bits(component, DA9055_AIF_CLK_MODE,
1207                 (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
1208                 aif_clk_mode);
1209     snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
1210                 aif_ctrl);
1211     return 0;
1212 }
1213 
1214 static int da9055_mute(struct snd_soc_dai *dai, int mute, int direction)
1215 {
1216     struct snd_soc_component *component = dai->component;
1217 
1218     if (mute) {
1219         snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1220                     DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
1221         snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1222                     DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
1223     } else {
1224         snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1225                     DA9055_DAC_L_MUTE_EN, 0);
1226         snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1227                     DA9055_DAC_R_MUTE_EN, 0);
1228     }
1229 
1230     return 0;
1231 }
1232 
1233 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1234             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1235 
1236 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1237                  int clk_id, unsigned int freq, int dir)
1238 {
1239     struct snd_soc_component *component = codec_dai->component;
1240     struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1241 
1242     switch (clk_id) {
1243     case DA9055_CLKSRC_MCLK:
1244         switch (freq) {
1245         case 11289600:
1246         case 12000000:
1247         case 12288000:
1248         case 13000000:
1249         case 13500000:
1250         case 14400000:
1251         case 19200000:
1252         case 19680000:
1253         case 19800000:
1254             da9055->mclk_rate = freq;
1255             return 0;
1256         default:
1257             dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1258                 freq);
1259             return -EINVAL;
1260         }
1261         break;
1262     default:
1263         dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1264         return -EINVAL;
1265     }
1266 }
1267 
1268 /*
1269  * da9055_set_dai_pll   : Configure the codec PLL
1270  * @param codec_dai : Pointer to codec DAI
1271  * @param pll_id    : da9055 has only one pll, so pll_id is always zero
1272  * @param fref      : Input MCLK frequency
1273  * @param fout      : FsDM value
1274  * @return int      : Zero for success, negative error code for error
1275  *
1276  * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1277  *   13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
1278  */
1279 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1280                   int source, unsigned int fref, unsigned int fout)
1281 {
1282     struct snd_soc_component *component = codec_dai->component;
1283     struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1284 
1285     u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
1286 
1287     /* Disable PLL before setting the divisors */
1288     snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1289 
1290     /* In slave mode, there is only one set of divisors */
1291     if (!da9055->master && (fout != 2822400))
1292         goto pll_err;
1293 
1294     /* Search pll div array for correct divisors */
1295     for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
1296         /* Check fref, mode  and fout */
1297         if ((fref == da9055_pll_div[cnt].fref) &&
1298             (da9055->master ==  da9055_pll_div[cnt].mode) &&
1299             (fout == da9055_pll_div[cnt].fout)) {
1300             /* All match, pick up divisors */
1301             pll_frac_top = da9055_pll_div[cnt].frac_top;
1302             pll_frac_bot = da9055_pll_div[cnt].frac_bot;
1303             pll_integer = da9055_pll_div[cnt].integer;
1304             break;
1305         }
1306     }
1307     if (cnt >= ARRAY_SIZE(da9055_pll_div))
1308         goto pll_err;
1309 
1310     /* Write PLL dividers */
1311     snd_soc_component_write(component, DA9055_PLL_FRAC_TOP, pll_frac_top);
1312     snd_soc_component_write(component, DA9055_PLL_FRAC_BOT, pll_frac_bot);
1313     snd_soc_component_write(component, DA9055_PLL_INTEGER, pll_integer);
1314 
1315     return 0;
1316 pll_err:
1317     dev_err(codec_dai->dev, "Error in setting up PLL\n");
1318     return -EINVAL;
1319 }
1320 
1321 /* DAI operations */
1322 static const struct snd_soc_dai_ops da9055_dai_ops = {
1323     .hw_params  = da9055_hw_params,
1324     .set_fmt    = da9055_set_dai_fmt,
1325     .set_sysclk = da9055_set_dai_sysclk,
1326     .set_pll    = da9055_set_dai_pll,
1327     .mute_stream    = da9055_mute,
1328     .no_capture_mute = 1,
1329 };
1330 
1331 static struct snd_soc_dai_driver da9055_dai = {
1332     .name = "da9055-hifi",
1333     /* Playback Capabilities */
1334     .playback = {
1335         .stream_name = "Playback",
1336         .channels_min = 1,
1337         .channels_max = 2,
1338         .rates = SNDRV_PCM_RATE_8000_96000,
1339         .formats = DA9055_FORMATS,
1340     },
1341     /* Capture Capabilities */
1342     .capture = {
1343         .stream_name = "Capture",
1344         .channels_min = 1,
1345         .channels_max = 2,
1346         .rates = SNDRV_PCM_RATE_8000_96000,
1347         .formats = DA9055_FORMATS,
1348     },
1349     .ops = &da9055_dai_ops,
1350     .symmetric_rate = 1,
1351 };
1352 
1353 static int da9055_set_bias_level(struct snd_soc_component *component,
1354                  enum snd_soc_bias_level level)
1355 {
1356     switch (level) {
1357     case SND_SOC_BIAS_ON:
1358     case SND_SOC_BIAS_PREPARE:
1359         break;
1360     case SND_SOC_BIAS_STANDBY:
1361         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1362             /* Enable VMID reference & master bias */
1363             snd_soc_component_update_bits(component, DA9055_REFERENCES,
1364                         DA9055_VMID_EN | DA9055_BIAS_EN,
1365                         DA9055_VMID_EN | DA9055_BIAS_EN);
1366         }
1367         break;
1368     case SND_SOC_BIAS_OFF:
1369         /* Disable VMID reference & master bias */
1370         snd_soc_component_update_bits(component, DA9055_REFERENCES,
1371                     DA9055_VMID_EN | DA9055_BIAS_EN, 0);
1372         break;
1373     }
1374     return 0;
1375 }
1376 
1377 static int da9055_probe(struct snd_soc_component *component)
1378 {
1379     struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
1380 
1381     /* Enable all Gain Ramps */
1382     snd_soc_component_update_bits(component, DA9055_AUX_L_CTRL,
1383                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1384     snd_soc_component_update_bits(component, DA9055_AUX_R_CTRL,
1385                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1386     snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
1387                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1388     snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
1389                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1390     snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
1391                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1392     snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
1393                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1394     snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
1395                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1396     snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
1397                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1398     snd_soc_component_update_bits(component, DA9055_HP_L_CTRL,
1399                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1400     snd_soc_component_update_bits(component, DA9055_HP_R_CTRL,
1401                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1402     snd_soc_component_update_bits(component, DA9055_LINE_CTRL,
1403                 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1404 
1405     /*
1406      * There are two separate control bits for input and output mixers.
1407      * One to enable corresponding amplifier and other to enable its
1408      * output. As amplifier bits are related to power control, they are
1409      * being managed by DAPM while other (non power related) bits are
1410      * enabled here
1411      */
1412     snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
1413                 DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
1414     snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
1415                 DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
1416 
1417     snd_soc_component_update_bits(component, DA9055_MIXOUT_L_CTRL,
1418                 DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
1419     snd_soc_component_update_bits(component, DA9055_MIXOUT_R_CTRL,
1420                 DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
1421 
1422     /* Set this as per your system configuration */
1423     snd_soc_component_write(component, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
1424 
1425     /* Set platform data values */
1426     if (da9055->pdata) {
1427         /* set mic bias source */
1428         if (da9055->pdata->micbias_source) {
1429             snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
1430                         DA9055_MICBIAS2_EN,
1431                         DA9055_MICBIAS2_EN);
1432         } else {
1433             snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
1434                         DA9055_MICBIAS2_EN, 0);
1435         }
1436         /* set mic bias voltage */
1437         switch (da9055->pdata->micbias) {
1438         case DA9055_MICBIAS_2_2V:
1439         case DA9055_MICBIAS_2_1V:
1440         case DA9055_MICBIAS_1_8V:
1441         case DA9055_MICBIAS_1_6V:
1442             snd_soc_component_update_bits(component, DA9055_MIC_CONFIG,
1443                         DA9055_MICBIAS_LEVEL_MASK,
1444                         (da9055->pdata->micbias) << 4);
1445             break;
1446         }
1447     }
1448     return 0;
1449 }
1450 
1451 static const struct snd_soc_component_driver soc_component_dev_da9055 = {
1452     .probe          = da9055_probe,
1453     .set_bias_level     = da9055_set_bias_level,
1454     .controls       = da9055_snd_controls,
1455     .num_controls       = ARRAY_SIZE(da9055_snd_controls),
1456     .dapm_widgets       = da9055_dapm_widgets,
1457     .num_dapm_widgets   = ARRAY_SIZE(da9055_dapm_widgets),
1458     .dapm_routes        = da9055_audio_map,
1459     .num_dapm_routes    = ARRAY_SIZE(da9055_audio_map),
1460     .idle_bias_on       = 1,
1461     .use_pmdown_time    = 1,
1462     .endianness     = 1,
1463 };
1464 
1465 static const struct regmap_config da9055_regmap_config = {
1466     .reg_bits = 8,
1467     .val_bits = 8,
1468 
1469     .reg_defaults = da9055_reg_defaults,
1470     .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
1471     .volatile_reg = da9055_volatile_register,
1472     .cache_type = REGCACHE_RBTREE,
1473 };
1474 
1475 static int da9055_i2c_probe(struct i2c_client *i2c)
1476 {
1477     struct da9055_priv *da9055;
1478     struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
1479     int ret;
1480 
1481     da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
1482                   GFP_KERNEL);
1483     if (!da9055)
1484         return -ENOMEM;
1485 
1486     if (pdata)
1487         da9055->pdata = pdata;
1488 
1489     i2c_set_clientdata(i2c, da9055);
1490 
1491     da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
1492     if (IS_ERR(da9055->regmap)) {
1493         ret = PTR_ERR(da9055->regmap);
1494         dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1495         return ret;
1496     }
1497 
1498     ret = devm_snd_soc_register_component(&i2c->dev,
1499             &soc_component_dev_da9055, &da9055_dai, 1);
1500     if (ret < 0) {
1501         dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",
1502             ret);
1503     }
1504     return ret;
1505 }
1506 
1507 /*
1508  * DO NOT change the device Ids. The naming is intentionally specific as both
1509  * the CODEC and PMIC parts of this chip are instantiated separately as I2C
1510  * devices (both have configurable I2C addresses, and are to all intents and
1511  * purposes separate). As a result there are specific DA9055 Ids for CODEC
1512  * and PMIC, which must be different to operate together.
1513  */
1514 static const struct i2c_device_id da9055_i2c_id[] = {
1515     { "da9055-codec", 0 },
1516     { }
1517 };
1518 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
1519 
1520 #ifdef CONFIG_OF
1521 static const struct of_device_id da9055_of_match[] = {
1522     { .compatible = "dlg,da9055-codec", },
1523     { }
1524 };
1525 MODULE_DEVICE_TABLE(of, da9055_of_match);
1526 #endif
1527 
1528 /* I2C codec control layer */
1529 static struct i2c_driver da9055_i2c_driver = {
1530     .driver = {
1531         .name = "da9055-codec",
1532         .of_match_table = of_match_ptr(da9055_of_match),
1533     },
1534     .probe_new  = da9055_i2c_probe,
1535     .id_table   = da9055_i2c_id,
1536 };
1537 
1538 module_i2c_driver(da9055_i2c_driver);
1539 
1540 MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
1541 MODULE_AUTHOR("David Chen, Ashish Chavan");
1542 MODULE_LICENSE("GPL");
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