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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // ALSA SoC CX20721/CX20723 codec driver
0004 //
0005 // Copyright:   (C) 2017 Conexant Systems, Inc.
0006 // Author:  Simon Ho, <Simon.ho@conexant.com>
0007 //
0008 // TODO: add support for TDM mode.
0009 //
0010 
0011 #include <linux/acpi.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/gpio.h>
0015 #include <linux/init.h>
0016 #include <linux/i2c.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/regmap.h>
0022 #include <linux/slab.h>
0023 #include <sound/core.h>
0024 #include <sound/initval.h>
0025 #include <sound/jack.h>
0026 #include <sound/pcm.h>
0027 #include <sound/pcm_params.h>
0028 #include <sound/tlv.h>
0029 #include <sound/soc.h>
0030 #include <sound/soc-dapm.h>
0031 #include "cx2072x.h"
0032 
0033 #define PLL_OUT_HZ_48   (1024 * 3 * 48000)
0034 #define BITS_PER_SLOT   8
0035 
0036 /* codec private data */
0037 struct cx2072x_priv {
0038     struct regmap *regmap;
0039     struct clk *mclk;
0040     unsigned int mclk_rate;
0041     struct device *dev;
0042     struct snd_soc_component *codec;
0043     struct snd_soc_jack_gpio jack_gpio;
0044     struct mutex lock;
0045     unsigned int bclk_ratio;
0046     bool pll_changed;
0047     bool i2spcm_changed;
0048     int sample_size;
0049     int frame_size;
0050     int sample_rate;
0051     unsigned int dai_fmt;
0052     bool en_aec_ref;
0053 };
0054 
0055 /*
0056  * DAC/ADC Volume
0057  *
0058  * max : 74 : 0 dB
0059  *   ( in 1 dB  step )
0060  * min : 0 : -74 dB
0061  */
0062 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
0063 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
0064 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
0065 
0066 struct cx2072x_eq_ctrl {
0067     u8 ch;
0068     u8 band;
0069 };
0070 
0071 static const DECLARE_TLV_DB_RANGE(hpf_tlv,
0072     0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
0073     1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
0074 );
0075 
0076 /* Lookup table for PRE_DIV */
0077 static const struct {
0078     unsigned int mclk;
0079     unsigned int div;
0080 } mclk_pre_div[] = {
0081     { 6144000, 1 },
0082     { 12288000, 2 },
0083     { 19200000, 3 },
0084     { 26000000, 4 },
0085     { 28224000, 5 },
0086     { 36864000, 6 },
0087     { 36864000, 7 },
0088     { 48000000, 8 },
0089     { 49152000, 8 },
0090 };
0091 
0092 /*
0093  * cx2072x register cache.
0094  */
0095 static const struct reg_default cx2072x_reg_defaults[] = {
0096     { CX2072X_AFG_POWER_STATE, 0x00000003 },
0097     { CX2072X_UM_RESPONSE, 0x00000000 },
0098     { CX2072X_GPIO_DATA, 0x00000000 },
0099     { CX2072X_GPIO_ENABLE, 0x00000000 },
0100     { CX2072X_GPIO_DIRECTION, 0x00000000 },
0101     { CX2072X_GPIO_WAKE, 0x00000000 },
0102     { CX2072X_GPIO_UM_ENABLE, 0x00000000 },
0103     { CX2072X_GPIO_STICKY_MASK, 0x00000000 },
0104     { CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
0105     { CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
0106     { CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
0107     { CX2072X_DAC1_POWER_STATE, 0x00000433 },
0108     { CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
0109     { CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
0110     { CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
0111     { CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
0112     { CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
0113     { CX2072X_DAC2_POWER_STATE, 0x00000433 },
0114     { CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
0115     { CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
0116     { CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
0117     { CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
0118     { CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
0119     { CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
0120     { CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
0121     { CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
0122     { CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
0123     { CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
0124     { CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
0125     { CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
0126     { CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
0127     { CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
0128     { CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
0129     { CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
0130     { CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
0131     { CX2072X_ADC1_POWER_STATE, 0x00000433 },
0132     { CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
0133     { CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
0134     { CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
0135     { CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
0136     { CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
0137     { CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
0138     { CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
0139     { CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
0140     { CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
0141     { CX2072X_ADC2_POWER_STATE, 0x00000433 },
0142     { CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
0143     { CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
0144     { CX2072X_PORTA_POWER_STATE, 0x00000433 },
0145     { CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
0146     { CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
0147     { CX2072X_PORTA_PIN_SENSE, 0x00000000 },
0148     { CX2072X_PORTA_EAPD_BTL, 0x00000002 },
0149     { CX2072X_PORTB_POWER_STATE, 0x00000433 },
0150     { CX2072X_PORTB_PIN_CTRL, 0x00000000 },
0151     { CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
0152     { CX2072X_PORTB_PIN_SENSE, 0x00000000 },
0153     { CX2072X_PORTB_EAPD_BTL, 0x00000002 },
0154     { CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
0155     { CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
0156     { CX2072X_PORTC_POWER_STATE, 0x00000433 },
0157     { CX2072X_PORTC_PIN_CTRL, 0x00000000 },
0158     { CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
0159     { CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
0160     { CX2072X_PORTD_POWER_STATE, 0x00000433 },
0161     { CX2072X_PORTD_PIN_CTRL, 0x00000020 },
0162     { CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
0163     { CX2072X_PORTD_PIN_SENSE, 0x00000000 },
0164     { CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
0165     { CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
0166     { CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
0167     { CX2072X_PORTE_POWER_STATE, 0x00000433 },
0168     { CX2072X_PORTE_PIN_CTRL, 0x00000040 },
0169     { CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
0170     { CX2072X_PORTE_PIN_SENSE, 0x00000000 },
0171     { CX2072X_PORTE_EAPD_BTL, 0x00000002 },
0172     { CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
0173     { CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
0174     { CX2072X_PORTF_POWER_STATE, 0x00000433 },
0175     { CX2072X_PORTF_PIN_CTRL, 0x00000000 },
0176     { CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
0177     { CX2072X_PORTF_PIN_SENSE, 0x00000000 },
0178     { CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
0179     { CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
0180     { CX2072X_PORTG_POWER_STATE, 0x00000433 },
0181     { CX2072X_PORTG_PIN_CTRL, 0x00000040 },
0182     { CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
0183     { CX2072X_PORTG_EAPD_BTL, 0x00000002 },
0184     { CX2072X_PORTM_POWER_STATE, 0x00000433 },
0185     { CX2072X_PORTM_PIN_CTRL, 0x00000000 },
0186     { CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
0187     { CX2072X_PORTM_EAPD_BTL, 0x00000002 },
0188     { CX2072X_MIXER_POWER_STATE, 0x00000433 },
0189     { CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
0190     { CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
0191     { CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
0192     { CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
0193     { CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
0194     { CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
0195     { CX2072X_SPKR_DRC_TEST, 0x00000000 },
0196     { CX2072X_DIGITAL_BIOS_TEST0, 0x001f008a },
0197     { CX2072X_DIGITAL_BIOS_TEST2, 0x00990026 },
0198     { CX2072X_I2SPCM_CONTROL1, 0x00010001 },
0199     { CX2072X_I2SPCM_CONTROL2, 0x00000000 },
0200     { CX2072X_I2SPCM_CONTROL3, 0x00000000 },
0201     { CX2072X_I2SPCM_CONTROL4, 0x00000000 },
0202     { CX2072X_I2SPCM_CONTROL5, 0x00000000 },
0203     { CX2072X_I2SPCM_CONTROL6, 0x00000000 },
0204     { CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
0205     { CX2072X_CODEC_TEST2, 0x00000000 },
0206     { CX2072X_CODEC_TEST9, 0x00000004 },
0207     { CX2072X_CODEC_TEST20, 0x00000600 },
0208     { CX2072X_CODEC_TEST26, 0x00000208 },
0209     { CX2072X_ANALOG_TEST4, 0x00000000 },
0210     { CX2072X_ANALOG_TEST5, 0x00000000 },
0211     { CX2072X_ANALOG_TEST6, 0x0000059a },
0212     { CX2072X_ANALOG_TEST7, 0x000000a7 },
0213     { CX2072X_ANALOG_TEST8, 0x00000017 },
0214     { CX2072X_ANALOG_TEST9, 0x00000000 },
0215     { CX2072X_ANALOG_TEST10, 0x00000285 },
0216     { CX2072X_ANALOG_TEST11, 0x00000000 },
0217     { CX2072X_ANALOG_TEST12, 0x00000000 },
0218     { CX2072X_ANALOG_TEST13, 0x00000000 },
0219     { CX2072X_DIGITAL_TEST1, 0x00000242 },
0220     { CX2072X_DIGITAL_TEST11, 0x00000000 },
0221     { CX2072X_DIGITAL_TEST12, 0x00000084 },
0222     { CX2072X_DIGITAL_TEST15, 0x00000077 },
0223     { CX2072X_DIGITAL_TEST16, 0x00000021 },
0224     { CX2072X_DIGITAL_TEST17, 0x00000018 },
0225     { CX2072X_DIGITAL_TEST18, 0x00000024 },
0226     { CX2072X_DIGITAL_TEST19, 0x00000001 },
0227     { CX2072X_DIGITAL_TEST20, 0x00000002 },
0228 };
0229 
0230 /*
0231  * register initialization
0232  */
0233 static const struct reg_sequence cx2072x_reg_init[] = {
0234     { CX2072X_ANALOG_TEST9, 0x080 },    /* DC offset Calibration */
0235     { CX2072X_CODEC_TEST26, 0x65f },    /* Disable the PA */
0236     { CX2072X_ANALOG_TEST10, 0x289 },   /* Set the speaker output gain */
0237     { CX2072X_CODEC_TEST20, 0xf05 },
0238     { CX2072X_CODEC_TESTXX, 0x380 },
0239     { CX2072X_CODEC_TEST26, 0xb90 },
0240     { CX2072X_CODEC_TEST9,  0x001 },    /* Enable 30 Hz High pass filter */
0241     { CX2072X_ANALOG_TEST3, 0x300 },    /* Disable PCBEEP pad */
0242     { CX2072X_CODEC_TEST24, 0x100 },    /* Disable SnM mode */
0243     { CX2072X_PORTD_PIN_CTRL, 0x020 },  /* Enable PortD input */
0244     { CX2072X_GPIO_ENABLE,  0x040 },    /* Enable GPIO7 pin for button */
0245     { CX2072X_GPIO_UM_ENABLE, 0x040 },  /* Enable UM for GPIO7 */
0246     { CX2072X_UM_RESPONSE,  0x080 },    /* Enable button response */
0247     { CX2072X_DIGITAL_TEST12, 0x0c4 },  /* Enable headset button */
0248     { CX2072X_DIGITAL_TEST0, 0x415 },   /* Power down class-D during idle */
0249     { CX2072X_I2SPCM_CONTROL2, 0x00f }, /* Enable I2S TX */
0250     { CX2072X_I2SPCM_CONTROL3, 0x00f }, /* Enable I2S RX */
0251 };
0252 
0253 static unsigned int cx2072x_register_size(unsigned int reg)
0254 {
0255     switch (reg) {
0256     case CX2072X_VENDOR_ID:
0257     case CX2072X_REVISION_ID:
0258     case CX2072X_PORTA_PIN_SENSE:
0259     case CX2072X_PORTB_PIN_SENSE:
0260     case CX2072X_PORTD_PIN_SENSE:
0261     case CX2072X_PORTE_PIN_SENSE:
0262     case CX2072X_PORTF_PIN_SENSE:
0263     case CX2072X_I2SPCM_CONTROL1:
0264     case CX2072X_I2SPCM_CONTROL2:
0265     case CX2072X_I2SPCM_CONTROL3:
0266     case CX2072X_I2SPCM_CONTROL4:
0267     case CX2072X_I2SPCM_CONTROL5:
0268     case CX2072X_I2SPCM_CONTROL6:
0269     case CX2072X_UM_INTERRUPT_CRTL_E:
0270     case CX2072X_EQ_G_COEFF:
0271     case CX2072X_SPKR_DRC_CONTROL:
0272     case CX2072X_SPKR_DRC_TEST:
0273     case CX2072X_DIGITAL_BIOS_TEST0:
0274     case CX2072X_DIGITAL_BIOS_TEST2:
0275         return 4;
0276     case CX2072X_EQ_ENABLE_BYPASS:
0277     case CX2072X_EQ_B0_COEFF:
0278     case CX2072X_EQ_B1_COEFF:
0279     case CX2072X_EQ_B2_COEFF:
0280     case CX2072X_EQ_A1_COEFF:
0281     case CX2072X_EQ_A2_COEFF:
0282     case CX2072X_DAC1_CONVERTER_FORMAT:
0283     case CX2072X_DAC2_CONVERTER_FORMAT:
0284     case CX2072X_ADC1_CONVERTER_FORMAT:
0285     case CX2072X_ADC2_CONVERTER_FORMAT:
0286     case CX2072X_CODEC_TEST2:
0287     case CX2072X_CODEC_TEST9:
0288     case CX2072X_CODEC_TEST20:
0289     case CX2072X_CODEC_TEST26:
0290     case CX2072X_ANALOG_TEST3:
0291     case CX2072X_ANALOG_TEST4:
0292     case CX2072X_ANALOG_TEST5:
0293     case CX2072X_ANALOG_TEST6:
0294     case CX2072X_ANALOG_TEST7:
0295     case CX2072X_ANALOG_TEST8:
0296     case CX2072X_ANALOG_TEST9:
0297     case CX2072X_ANALOG_TEST10:
0298     case CX2072X_ANALOG_TEST11:
0299     case CX2072X_ANALOG_TEST12:
0300     case CX2072X_ANALOG_TEST13:
0301     case CX2072X_DIGITAL_TEST0:
0302     case CX2072X_DIGITAL_TEST1:
0303     case CX2072X_DIGITAL_TEST11:
0304     case CX2072X_DIGITAL_TEST12:
0305     case CX2072X_DIGITAL_TEST15:
0306     case CX2072X_DIGITAL_TEST16:
0307     case CX2072X_DIGITAL_TEST17:
0308     case CX2072X_DIGITAL_TEST18:
0309     case CX2072X_DIGITAL_TEST19:
0310     case CX2072X_DIGITAL_TEST20:
0311         return 2;
0312     default:
0313         return 1;
0314     }
0315 }
0316 
0317 static bool cx2072x_readable_register(struct device *dev, unsigned int reg)
0318 {
0319     switch (reg) {
0320     case CX2072X_VENDOR_ID:
0321     case CX2072X_REVISION_ID:
0322     case CX2072X_CURRENT_BCLK_FREQUENCY:
0323     case CX2072X_AFG_POWER_STATE:
0324     case CX2072X_UM_RESPONSE:
0325     case CX2072X_GPIO_DATA:
0326     case CX2072X_GPIO_ENABLE:
0327     case CX2072X_GPIO_DIRECTION:
0328     case CX2072X_GPIO_WAKE:
0329     case CX2072X_GPIO_UM_ENABLE:
0330     case CX2072X_GPIO_STICKY_MASK:
0331     case CX2072X_DAC1_CONVERTER_FORMAT:
0332     case CX2072X_DAC1_AMP_GAIN_RIGHT:
0333     case CX2072X_DAC1_AMP_GAIN_LEFT:
0334     case CX2072X_DAC1_POWER_STATE:
0335     case CX2072X_DAC1_CONVERTER_STREAM_CHANNEL:
0336     case CX2072X_DAC1_EAPD_ENABLE:
0337     case CX2072X_DAC2_CONVERTER_FORMAT:
0338     case CX2072X_DAC2_AMP_GAIN_RIGHT:
0339     case CX2072X_DAC2_AMP_GAIN_LEFT:
0340     case CX2072X_DAC2_POWER_STATE:
0341     case CX2072X_DAC2_CONVERTER_STREAM_CHANNEL:
0342     case CX2072X_ADC1_CONVERTER_FORMAT:
0343     case CX2072X_ADC1_AMP_GAIN_RIGHT_0:
0344     case CX2072X_ADC1_AMP_GAIN_LEFT_0:
0345     case CX2072X_ADC1_AMP_GAIN_RIGHT_1:
0346     case CX2072X_ADC1_AMP_GAIN_LEFT_1:
0347     case CX2072X_ADC1_AMP_GAIN_RIGHT_2:
0348     case CX2072X_ADC1_AMP_GAIN_LEFT_2:
0349     case CX2072X_ADC1_AMP_GAIN_RIGHT_3:
0350     case CX2072X_ADC1_AMP_GAIN_LEFT_3:
0351     case CX2072X_ADC1_AMP_GAIN_RIGHT_4:
0352     case CX2072X_ADC1_AMP_GAIN_LEFT_4:
0353     case CX2072X_ADC1_AMP_GAIN_RIGHT_5:
0354     case CX2072X_ADC1_AMP_GAIN_LEFT_5:
0355     case CX2072X_ADC1_AMP_GAIN_RIGHT_6:
0356     case CX2072X_ADC1_AMP_GAIN_LEFT_6:
0357     case CX2072X_ADC1_CONNECTION_SELECT_CONTROL:
0358     case CX2072X_ADC1_POWER_STATE:
0359     case CX2072X_ADC1_CONVERTER_STREAM_CHANNEL:
0360     case CX2072X_ADC2_CONVERTER_FORMAT:
0361     case CX2072X_ADC2_AMP_GAIN_RIGHT_0:
0362     case CX2072X_ADC2_AMP_GAIN_LEFT_0:
0363     case CX2072X_ADC2_AMP_GAIN_RIGHT_1:
0364     case CX2072X_ADC2_AMP_GAIN_LEFT_1:
0365     case CX2072X_ADC2_AMP_GAIN_RIGHT_2:
0366     case CX2072X_ADC2_AMP_GAIN_LEFT_2:
0367     case CX2072X_ADC2_CONNECTION_SELECT_CONTROL:
0368     case CX2072X_ADC2_POWER_STATE:
0369     case CX2072X_ADC2_CONVERTER_STREAM_CHANNEL:
0370     case CX2072X_PORTA_CONNECTION_SELECT_CTRL:
0371     case CX2072X_PORTA_POWER_STATE:
0372     case CX2072X_PORTA_PIN_CTRL:
0373     case CX2072X_PORTA_UNSOLICITED_RESPONSE:
0374     case CX2072X_PORTA_PIN_SENSE:
0375     case CX2072X_PORTA_EAPD_BTL:
0376     case CX2072X_PORTB_POWER_STATE:
0377     case CX2072X_PORTB_PIN_CTRL:
0378     case CX2072X_PORTB_UNSOLICITED_RESPONSE:
0379     case CX2072X_PORTB_PIN_SENSE:
0380     case CX2072X_PORTB_EAPD_BTL:
0381     case CX2072X_PORTB_GAIN_RIGHT:
0382     case CX2072X_PORTB_GAIN_LEFT:
0383     case CX2072X_PORTC_POWER_STATE:
0384     case CX2072X_PORTC_PIN_CTRL:
0385     case CX2072X_PORTC_GAIN_RIGHT:
0386     case CX2072X_PORTC_GAIN_LEFT:
0387     case CX2072X_PORTD_POWER_STATE:
0388     case CX2072X_PORTD_PIN_CTRL:
0389     case CX2072X_PORTD_UNSOLICITED_RESPONSE:
0390     case CX2072X_PORTD_PIN_SENSE:
0391     case CX2072X_PORTD_GAIN_RIGHT:
0392     case CX2072X_PORTD_GAIN_LEFT:
0393     case CX2072X_PORTE_CONNECTION_SELECT_CTRL:
0394     case CX2072X_PORTE_POWER_STATE:
0395     case CX2072X_PORTE_PIN_CTRL:
0396     case CX2072X_PORTE_UNSOLICITED_RESPONSE:
0397     case CX2072X_PORTE_PIN_SENSE:
0398     case CX2072X_PORTE_EAPD_BTL:
0399     case CX2072X_PORTE_GAIN_RIGHT:
0400     case CX2072X_PORTE_GAIN_LEFT:
0401     case CX2072X_PORTF_POWER_STATE:
0402     case CX2072X_PORTF_PIN_CTRL:
0403     case CX2072X_PORTF_UNSOLICITED_RESPONSE:
0404     case CX2072X_PORTF_PIN_SENSE:
0405     case CX2072X_PORTF_GAIN_RIGHT:
0406     case CX2072X_PORTF_GAIN_LEFT:
0407     case CX2072X_PORTG_POWER_STATE:
0408     case CX2072X_PORTG_PIN_CTRL:
0409     case CX2072X_PORTG_CONNECTION_SELECT_CTRL:
0410     case CX2072X_PORTG_EAPD_BTL:
0411     case CX2072X_PORTM_POWER_STATE:
0412     case CX2072X_PORTM_PIN_CTRL:
0413     case CX2072X_PORTM_CONNECTION_SELECT_CTRL:
0414     case CX2072X_PORTM_EAPD_BTL:
0415     case CX2072X_MIXER_POWER_STATE:
0416     case CX2072X_MIXER_GAIN_RIGHT_0:
0417     case CX2072X_MIXER_GAIN_LEFT_0:
0418     case CX2072X_MIXER_GAIN_RIGHT_1:
0419     case CX2072X_MIXER_GAIN_LEFT_1:
0420     case CX2072X_EQ_ENABLE_BYPASS:
0421     case CX2072X_EQ_B0_COEFF:
0422     case CX2072X_EQ_B1_COEFF:
0423     case CX2072X_EQ_B2_COEFF:
0424     case CX2072X_EQ_A1_COEFF:
0425     case CX2072X_EQ_A2_COEFF:
0426     case CX2072X_EQ_G_COEFF:
0427     case CX2072X_SPKR_DRC_ENABLE_STEP:
0428     case CX2072X_SPKR_DRC_CONTROL:
0429     case CX2072X_SPKR_DRC_TEST:
0430     case CX2072X_DIGITAL_BIOS_TEST0:
0431     case CX2072X_DIGITAL_BIOS_TEST2:
0432     case CX2072X_I2SPCM_CONTROL1:
0433     case CX2072X_I2SPCM_CONTROL2:
0434     case CX2072X_I2SPCM_CONTROL3:
0435     case CX2072X_I2SPCM_CONTROL4:
0436     case CX2072X_I2SPCM_CONTROL5:
0437     case CX2072X_I2SPCM_CONTROL6:
0438     case CX2072X_UM_INTERRUPT_CRTL_E:
0439     case CX2072X_CODEC_TEST2:
0440     case CX2072X_CODEC_TEST9:
0441     case CX2072X_CODEC_TEST20:
0442     case CX2072X_CODEC_TEST26:
0443     case CX2072X_ANALOG_TEST4:
0444     case CX2072X_ANALOG_TEST5:
0445     case CX2072X_ANALOG_TEST6:
0446     case CX2072X_ANALOG_TEST7:
0447     case CX2072X_ANALOG_TEST8:
0448     case CX2072X_ANALOG_TEST9:
0449     case CX2072X_ANALOG_TEST10:
0450     case CX2072X_ANALOG_TEST11:
0451     case CX2072X_ANALOG_TEST12:
0452     case CX2072X_ANALOG_TEST13:
0453     case CX2072X_DIGITAL_TEST0:
0454     case CX2072X_DIGITAL_TEST1:
0455     case CX2072X_DIGITAL_TEST11:
0456     case CX2072X_DIGITAL_TEST12:
0457     case CX2072X_DIGITAL_TEST15:
0458     case CX2072X_DIGITAL_TEST16:
0459     case CX2072X_DIGITAL_TEST17:
0460     case CX2072X_DIGITAL_TEST18:
0461     case CX2072X_DIGITAL_TEST19:
0462     case CX2072X_DIGITAL_TEST20:
0463         return true;
0464     default:
0465         return false;
0466     }
0467 }
0468 
0469 static bool cx2072x_volatile_register(struct device *dev, unsigned int reg)
0470 {
0471     switch (reg) {
0472     case CX2072X_VENDOR_ID:
0473     case CX2072X_REVISION_ID:
0474     case CX2072X_UM_INTERRUPT_CRTL_E:
0475     case CX2072X_DIGITAL_TEST11:
0476     case CX2072X_PORTA_PIN_SENSE:
0477     case CX2072X_PORTB_PIN_SENSE:
0478     case CX2072X_PORTD_PIN_SENSE:
0479     case CX2072X_PORTE_PIN_SENSE:
0480     case CX2072X_PORTF_PIN_SENSE:
0481     case CX2072X_EQ_G_COEFF:
0482     case CX2072X_EQ_BAND:
0483         return true;
0484     default:
0485         return false;
0486     }
0487 }
0488 
0489 static int cx2072x_reg_raw_write(struct i2c_client *client,
0490                  unsigned int reg,
0491                  const void *val, size_t val_count)
0492 {
0493     struct device *dev = &client->dev;
0494     u8 buf[2 + CX2072X_MAX_EQ_COEFF];
0495     int ret;
0496 
0497     if (WARN_ON(val_count + 2 > sizeof(buf)))
0498         return -EINVAL;
0499 
0500     buf[0] = reg >> 8;
0501     buf[1] = reg & 0xff;
0502 
0503     memcpy(buf + 2, val, val_count);
0504 
0505     ret = i2c_master_send(client, buf, val_count + 2);
0506     if (ret != val_count + 2) {
0507         dev_err(dev, "I2C write failed, ret = %d\n", ret);
0508         return ret < 0 ? ret : -EIO;
0509     }
0510     return 0;
0511 }
0512 
0513 static int cx2072x_reg_write(void *context, unsigned int reg,
0514                  unsigned int value)
0515 {
0516     __le32 raw_value;
0517     unsigned int size;
0518 
0519     size = cx2072x_register_size(reg);
0520 
0521     if (reg == CX2072X_UM_INTERRUPT_CRTL_E) {
0522         /* Update the MSB byte only */
0523         reg += 3;
0524         size = 1;
0525         value >>= 24;
0526     }
0527 
0528     raw_value = cpu_to_le32(value);
0529     return cx2072x_reg_raw_write(context, reg, &raw_value, size);
0530 }
0531 
0532 static int cx2072x_reg_read(void *context, unsigned int reg,
0533                 unsigned int *value)
0534 {
0535     struct i2c_client *client = context;
0536     struct device *dev = &client->dev;
0537     __le32 recv_buf = 0;
0538     struct i2c_msg msgs[2];
0539     unsigned int size;
0540     u8 send_buf[2];
0541     int ret;
0542 
0543     size = cx2072x_register_size(reg);
0544 
0545     send_buf[0] = reg >> 8;
0546     send_buf[1] = reg & 0xff;
0547 
0548     msgs[0].addr = client->addr;
0549     msgs[0].len = sizeof(send_buf);
0550     msgs[0].buf = send_buf;
0551     msgs[0].flags = 0;
0552 
0553     msgs[1].addr = client->addr;
0554     msgs[1].len = size;
0555     msgs[1].buf = (u8 *)&recv_buf;
0556     msgs[1].flags = I2C_M_RD;
0557 
0558     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0559     if (ret != ARRAY_SIZE(msgs)) {
0560         dev_err(dev, "Failed to read register, ret = %d\n", ret);
0561         return ret < 0 ? ret : -EIO;
0562     }
0563 
0564     *value = le32_to_cpu(recv_buf);
0565     return 0;
0566 }
0567 
0568 /* get suggested pre_div valuce from mclk frequency */
0569 static unsigned int get_div_from_mclk(unsigned int mclk)
0570 {
0571     unsigned int div = 8;
0572     int i;
0573 
0574     for (i = 0; i < ARRAY_SIZE(mclk_pre_div); i++) {
0575         if (mclk <= mclk_pre_div[i].mclk) {
0576             div = mclk_pre_div[i].div;
0577             break;
0578         }
0579     }
0580     return div;
0581 }
0582 
0583 static int cx2072x_config_pll(struct cx2072x_priv *cx2072x)
0584 {
0585     struct device *dev = cx2072x->dev;
0586     unsigned int pre_div;
0587     unsigned int pre_div_val;
0588     unsigned int pll_input;
0589     unsigned int pll_output;
0590     unsigned int int_div;
0591     unsigned int frac_div;
0592     u64 frac_num;
0593     unsigned int frac;
0594     unsigned int sample_rate = cx2072x->sample_rate;
0595     int pt_sample_per_sync = 2;
0596     int pt_clock_per_sample = 96;
0597 
0598     switch (sample_rate) {
0599     case 48000:
0600     case 32000:
0601     case 24000:
0602     case 16000:
0603         break;
0604 
0605     case 96000:
0606         pt_sample_per_sync = 1;
0607         pt_clock_per_sample = 48;
0608         break;
0609 
0610     case 192000:
0611         pt_sample_per_sync = 0;
0612         pt_clock_per_sample = 24;
0613         break;
0614 
0615     default:
0616         dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
0617         return -EINVAL;
0618     }
0619 
0620     /* Configure PLL settings */
0621     pre_div = get_div_from_mclk(cx2072x->mclk_rate);
0622     pll_input = cx2072x->mclk_rate / pre_div;
0623     pll_output = sample_rate * 3072;
0624     int_div = pll_output / pll_input;
0625     frac_div = pll_output - (int_div * pll_input);
0626 
0627     if (frac_div) {
0628         frac_div *= 1000;
0629         frac_div /= pll_input;
0630         frac_num = (u64)(4000 + frac_div) * ((1 << 20) - 4);
0631         do_div(frac_num, 7);
0632         frac = ((u32)frac_num + 499) / 1000;
0633     }
0634     pre_div_val = (pre_div - 1) * 2;
0635 
0636     regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST4,
0637              0x40 | (pre_div_val << 8));
0638     if (frac_div == 0) {
0639         /* Int mode */
0640         regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100);
0641     } else {
0642         /* frac mode */
0643         regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST6,
0644                  frac & 0xfff);
0645         regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7,
0646                  (u8)(frac >> 12));
0647     }
0648 
0649     int_div--;
0650     regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST8, int_div);
0651 
0652     /* configure PLL tracking */
0653     if (frac_div == 0) {
0654         /* disable PLL tracking */
0655         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00);
0656     } else {
0657         /* configure and enable PLL tracking */
0658         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
0659                  (pt_sample_per_sync << 4) & 0xf0);
0660         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST17,
0661                  pt_clock_per_sample);
0662         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST18,
0663                  pt_clock_per_sample * 3 / 2);
0664         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01);
0665         regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02);
0666         regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
0667                    0x01, 0x01);
0668     }
0669 
0670     return 0;
0671 }
0672 
0673 static int cx2072x_config_i2spcm(struct cx2072x_priv *cx2072x)
0674 {
0675     struct device *dev = cx2072x->dev;
0676     unsigned int bclk_rate = 0;
0677     int is_i2s = 0;
0678     int has_one_bit_delay = 0;
0679     int is_frame_inv = 0;
0680     int is_bclk_inv = 0;
0681     int pulse_len;
0682     int frame_len = cx2072x->frame_size;
0683     int sample_size = cx2072x->sample_size;
0684     int i2s_right_slot;
0685     int i2s_right_pause_interval = 0;
0686     int i2s_right_pause_pos;
0687     int is_big_endian = 1;
0688     u64 div;
0689     unsigned int mod;
0690     union cx2072x_reg_i2spcm_ctrl_reg1 reg1;
0691     union cx2072x_reg_i2spcm_ctrl_reg2 reg2;
0692     union cx2072x_reg_i2spcm_ctrl_reg3 reg3;
0693     union cx2072x_reg_i2spcm_ctrl_reg4 reg4;
0694     union cx2072x_reg_i2spcm_ctrl_reg5 reg5;
0695     union cx2072x_reg_i2spcm_ctrl_reg6 reg6;
0696     union cx2072x_reg_digital_bios_test2 regdbt2;
0697     const unsigned int fmt = cx2072x->dai_fmt;
0698 
0699     if (frame_len <= 0) {
0700         dev_err(dev, "Incorrect frame len %d\n", frame_len);
0701         return -EINVAL;
0702     }
0703 
0704     if (sample_size <= 0) {
0705         dev_err(dev, "Incorrect sample size %d\n", sample_size);
0706         return -EINVAL;
0707     }
0708 
0709     dev_dbg(dev, "config_i2spcm set_dai_fmt- %08x\n", fmt);
0710 
0711     regdbt2.ulval = 0xac;
0712 
0713     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0714     case SND_SOC_DAIFMT_CBP_CFP:
0715         reg2.r.tx_master = 1;
0716         reg3.r.rx_master = 1;
0717         break;
0718 
0719     case SND_SOC_DAIFMT_CBC_CFC:
0720         reg2.r.tx_master = 0;
0721         reg3.r.rx_master = 0;
0722         break;
0723 
0724     default:
0725         dev_err(dev, "Unsupported DAI clocking mode\n");
0726         return -EINVAL;
0727     }
0728 
0729     /* set format */
0730     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0731     case SND_SOC_DAIFMT_I2S:
0732         is_i2s = 1;
0733         has_one_bit_delay = 1;
0734         pulse_len = frame_len / 2;
0735         break;
0736 
0737     case SND_SOC_DAIFMT_RIGHT_J:
0738         is_i2s = 1;
0739         pulse_len = frame_len / 2;
0740         break;
0741 
0742     case SND_SOC_DAIFMT_LEFT_J:
0743         is_i2s = 1;
0744         pulse_len = frame_len / 2;
0745         break;
0746 
0747     default:
0748         dev_err(dev, "Unsupported DAI format\n");
0749         return -EINVAL;
0750     }
0751 
0752     /* clock inversion */
0753     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0754     case SND_SOC_DAIFMT_NB_NF:
0755         is_frame_inv = is_i2s;
0756         is_bclk_inv = is_i2s;
0757         break;
0758 
0759     case SND_SOC_DAIFMT_IB_IF:
0760         is_frame_inv = !is_i2s;
0761         is_bclk_inv = !is_i2s;
0762         break;
0763 
0764     case SND_SOC_DAIFMT_IB_NF:
0765         is_frame_inv = is_i2s;
0766         is_bclk_inv = !is_i2s;
0767         break;
0768 
0769     case SND_SOC_DAIFMT_NB_IF:
0770         is_frame_inv = !is_i2s;
0771         is_bclk_inv = is_i2s;
0772         break;
0773 
0774     default:
0775         dev_err(dev, "Unsupported DAI clock inversion\n");
0776         return -EINVAL;
0777     }
0778 
0779     reg1.r.rx_data_one_line = 1;
0780     reg1.r.tx_data_one_line = 1;
0781 
0782     if (is_i2s) {
0783         i2s_right_slot = (frame_len / 2) / BITS_PER_SLOT;
0784         i2s_right_pause_interval = (frame_len / 2) % BITS_PER_SLOT;
0785         i2s_right_pause_pos = i2s_right_slot * BITS_PER_SLOT;
0786     }
0787 
0788     reg1.r.rx_ws_pol = is_frame_inv;
0789     reg1.r.rx_ws_wid = pulse_len - 1;
0790 
0791     reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1;
0792     reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1;
0793 
0794     reg1.r.tx_ws_pol = reg1.r.rx_ws_pol;
0795     reg1.r.tx_ws_wid = pulse_len - 1;
0796     reg1.r.tx_frm_len = reg1.r.rx_frm_len;
0797     reg1.r.tx_sa_size = reg1.r.rx_sa_size;
0798 
0799     reg2.r.tx_endian_sel = !is_big_endian;
0800     reg2.r.tx_dstart_dly = has_one_bit_delay;
0801     if (cx2072x->en_aec_ref)
0802         reg2.r.tx_dstart_dly = 0;
0803 
0804     reg3.r.rx_endian_sel = !is_big_endian;
0805     reg3.r.rx_dstart_dly = has_one_bit_delay;
0806 
0807     reg4.ulval = 0;
0808 
0809     if (is_i2s) {
0810         reg2.r.tx_slot_1 = 0;
0811         reg2.r.tx_slot_2 = i2s_right_slot;
0812         reg3.r.rx_slot_1 = 0;
0813         if (cx2072x->en_aec_ref)
0814             reg3.r.rx_slot_2 = 0;
0815         else
0816             reg3.r.rx_slot_2 = i2s_right_slot;
0817         reg6.r.rx_pause_start_pos = i2s_right_pause_pos;
0818         reg6.r.rx_pause_cycles = i2s_right_pause_interval;
0819         reg6.r.tx_pause_start_pos = i2s_right_pause_pos;
0820         reg6.r.tx_pause_cycles = i2s_right_pause_interval;
0821     } else {
0822         dev_err(dev, "TDM mode is not implemented yet\n");
0823         return -EINVAL;
0824     }
0825     regdbt2.r.i2s_bclk_invert = is_bclk_inv;
0826 
0827     /* Configures the BCLK output */
0828     bclk_rate = cx2072x->sample_rate * frame_len;
0829     reg5.r.i2s_pcm_clk_div_chan_en = 0;
0830 
0831     /* Disables bclk output before setting new value */
0832     regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0);
0833 
0834     if (reg2.r.tx_master) {
0835         /* Configures BCLK rate */
0836         div = PLL_OUT_HZ_48;
0837         mod = do_div(div, bclk_rate);
0838         if (mod) {
0839             dev_err(dev, "Unsupported BCLK %dHz\n", bclk_rate);
0840             return -EINVAL;
0841         }
0842         dev_dbg(dev, "enables BCLK %dHz output\n", bclk_rate);
0843         reg5.r.i2s_pcm_clk_div = (u32)div - 1;
0844         reg5.r.i2s_pcm_clk_div_chan_en = 1;
0845     }
0846 
0847     regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval);
0848     regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, 0xffffffc0,
0849                reg2.ulval);
0850     regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, 0xffffffc0,
0851                reg3.ulval);
0852     regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4, reg4.ulval);
0853     regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL6, reg6.ulval);
0854     regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
0855 
0856     regmap_write(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
0857              regdbt2.ulval);
0858 
0859     return 0;
0860 }
0861 
0862 static int afg_power_ev(struct snd_soc_dapm_widget *w,
0863             struct snd_kcontrol *kcontrol, int event)
0864 {
0865     struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
0866     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
0867 
0868     switch (event) {
0869     case SND_SOC_DAPM_POST_PMU:
0870         regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0871                    0x00, 0x10);
0872         break;
0873 
0874     case SND_SOC_DAPM_PRE_PMD:
0875         regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0876                    0x10, 0x10);
0877         break;
0878     }
0879 
0880     return 0;
0881 }
0882 
0883 static const struct snd_kcontrol_new cx2072x_snd_controls[] = {
0884     SOC_DOUBLE_R_TLV("PortD Boost Volume", CX2072X_PORTD_GAIN_LEFT,
0885              CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
0886     SOC_DOUBLE_R_TLV("PortC Boost Volume", CX2072X_PORTC_GAIN_LEFT,
0887              CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
0888     SOC_DOUBLE_R_TLV("PortB Boost Volume", CX2072X_PORTB_GAIN_LEFT,
0889              CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
0890     SOC_DOUBLE_R_TLV("PortD ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_1,
0891              CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
0892     SOC_DOUBLE_R_TLV("PortC ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_2,
0893              CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
0894     SOC_DOUBLE_R_TLV("PortB ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_0,
0895              CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
0896     SOC_DOUBLE_R_TLV("DAC1 Volume", CX2072X_DAC1_AMP_GAIN_LEFT,
0897              CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
0898     SOC_DOUBLE_R("DAC1 Switch", CX2072X_DAC1_AMP_GAIN_LEFT,
0899              CX2072X_DAC1_AMP_GAIN_RIGHT, 7,  1, 0),
0900     SOC_DOUBLE_R_TLV("DAC2 Volume", CX2072X_DAC2_AMP_GAIN_LEFT,
0901              CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
0902     SOC_SINGLE_TLV("HPF Freq", CX2072X_CODEC_TEST9, 0, 0x3f, 0, hpf_tlv),
0903     SOC_DOUBLE("HPF Switch", CX2072X_CODEC_TEST9, 8, 9, 1, 1),
0904     SOC_SINGLE("PortA HP Amp Switch", CX2072X_PORTA_PIN_CTRL, 7, 1, 0),
0905 };
0906 
0907 static int cx2072x_hw_params(struct snd_pcm_substream *substream,
0908                  struct snd_pcm_hw_params *params,
0909                  struct snd_soc_dai *dai)
0910 {
0911     struct snd_soc_component *codec = dai->component;
0912     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
0913     struct device *dev = codec->dev;
0914     const unsigned int sample_rate = params_rate(params);
0915     int sample_size, frame_size;
0916 
0917     /* Data sizes if not using TDM */
0918     sample_size = params_width(params);
0919 
0920     if (sample_size < 0)
0921         return sample_size;
0922 
0923     frame_size = snd_soc_params_to_frame_size(params);
0924     if (frame_size < 0)
0925         return frame_size;
0926 
0927     if (cx2072x->mclk_rate == 0) {
0928         dev_err(dev, "Master clock rate is not configured\n");
0929         return -EINVAL;
0930     }
0931 
0932     if (cx2072x->bclk_ratio)
0933         frame_size = cx2072x->bclk_ratio;
0934 
0935     switch (sample_rate) {
0936     case 48000:
0937     case 32000:
0938     case 24000:
0939     case 16000:
0940     case 96000:
0941     case 192000:
0942         break;
0943 
0944     default:
0945         dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
0946         return -EINVAL;
0947     }
0948 
0949     dev_dbg(dev, "Sample size %d bits, frame = %d bits, rate = %d Hz\n",
0950         sample_size, frame_size, sample_rate);
0951 
0952     cx2072x->frame_size = frame_size;
0953     cx2072x->sample_size = sample_size;
0954     cx2072x->sample_rate = sample_rate;
0955 
0956     if (dai->id == CX2072X_DAI_DSP) {
0957         cx2072x->en_aec_ref = true;
0958         dev_dbg(cx2072x->dev, "enables aec reference\n");
0959         regmap_write(cx2072x->regmap,
0960                  CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 3);
0961     }
0962 
0963     if (cx2072x->pll_changed) {
0964         cx2072x_config_pll(cx2072x);
0965         cx2072x->pll_changed = false;
0966     }
0967 
0968     if (cx2072x->i2spcm_changed) {
0969         cx2072x_config_i2spcm(cx2072x);
0970         cx2072x->i2spcm_changed = false;
0971     }
0972 
0973     return 0;
0974 }
0975 
0976 static int cx2072x_set_dai_bclk_ratio(struct snd_soc_dai *dai,
0977                       unsigned int ratio)
0978 {
0979     struct snd_soc_component *codec = dai->component;
0980     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
0981 
0982     cx2072x->bclk_ratio = ratio;
0983     return 0;
0984 }
0985 
0986 static int cx2072x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
0987                   unsigned int freq, int dir)
0988 {
0989     struct snd_soc_component *codec = dai->component;
0990     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
0991 
0992     if (clk_set_rate(cx2072x->mclk, freq)) {
0993         dev_err(codec->dev, "set clk rate failed\n");
0994         return -EINVAL;
0995     }
0996 
0997     cx2072x->mclk_rate = freq;
0998     return 0;
0999 }
1000 
1001 static int cx2072x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1002 {
1003     struct snd_soc_component *codec = dai->component;
1004     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1005     struct device *dev = codec->dev;
1006 
1007     dev_dbg(dev, "set_dai_fmt- %08x\n", fmt);
1008     /* set master/slave */
1009     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1010     case SND_SOC_DAIFMT_CBP_CFP:
1011     case SND_SOC_DAIFMT_CBC_CFC:
1012         break;
1013 
1014     default:
1015         dev_err(dev, "Unsupported DAI master mode\n");
1016         return -EINVAL;
1017     }
1018 
1019     /* set format */
1020     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1021     case SND_SOC_DAIFMT_I2S:
1022     case SND_SOC_DAIFMT_RIGHT_J:
1023     case SND_SOC_DAIFMT_LEFT_J:
1024         break;
1025 
1026     default:
1027         dev_err(dev, "Unsupported DAI format\n");
1028         return -EINVAL;
1029     }
1030 
1031     /* clock inversion */
1032     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1033     case SND_SOC_DAIFMT_NB_NF:
1034     case SND_SOC_DAIFMT_IB_IF:
1035     case SND_SOC_DAIFMT_IB_NF:
1036     case SND_SOC_DAIFMT_NB_IF:
1037         break;
1038 
1039     default:
1040         dev_err(dev, "Unsupported DAI clock inversion\n");
1041         return -EINVAL;
1042     }
1043 
1044     cx2072x->dai_fmt = fmt;
1045     return 0;
1046 }
1047 
1048 static const struct snd_kcontrol_new portaouten_ctl =
1049     SOC_DAPM_SINGLE("Switch", CX2072X_PORTA_PIN_CTRL, 6, 1, 0);
1050 
1051 static const struct snd_kcontrol_new porteouten_ctl =
1052     SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 6, 1, 0);
1053 
1054 static const struct snd_kcontrol_new portgouten_ctl =
1055     SOC_DAPM_SINGLE("Switch", CX2072X_PORTG_PIN_CTRL, 6, 1, 0);
1056 
1057 static const struct snd_kcontrol_new portmouten_ctl =
1058     SOC_DAPM_SINGLE("Switch", CX2072X_PORTM_PIN_CTRL, 6, 1, 0);
1059 
1060 static const struct snd_kcontrol_new portbinen_ctl =
1061     SOC_DAPM_SINGLE("Switch", CX2072X_PORTB_PIN_CTRL, 5, 1, 0);
1062 
1063 static const struct snd_kcontrol_new portcinen_ctl =
1064     SOC_DAPM_SINGLE("Switch", CX2072X_PORTC_PIN_CTRL, 5, 1, 0);
1065 
1066 static const struct snd_kcontrol_new portdinen_ctl =
1067     SOC_DAPM_SINGLE("Switch", CX2072X_PORTD_PIN_CTRL, 5, 1, 0);
1068 
1069 static const struct snd_kcontrol_new porteinen_ctl =
1070     SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 5, 1, 0);
1071 
1072 static const struct snd_kcontrol_new i2sadc1l_ctl =
1073     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 0, 1, 0);
1074 
1075 static const struct snd_kcontrol_new i2sadc1r_ctl =
1076     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 1, 1, 0);
1077 
1078 static const struct snd_kcontrol_new i2sadc2l_ctl =
1079     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 2, 1, 0);
1080 
1081 static const struct snd_kcontrol_new i2sadc2r_ctl =
1082     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 3, 1, 0);
1083 
1084 static const struct snd_kcontrol_new i2sdac1l_ctl =
1085     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 0, 1, 0);
1086 
1087 static const struct snd_kcontrol_new i2sdac1r_ctl =
1088     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 1, 1, 0);
1089 
1090 static const struct snd_kcontrol_new i2sdac2l_ctl =
1091     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 2, 1, 0);
1092 
1093 static const struct snd_kcontrol_new i2sdac2r_ctl =
1094     SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 3, 1, 0);
1095 
1096 static const char * const dac_enum_text[] = {
1097     "DAC1 Switch", "DAC2 Switch",
1098 };
1099 
1100 static const struct soc_enum porta_dac_enum =
1101 SOC_ENUM_SINGLE(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1102 
1103 static const struct snd_kcontrol_new porta_mux =
1104 SOC_DAPM_ENUM("PortA Mux", porta_dac_enum);
1105 
1106 static const struct soc_enum portg_dac_enum =
1107 SOC_ENUM_SINGLE(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1108 
1109 static const struct snd_kcontrol_new portg_mux =
1110 SOC_DAPM_ENUM("PortG Mux", portg_dac_enum);
1111 
1112 static const struct soc_enum porte_dac_enum =
1113 SOC_ENUM_SINGLE(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1114 
1115 static const struct snd_kcontrol_new porte_mux =
1116 SOC_DAPM_ENUM("PortE Mux", porte_dac_enum);
1117 
1118 static const struct soc_enum portm_dac_enum =
1119 SOC_ENUM_SINGLE(CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1120 
1121 static const struct snd_kcontrol_new portm_mux =
1122 SOC_DAPM_ENUM("PortM Mux", portm_dac_enum);
1123 
1124 static const char * const adc1in_sel_text[] = {
1125     "PortB Switch", "PortD Switch", "PortC Switch", "Widget15 Switch",
1126     "PortE Switch", "PortF Switch", "PortH Switch"
1127 };
1128 
1129 static const struct soc_enum adc1in_sel_enum =
1130 SOC_ENUM_SINGLE(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0, 7, adc1in_sel_text);
1131 
1132 static const struct snd_kcontrol_new adc1_mux =
1133 SOC_DAPM_ENUM("ADC1 Mux", adc1in_sel_enum);
1134 
1135 static const char * const adc2in_sel_text[] = {
1136     "PortC Switch", "Widget15 Switch", "PortH Switch"
1137 };
1138 
1139 static const struct soc_enum adc2in_sel_enum =
1140 SOC_ENUM_SINGLE(CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0, 3, adc2in_sel_text);
1141 
1142 static const struct snd_kcontrol_new adc2_mux =
1143 SOC_DAPM_ENUM("ADC2 Mux", adc2in_sel_enum);
1144 
1145 static const struct snd_kcontrol_new wid15_mix[] = {
1146     SOC_DAPM_SINGLE("DAC1L Switch", CX2072X_MIXER_GAIN_LEFT_0, 7, 1, 1),
1147     SOC_DAPM_SINGLE("DAC1R Switch", CX2072X_MIXER_GAIN_RIGHT_0, 7, 1, 1),
1148     SOC_DAPM_SINGLE("DAC2L Switch", CX2072X_MIXER_GAIN_LEFT_1, 7, 1, 1),
1149     SOC_DAPM_SINGLE("DAC2R Switch", CX2072X_MIXER_GAIN_RIGHT_1, 7, 1, 1),
1150 };
1151 
1152 #define CX2072X_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, wmask,  won_val, \
1153     woff_val, wevent, wflags) \
1154     {.id = snd_soc_dapm_supply, .name = wname, .kcontrol_news = NULL, \
1155     .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1156     .on_val = won_val, .off_val = woff_val, \
1157     .subseq = wsubseq, .event = wevent, .event_flags = wflags}
1158 
1159 #define CX2072X_DAPM_SWITCH(wname,  wreg, wshift, wmask,  won_val, woff_val, \
1160     wevent, wflags) \
1161     {.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1162     .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1163     .on_val = won_val, .off_val = woff_val, \
1164     .event = wevent, .event_flags = wflags}
1165 
1166 #define CX2072X_DAPM_SWITCH(wname,  wreg, wshift, wmask,  won_val, woff_val, \
1167     wevent, wflags) \
1168     {.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1169     .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1170     .on_val = won_val, .off_val = woff_val, \
1171     .event = wevent, .event_flags = wflags}
1172 
1173 #define CX2072X_DAPM_REG_E(wid, wname, wreg, wshift, wmask, won_val, woff_val, \
1174                 wevent, wflags) \
1175     {.id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \
1176     .reg = wreg, .shift = wshift, .mask = wmask, \
1177     .on_val = won_val, .off_val = woff_val, \
1178     .event = wevent, .event_flags = wflags}
1179 
1180 static const struct snd_soc_dapm_widget cx2072x_dapm_widgets[] = {
1181     /*Playback*/
1182     SND_SOC_DAPM_AIF_IN("In AIF", "Playback", 0, SND_SOC_NOPM, 0, 0),
1183 
1184     SND_SOC_DAPM_SWITCH("I2S DAC1L", SND_SOC_NOPM, 0, 0, &i2sdac1l_ctl),
1185     SND_SOC_DAPM_SWITCH("I2S DAC1R", SND_SOC_NOPM, 0, 0, &i2sdac1r_ctl),
1186     SND_SOC_DAPM_SWITCH("I2S DAC2L", SND_SOC_NOPM, 0, 0, &i2sdac2l_ctl),
1187     SND_SOC_DAPM_SWITCH("I2S DAC2R", SND_SOC_NOPM, 0, 0, &i2sdac2r_ctl),
1188 
1189     SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC1", CX2072X_DAC1_POWER_STATE,
1190              0, 0xfff, 0x00, 0x03),
1191 
1192     SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC2", CX2072X_DAC2_POWER_STATE,
1193              0, 0xfff, 0x00, 0x03),
1194 
1195     SND_SOC_DAPM_MUX("PortA Mux", SND_SOC_NOPM, 0, 0, &porta_mux),
1196     SND_SOC_DAPM_MUX("PortG Mux", SND_SOC_NOPM, 0, 0, &portg_mux),
1197     SND_SOC_DAPM_MUX("PortE Mux", SND_SOC_NOPM, 0, 0, &porte_mux),
1198     SND_SOC_DAPM_MUX("PortM Mux", SND_SOC_NOPM, 0, 0, &portm_mux),
1199 
1200     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortA Power",
1201              CX2072X_PORTA_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1202 
1203     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortM Power",
1204              CX2072X_PORTM_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1205 
1206     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortG Power",
1207              CX2072X_PORTG_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1208 
1209     CX2072X_DAPM_SUPPLY_S("AFG Power", 0, CX2072X_AFG_POWER_STATE,
1210                   0, 0xfff, 0x00, 0x03, afg_power_ev,
1211                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1212 
1213     SND_SOC_DAPM_SWITCH("PortA Out En", SND_SOC_NOPM, 0, 0,
1214                 &portaouten_ctl),
1215     SND_SOC_DAPM_SWITCH("PortE Out En", SND_SOC_NOPM, 0, 0,
1216                 &porteouten_ctl),
1217     SND_SOC_DAPM_SWITCH("PortG Out En", SND_SOC_NOPM, 0, 0,
1218                 &portgouten_ctl),
1219     SND_SOC_DAPM_SWITCH("PortM Out En", SND_SOC_NOPM, 0, 0,
1220                 &portmouten_ctl),
1221 
1222     SND_SOC_DAPM_OUTPUT("PORTA"),
1223     SND_SOC_DAPM_OUTPUT("PORTG"),
1224     SND_SOC_DAPM_OUTPUT("PORTE"),
1225     SND_SOC_DAPM_OUTPUT("PORTM"),
1226     SND_SOC_DAPM_OUTPUT("AEC REF"),
1227 
1228     /*Capture*/
1229     SND_SOC_DAPM_AIF_OUT("Out AIF", "Capture", 0, SND_SOC_NOPM, 0, 0),
1230 
1231     SND_SOC_DAPM_SWITCH("I2S ADC1L", SND_SOC_NOPM, 0, 0, &i2sadc1l_ctl),
1232     SND_SOC_DAPM_SWITCH("I2S ADC1R", SND_SOC_NOPM, 0, 0, &i2sadc1r_ctl),
1233     SND_SOC_DAPM_SWITCH("I2S ADC2L", SND_SOC_NOPM, 0, 0, &i2sadc2l_ctl),
1234     SND_SOC_DAPM_SWITCH("I2S ADC2R", SND_SOC_NOPM, 0, 0, &i2sadc2r_ctl),
1235 
1236     SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC1", CX2072X_ADC1_POWER_STATE,
1237              0, 0xff, 0x00, 0x03),
1238     SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2", CX2072X_ADC2_POWER_STATE,
1239              0, 0xff, 0x00, 0x03),
1240 
1241     SND_SOC_DAPM_MUX("ADC1 Mux", SND_SOC_NOPM, 0, 0, &adc1_mux),
1242     SND_SOC_DAPM_MUX("ADC2 Mux", SND_SOC_NOPM, 0, 0, &adc2_mux),
1243 
1244     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortB Power",
1245              CX2072X_PORTB_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1246     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortC Power",
1247              CX2072X_PORTC_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1248     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortD Power",
1249              CX2072X_PORTD_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1250     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "PortE Power",
1251              CX2072X_PORTE_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1252     SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Widget15 Power",
1253              CX2072X_MIXER_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1254 
1255     SND_SOC_DAPM_MIXER("Widget15 Mixer", SND_SOC_NOPM, 0, 0,
1256                wid15_mix, ARRAY_SIZE(wid15_mix)),
1257     SND_SOC_DAPM_SWITCH("PortB In En", SND_SOC_NOPM, 0, 0, &portbinen_ctl),
1258     SND_SOC_DAPM_SWITCH("PortC In En", SND_SOC_NOPM, 0, 0, &portcinen_ctl),
1259     SND_SOC_DAPM_SWITCH("PortD In En", SND_SOC_NOPM, 0, 0, &portdinen_ctl),
1260     SND_SOC_DAPM_SWITCH("PortE In En", SND_SOC_NOPM, 0, 0, &porteinen_ctl),
1261 
1262     SND_SOC_DAPM_MICBIAS("Headset Bias", CX2072X_ANALOG_TEST11, 1, 0),
1263     SND_SOC_DAPM_MICBIAS("PortB Mic Bias", CX2072X_PORTB_PIN_CTRL, 2, 0),
1264     SND_SOC_DAPM_MICBIAS("PortD Mic Bias", CX2072X_PORTD_PIN_CTRL, 2, 0),
1265     SND_SOC_DAPM_MICBIAS("PortE Mic Bias", CX2072X_PORTE_PIN_CTRL, 2, 0),
1266     SND_SOC_DAPM_INPUT("PORTB"),
1267     SND_SOC_DAPM_INPUT("PORTC"),
1268     SND_SOC_DAPM_INPUT("PORTD"),
1269     SND_SOC_DAPM_INPUT("PORTEIN"),
1270 
1271 };
1272 
1273 static const struct snd_soc_dapm_route cx2072x_intercon[] = {
1274     /* Playback */
1275     {"In AIF", NULL, "AFG Power"},
1276     {"I2S DAC1L", "Switch", "In AIF"},
1277     {"I2S DAC1R", "Switch", "In AIF"},
1278     {"I2S DAC2L", "Switch", "In AIF"},
1279     {"I2S DAC2R", "Switch", "In AIF"},
1280     {"DAC1", NULL, "I2S DAC1L"},
1281     {"DAC1", NULL, "I2S DAC1R"},
1282     {"DAC2", NULL, "I2S DAC2L"},
1283     {"DAC2", NULL, "I2S DAC2R"},
1284     {"PortA Mux", "DAC1 Switch", "DAC1"},
1285     {"PortA Mux", "DAC2 Switch", "DAC2"},
1286     {"PortG Mux", "DAC1 Switch", "DAC1"},
1287     {"PortG Mux", "DAC2 Switch", "DAC2"},
1288     {"PortE Mux", "DAC1 Switch", "DAC1"},
1289     {"PortE Mux", "DAC2 Switch", "DAC2"},
1290     {"PortM Mux", "DAC1 Switch", "DAC1"},
1291     {"PortM Mux", "DAC2 Switch", "DAC2"},
1292     {"Widget15 Mixer", "DAC1L Switch", "DAC1"},
1293     {"Widget15 Mixer", "DAC1R Switch", "DAC2"},
1294     {"Widget15 Mixer", "DAC2L Switch", "DAC1"},
1295     {"Widget15 Mixer", "DAC2R Switch", "DAC2"},
1296     {"Widget15 Mixer", NULL, "Widget15 Power"},
1297     {"PortA Out En", "Switch", "PortA Mux"},
1298     {"PortG Out En", "Switch", "PortG Mux"},
1299     {"PortE Out En", "Switch", "PortE Mux"},
1300     {"PortM Out En", "Switch", "PortM Mux"},
1301     {"PortA Mux", NULL, "PortA Power"},
1302     {"PortG Mux", NULL, "PortG Power"},
1303     {"PortE Mux", NULL, "PortE Power"},
1304     {"PortM Mux", NULL, "PortM Power"},
1305     {"PortA Out En", NULL, "PortA Power"},
1306     {"PortG Out En", NULL, "PortG Power"},
1307     {"PortE Out En", NULL, "PortE Power"},
1308     {"PortM Out En", NULL, "PortM Power"},
1309     {"PORTA", NULL, "PortA Out En"},
1310     {"PORTG", NULL, "PortG Out En"},
1311     {"PORTE", NULL, "PortE Out En"},
1312     {"PORTM", NULL, "PortM Out En"},
1313 
1314     /* Capture */
1315     {"PORTD", NULL, "Headset Bias"},
1316     {"PortB In En", "Switch", "PORTB"},
1317     {"PortC In En", "Switch", "PORTC"},
1318     {"PortD In En", "Switch", "PORTD"},
1319     {"PortE In En", "Switch", "PORTEIN"},
1320     {"ADC1 Mux", "PortB Switch", "PortB In En"},
1321     {"ADC1 Mux", "PortC Switch", "PortC In En"},
1322     {"ADC1 Mux", "PortD Switch", "PortD In En"},
1323     {"ADC1 Mux", "PortE Switch", "PortE In En"},
1324     {"ADC1 Mux", "Widget15 Switch", "Widget15 Mixer"},
1325     {"ADC2 Mux", "PortC Switch", "PortC In En"},
1326     {"ADC2 Mux", "Widget15 Switch", "Widget15 Mixer"},
1327     {"ADC1", NULL, "ADC1 Mux"},
1328     {"ADC2", NULL, "ADC2 Mux"},
1329     {"I2S ADC1L", "Switch", "ADC1"},
1330     {"I2S ADC1R", "Switch", "ADC1"},
1331     {"I2S ADC2L", "Switch", "ADC2"},
1332     {"I2S ADC2R", "Switch", "ADC2"},
1333     {"Out AIF", NULL, "I2S ADC1L"},
1334     {"Out AIF", NULL, "I2S ADC1R"},
1335     {"Out AIF", NULL, "I2S ADC2L"},
1336     {"Out AIF", NULL, "I2S ADC2R"},
1337     {"Out AIF", NULL, "AFG Power"},
1338     {"AEC REF", NULL, "Out AIF"},
1339     {"PortB In En", NULL, "PortB Power"},
1340     {"PortC In En", NULL, "PortC Power"},
1341     {"PortD In En", NULL, "PortD Power"},
1342     {"PortE In En", NULL, "PortE Power"},
1343 };
1344 
1345 static int cx2072x_set_bias_level(struct snd_soc_component *codec,
1346                   enum snd_soc_bias_level level)
1347 {
1348     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1349     const enum snd_soc_bias_level old_level =
1350         snd_soc_component_get_bias_level(codec);
1351 
1352     if (level == SND_SOC_BIAS_STANDBY && old_level == SND_SOC_BIAS_OFF)
1353         regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
1354     else if (level == SND_SOC_BIAS_OFF && old_level != SND_SOC_BIAS_OFF)
1355         regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
1356 
1357     return 0;
1358 }
1359 
1360 /*
1361  * FIXME: the whole jack detection code below is pretty platform-specific;
1362  * it has lots of implicit assumptions about the pins, etc.
1363  * However, since we have no other code and reference, take this hard-coded
1364  * setup for now.  Once when we have different platform implementations,
1365  * this needs to be rewritten in a more generic form, or moving into the
1366  * platform data.
1367  */
1368 static void cx2072x_enable_jack_detect(struct snd_soc_component *codec)
1369 {
1370     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1371     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec);
1372 
1373     /* No-sticky input type */
1374     regmap_write(cx2072x->regmap, CX2072X_GPIO_STICKY_MASK, 0x1f);
1375 
1376     /* Use GPOI0 as interrupt pin */
1377     regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
1378 
1379     /* Enables unsolitited message on PortA */
1380     regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x80);
1381 
1382     /* support both nokia and apple headset set. Monitor time = 275 ms */
1383     regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST15, 0x73);
1384 
1385     /* Disable TIP detection */
1386     regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST12, 0x300);
1387 
1388     /* Switch MusicD3Live pin to GPIO */
1389     regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST1, 0);
1390 
1391     snd_soc_dapm_mutex_lock(dapm);
1392 
1393     snd_soc_dapm_force_enable_pin_unlocked(dapm, "PORTD");
1394     snd_soc_dapm_force_enable_pin_unlocked(dapm, "Headset Bias");
1395     snd_soc_dapm_force_enable_pin_unlocked(dapm, "PortD Mic Bias");
1396 
1397     snd_soc_dapm_mutex_unlock(dapm);
1398 }
1399 
1400 static void cx2072x_disable_jack_detect(struct snd_soc_component *codec)
1401 {
1402     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1403 
1404     regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0);
1405     regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0);
1406 }
1407 
1408 static int cx2072x_jack_status_check(void *data)
1409 {
1410     struct snd_soc_component *codec = data;
1411     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1412     unsigned int jack;
1413     unsigned int type = 0;
1414     int state = 0;
1415 
1416     mutex_lock(&cx2072x->lock);
1417 
1418     regmap_read(cx2072x->regmap, CX2072X_PORTA_PIN_SENSE, &jack);
1419     jack = jack >> 24;
1420     regmap_read(cx2072x->regmap, CX2072X_DIGITAL_TEST11, &type);
1421 
1422     if (jack == 0x80) {
1423         type = type >> 8;
1424 
1425         if (type & 0x8) {
1426             /* Apple headset */
1427             state |= SND_JACK_HEADSET;
1428             if (type & 0x2)
1429                 state |= SND_JACK_BTN_0;
1430         } else {
1431             /*
1432              * Nokia headset (type & 0x4) and
1433              * regular Headphone
1434              */
1435             state |= SND_JACK_HEADPHONE;
1436         }
1437     }
1438 
1439     /* clear interrupt */
1440     regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
1441 
1442     mutex_unlock(&cx2072x->lock);
1443 
1444     dev_dbg(codec->dev, "CX2072X_HSDETECT type=0x%X,Jack state = %x\n",
1445         type, state);
1446     return state;
1447 }
1448 
1449 static const struct snd_soc_jack_gpio cx2072x_jack_gpio = {
1450     .name = "headset",
1451     .report = SND_JACK_HEADSET | SND_JACK_BTN_0,
1452     .debounce_time = 150,
1453     .wake = true,
1454     .jack_status_check = cx2072x_jack_status_check,
1455 };
1456 
1457 static int cx2072x_set_jack(struct snd_soc_component *codec,
1458                 struct snd_soc_jack *jack, void *data)
1459 {
1460     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1461     int err;
1462 
1463     if (!jack) {
1464         cx2072x_disable_jack_detect(codec);
1465         return 0;
1466     }
1467 
1468     if (!cx2072x->jack_gpio.gpiod_dev) {
1469         cx2072x->jack_gpio = cx2072x_jack_gpio;
1470         cx2072x->jack_gpio.gpiod_dev = codec->dev;
1471         cx2072x->jack_gpio.data = codec;
1472         err = snd_soc_jack_add_gpios(jack, 1, &cx2072x->jack_gpio);
1473         if (err) {
1474             cx2072x->jack_gpio.gpiod_dev = NULL;
1475             return err;
1476         }
1477     }
1478 
1479     cx2072x_enable_jack_detect(codec);
1480     return 0;
1481 }
1482 
1483 static int cx2072x_probe(struct snd_soc_component *codec)
1484 {
1485     struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
1486 
1487     cx2072x->codec = codec;
1488 
1489     /*
1490      * FIXME: below is, again, a very platform-specific init sequence,
1491      * but we keep the code here just for simplicity.  It seems that all
1492      * existing hardware implementations require this, so there is no very
1493      * much reason to move this out of the codec driver to the platform
1494      * data.
1495      * But of course it's no "right" thing; if you are a good boy, don't
1496      * read and follow the code like this!
1497      */
1498     pm_runtime_get_sync(codec->dev);
1499     regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
1500 
1501     regmap_multi_reg_write(cx2072x->regmap, cx2072x_reg_init,
1502                    ARRAY_SIZE(cx2072x_reg_init));
1503 
1504     /* configure PortC as input device */
1505     regmap_update_bits(cx2072x->regmap, CX2072X_PORTC_PIN_CTRL,
1506                0x20, 0x20);
1507 
1508     regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
1509                0x84, 0xff);
1510 
1511     regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 3);
1512     pm_runtime_put(codec->dev);
1513 
1514     return 0;
1515 }
1516 
1517 static const struct snd_soc_component_driver soc_codec_driver_cx2072x = {
1518     .probe = cx2072x_probe,
1519     .set_bias_level = cx2072x_set_bias_level,
1520     .set_jack = cx2072x_set_jack,
1521     .controls = cx2072x_snd_controls,
1522     .num_controls = ARRAY_SIZE(cx2072x_snd_controls),
1523     .dapm_widgets = cx2072x_dapm_widgets,
1524     .num_dapm_widgets = ARRAY_SIZE(cx2072x_dapm_widgets),
1525     .dapm_routes = cx2072x_intercon,
1526     .num_dapm_routes = ARRAY_SIZE(cx2072x_intercon),
1527     .endianness = 1,
1528 };
1529 
1530 /*
1531  * DAI ops
1532  */
1533 static const struct snd_soc_dai_ops cx2072x_dai_ops = {
1534     .set_sysclk = cx2072x_set_dai_sysclk,
1535     .set_fmt = cx2072x_set_dai_fmt,
1536     .hw_params = cx2072x_hw_params,
1537     .set_bclk_ratio = cx2072x_set_dai_bclk_ratio,
1538 };
1539 
1540 static int cx2072x_dsp_dai_probe(struct snd_soc_dai *dai)
1541 {
1542     struct cx2072x_priv *cx2072x =
1543         snd_soc_component_get_drvdata(dai->component);
1544 
1545     cx2072x->en_aec_ref = true;
1546     return 0;
1547 }
1548 
1549 #define CX2072X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1550 
1551 static struct snd_soc_dai_driver soc_codec_cx2072x_dai[] = {
1552     { /* playback and capture */
1553         .name = "cx2072x-hifi",
1554         .id = CX2072X_DAI_HIFI,
1555         .playback = {
1556             .stream_name = "Playback",
1557             .channels_min = 1,
1558             .channels_max = 2,
1559             .rates = CX2072X_RATES_DSP,
1560             .formats = CX2072X_FORMATS,
1561         },
1562         .capture = {
1563             .stream_name = "Capture",
1564             .channels_min = 1,
1565             .channels_max = 2,
1566             .rates = CX2072X_RATES_DSP,
1567             .formats = CX2072X_FORMATS,
1568         },
1569         .ops = &cx2072x_dai_ops,
1570         .symmetric_rate = 1,
1571     },
1572     { /* plabayck only, return echo reference to Conexant DSP chip */
1573         .name = "cx2072x-dsp",
1574         .id = CX2072X_DAI_DSP,
1575         .probe = cx2072x_dsp_dai_probe,
1576         .playback = {
1577             .stream_name = "DSP Playback",
1578             .channels_min = 2,
1579             .channels_max = 2,
1580             .rates = CX2072X_RATES_DSP,
1581             .formats = CX2072X_FORMATS,
1582         },
1583         .ops = &cx2072x_dai_ops,
1584     },
1585     { /* plabayck only, return echo reference through I2S TX */
1586         .name = "cx2072x-aec",
1587         .id = 3,
1588         .capture = {
1589             .stream_name = "AEC Capture",
1590             .channels_min = 2,
1591             .channels_max = 2,
1592             .rates = CX2072X_RATES_DSP,
1593             .formats = CX2072X_FORMATS,
1594         },
1595     },
1596 };
1597 
1598 static const struct regmap_config cx2072x_regmap = {
1599     .reg_bits = 16,
1600     .val_bits = 32,
1601     .max_register = CX2072X_REG_MAX,
1602     .reg_defaults = cx2072x_reg_defaults,
1603     .num_reg_defaults = ARRAY_SIZE(cx2072x_reg_defaults),
1604     .cache_type = REGCACHE_RBTREE,
1605     .readable_reg = cx2072x_readable_register,
1606     .volatile_reg = cx2072x_volatile_register,
1607     /* Needs custom read/write functions for various register lengths */
1608     .reg_read = cx2072x_reg_read,
1609     .reg_write = cx2072x_reg_write,
1610 };
1611 
1612 static int __maybe_unused cx2072x_runtime_suspend(struct device *dev)
1613 {
1614     struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1615 
1616     clk_disable_unprepare(cx2072x->mclk);
1617     return 0;
1618 }
1619 
1620 static int __maybe_unused cx2072x_runtime_resume(struct device *dev)
1621 {
1622     struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1623 
1624     return clk_prepare_enable(cx2072x->mclk);
1625 }
1626 
1627 static int cx2072x_i2c_probe(struct i2c_client *i2c)
1628 {
1629     struct cx2072x_priv *cx2072x;
1630     unsigned int ven_id, rev_id;
1631     int ret;
1632 
1633     cx2072x = devm_kzalloc(&i2c->dev, sizeof(struct cx2072x_priv),
1634                    GFP_KERNEL);
1635     if (!cx2072x)
1636         return -ENOMEM;
1637 
1638     cx2072x->regmap = devm_regmap_init(&i2c->dev, NULL, i2c,
1639                        &cx2072x_regmap);
1640     if (IS_ERR(cx2072x->regmap))
1641         return PTR_ERR(cx2072x->regmap);
1642 
1643     mutex_init(&cx2072x->lock);
1644 
1645     i2c_set_clientdata(i2c, cx2072x);
1646 
1647     cx2072x->dev = &i2c->dev;
1648     cx2072x->pll_changed = true;
1649     cx2072x->i2spcm_changed = true;
1650     cx2072x->bclk_ratio = 0;
1651 
1652     cx2072x->mclk = devm_clk_get(cx2072x->dev, "mclk");
1653     if (IS_ERR(cx2072x->mclk)) {
1654         dev_err(cx2072x->dev, "Failed to get MCLK\n");
1655         return PTR_ERR(cx2072x->mclk);
1656     }
1657 
1658     regmap_read(cx2072x->regmap, CX2072X_VENDOR_ID, &ven_id);
1659     regmap_read(cx2072x->regmap, CX2072X_REVISION_ID, &rev_id);
1660 
1661     dev_info(cx2072x->dev, "codec version: %08x,%08x\n", ven_id, rev_id);
1662 
1663     ret = devm_snd_soc_register_component(cx2072x->dev,
1664                           &soc_codec_driver_cx2072x,
1665                           soc_codec_cx2072x_dai,
1666                           ARRAY_SIZE(soc_codec_cx2072x_dai));
1667     if (ret < 0)
1668         return ret;
1669 
1670     pm_runtime_use_autosuspend(cx2072x->dev);
1671     pm_runtime_enable(cx2072x->dev);
1672 
1673     return 0;
1674 }
1675 
1676 static int cx2072x_i2c_remove(struct i2c_client *i2c)
1677 {
1678     pm_runtime_disable(&i2c->dev);
1679     return 0;
1680 }
1681 
1682 static const struct i2c_device_id cx2072x_i2c_id[] = {
1683     { "cx20721", 0 },
1684     { "cx20723", 0 },
1685     {}
1686 };
1687 MODULE_DEVICE_TABLE(i2c, cx2072x_i2c_id);
1688 
1689 #ifdef CONFIG_ACPI
1690 static struct acpi_device_id cx2072x_acpi_match[] = {
1691     { "14F10720", 0 },
1692     {},
1693 };
1694 MODULE_DEVICE_TABLE(acpi, cx2072x_acpi_match);
1695 #endif
1696 
1697 static const struct dev_pm_ops cx2072x_runtime_pm = {
1698     SET_RUNTIME_PM_OPS(cx2072x_runtime_suspend, cx2072x_runtime_resume,
1699                NULL)
1700     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1701                 pm_runtime_force_resume)
1702 };
1703 
1704 static struct i2c_driver cx2072x_i2c_driver = {
1705     .driver = {
1706         .name = "cx2072x",
1707         .acpi_match_table = ACPI_PTR(cx2072x_acpi_match),
1708         .pm = &cx2072x_runtime_pm,
1709     },
1710     .probe_new = cx2072x_i2c_probe,
1711     .remove = cx2072x_i2c_remove,
1712     .id_table = cx2072x_i2c_id,
1713 };
1714 
1715 module_i2c_driver(cx2072x_i2c_driver);
1716 
1717 MODULE_DESCRIPTION("ASoC cx2072x Codec Driver");
1718 MODULE_AUTHOR("Simon Ho <simon.ho@conexant.com>");
1719 MODULE_LICENSE("GPL");
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