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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ALSA SoC CS43130 codec driver
0004  *
0005  * Copyright 2017 Cirrus Logic, Inc.
0006  *
0007  * Author: Li Xu <li.xu@cirrus.com>
0008  */
0009 
0010 #ifndef __CS43130_H__
0011 #define __CS43130_H__
0012 
0013 #include <linux/math.h>
0014 
0015 /* CS43130 registers addresses */
0016 /* all reg address is shifted by a byte for control byte to be LSB */
0017 #define CS43130_FIRSTREG    0x010000
0018 #define CS43130_LASTREG     0x190000
0019 #define CS43130_CHIP_ID     0x00043130
0020 #define CS4399_CHIP_ID      0x00043990
0021 #define CS43131_CHIP_ID     0x00043131
0022 #define CS43198_CHIP_ID     0x00043198
0023 #define CS43130_DEVID_AB    0x010000    /* Device ID A & B [RO] */
0024 #define CS43130_DEVID_CD    0x010001    /* Device ID C & D [RO] */
0025 #define CS43130_DEVID_E     0x010002    /* Device ID E [RO] */
0026 #define CS43130_FAB_ID      0x010003        /* Fab ID [RO] */
0027 #define CS43130_REV_ID      0x010004        /* Revision ID [RO] */
0028 #define CS43130_SUBREV_ID   0x010005        /* Subrevision ID */
0029 #define CS43130_SYS_CLK_CTL_1   0x010006    /* System Clocking Ctl 1 */
0030 #define CS43130_SP_SRATE    0x01000B        /* Serial Port Sample Rate */
0031 #define CS43130_SP_BITSIZE  0x01000C        /* Serial Port Bit Size */
0032 #define CS43130_PAD_INT_CFG 0x01000D    /* Pad Interface Config */
0033 #define CS43130_DXD1            0x010010        /* DXD1 */
0034 #define CS43130_DXD7            0x010025        /* DXD7 */
0035 #define CS43130_DXD19           0x010026        /* DXD19 */
0036 #define CS43130_DXD17           0x010027        /* DXD17 */
0037 #define CS43130_DXD18           0x010028        /* DXD18 */
0038 #define CS43130_DXD12           0x01002C        /* DXD12 */
0039 #define CS43130_DXD8            0x01002E        /* DXD8 */
0040 #define CS43130_PWDN_CTL    0x020000        /* Power Down Ctl */
0041 #define CS43130_DXD2            0x020019        /* DXD2 */
0042 #define CS43130_CRYSTAL_SET 0x020052    /* Crystal Setting */
0043 #define CS43130_PLL_SET_1   0x030001        /* PLL Setting 1 */
0044 #define CS43130_PLL_SET_2   0x030002        /* PLL Setting 2 */
0045 #define CS43130_PLL_SET_3   0x030003        /* PLL Setting 3 */
0046 #define CS43130_PLL_SET_4   0x030004        /* PLL Setting 4 */
0047 #define CS43130_PLL_SET_5   0x030005        /* PLL Setting 5 */
0048 #define CS43130_PLL_SET_6   0x030008        /* PLL Setting 6 */
0049 #define CS43130_PLL_SET_7   0x03000A        /* PLL Setting 7 */
0050 #define CS43130_PLL_SET_8   0x03001B        /* PLL Setting 8 */
0051 #define CS43130_PLL_SET_9   0x040002        /* PLL Setting 9 */
0052 #define CS43130_PLL_SET_10  0x040003        /* PLL Setting 10 */
0053 #define CS43130_CLKOUT_CTL  0x040004        /* CLKOUT Ctl */
0054 #define CS43130_ASP_NUM_1   0x040010        /* ASP Numerator 1 */
0055 #define CS43130_ASP_NUM_2   0x040011        /* ASP Numerator 2 */
0056 #define CS43130_ASP_DEN_1   0x040012    /* ASP Denominator 1 */
0057 #define CS43130_ASP_DEN_2   0x040013    /* ASP Denominator 2 */
0058 #define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */
0059 #define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */
0060 #define CS43130_ASP_LRCK_PERIOD_1  0x040016 /* ASP LRCK Period 1 */
0061 #define CS43130_ASP_LRCK_PERIOD_2  0x040017 /* ASP LRCK Period 2 */
0062 #define CS43130_ASP_CLOCK_CONF  0x040018    /* ASP Clock Config */
0063 #define CS43130_ASP_FRAME_CONF  0x040019    /* ASP Frame Config */
0064 #define CS43130_XSP_NUM_1   0x040020        /* XSP Numerator 1 */
0065 #define CS43130_XSP_NUM_2   0x040021        /* XSP Numerator 2 */
0066 #define CS43130_XSP_DEN_1   0x040022    /* XSP Denominator 1 */
0067 #define CS43130_XSP_DEN_2   0x040023    /* XSP Denominator 2 */
0068 #define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */
0069 #define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */
0070 #define CS43130_XSP_LRCK_PERIOD_1  0x040026 /* XSP LRCK Period 1 */
0071 #define CS43130_XSP_LRCK_PERIOD_2  0x040027 /* XSP LRCK Period 2 */
0072 #define CS43130_XSP_CLOCK_CONF  0x040028    /* XSP Clock Config */
0073 #define CS43130_XSP_FRAME_CONF  0x040029    /* XSP Frame Config */
0074 #define CS43130_ASP_CH_1_LOC    0x050000    /* ASP Chan 1 Location */
0075 #define CS43130_ASP_CH_2_LOC    0x050001    /* ASP Chan 2 Location */
0076 #define CS43130_ASP_CH_1_SZ_EN  0x05000A    /* ASP Chan 1 Size, Enable */
0077 #define CS43130_ASP_CH_2_SZ_EN  0x05000B    /* ASP Chan 2 Size, Enable */
0078 #define CS43130_XSP_CH_1_LOC    0x060000    /* XSP Chan 1 Location */
0079 #define CS43130_XSP_CH_2_LOC    0x060001    /* XSP Chan 2 Location */
0080 #define CS43130_XSP_CH_1_SZ_EN  0x06000A    /* XSP Chan 1 Size, Enable */
0081 #define CS43130_XSP_CH_2_SZ_EN  0x06000B    /* XSP Chan 2 Size, Enable */
0082 #define CS43130_DSD_VOL_B   0x070000        /* DSD Volume B */
0083 #define CS43130_DSD_VOL_A   0x070001        /* DSD Volume A */
0084 #define CS43130_DSD_PATH_CTL_1  0x070002    /* DSD Proc Path Sig Ctl 1 */
0085 #define CS43130_DSD_INT_CFG 0x070003    /* DSD Interface Config */
0086 #define CS43130_DSD_PATH_CTL_2  0x070004    /* DSD Proc Path Sig Ctl 2 */
0087 #define CS43130_DSD_PCM_MIX_CTL 0x070005    /* DSD and PCM Mixing Ctl */
0088 #define CS43130_DSD_PATH_CTL_3  0x070006    /* DSD Proc Path Sig Ctl 3 */
0089 #define CS43130_HP_OUT_CTL_1    0x080000    /* HP Output Ctl 1 */
0090 #define CS43130_DXD16       0x080024    /* DXD16 */
0091 #define CS43130_DXD13       0x080032    /* DXD13 */
0092 #define CS43130_PCM_FILT_OPT    0x090000    /* PCM Filter Option */
0093 #define CS43130_PCM_VOL_B   0x090001        /* PCM Volume B */
0094 #define CS43130_PCM_VOL_A   0x090002        /* PCM Volume A */
0095 #define CS43130_PCM_PATH_CTL_1  0x090003    /* PCM Path Signal Ctl 1 */
0096 #define CS43130_PCM_PATH_CTL_2  0x090004    /* PCM Path Signal Ctl 2 */
0097 #define CS43130_DXD6        0x090097    /* DXD6 */
0098 #define CS43130_CLASS_H_CTL 0x0B0000    /* Class H Ctl */
0099 #define CS43130_DXD15       0x0B0005    /* DXD15 */
0100 #define CS43130_DXD14       0x0B0006    /* DXD14 */
0101 #define CS43130_DXD3        0x0C0002    /* DXD3 */
0102 #define CS43130_DXD10       0x0C0003    /* DXD10 */
0103 #define CS43130_DXD11       0x0C0005    /* DXD11 */
0104 #define CS43130_DXD9        0x0C0006    /* DXD9 */
0105 #define CS43130_DXD4        0x0C0009    /* DXD4 */
0106 #define CS43130_DXD5        0x0C000E    /* DXD5 */
0107 #define CS43130_HP_DETECT   0x0D0000        /* HP Detect */
0108 #define CS43130_HP_STATUS   0x0D0001        /* HP Status [RO] */
0109 #define CS43130_HP_LOAD_1   0x0E0000        /* HP Load 1 */
0110 #define CS43130_HP_MEAS_LOAD_1  0x0E0003    /* HP Load Measurement 1 */
0111 #define CS43130_HP_MEAS_LOAD_2  0x0E0004    /* HP Load Measurement 2 */
0112 #define CS43130_HP_DC_STAT_1    0x0E000D    /* HP DC Load Status 0 [RO] */
0113 #define CS43130_HP_DC_STAT_2    0x0E000E    /* HP DC Load Status 1 [RO] */
0114 #define CS43130_HP_AC_STAT_1    0x0E0010    /* HP AC Load Status 0 [RO] */
0115 #define CS43130_HP_AC_STAT_2    0x0E0011    /* HP AC Load Status 1 [RO] */
0116 #define CS43130_HP_LOAD_STAT    0x0E001A    /* HP Load Status [RO] */
0117 #define CS43130_INT_STATUS_1    0x0F0000    /* Interrupt Status 1 */
0118 #define CS43130_INT_STATUS_2    0x0F0001    /* Interrupt Status 2 */
0119 #define CS43130_INT_STATUS_3    0x0F0002    /* Interrupt Status 3 */
0120 #define CS43130_INT_STATUS_4    0x0F0003    /* Interrupt Status 4 */
0121 #define CS43130_INT_STATUS_5    0x0F0004    /* Interrupt Status 5 */
0122 #define CS43130_INT_MASK_1  0x0F0010        /* Interrupt Mask 1 */
0123 #define CS43130_INT_MASK_2  0x0F0011    /* Interrupt Mask 2 */
0124 #define CS43130_INT_MASK_3  0x0F0012        /* Interrupt Mask 3 */
0125 #define CS43130_INT_MASK_4  0x0F0013        /* Interrupt Mask 4 */
0126 #define CS43130_INT_MASK_5  0x0F0014        /* Interrupt Mask 5 */
0127 
0128 #define CS43130_MCLK_SRC_SEL_MASK   0x03
0129 #define CS43130_MCLK_SRC_SEL_SHIFT  0
0130 #define CS43130_MCLK_INT_MASK       0x04
0131 #define CS43130_MCLK_INT_SHIFT      2
0132 #define CS43130_CH_BITSIZE_MASK     0x03
0133 #define CS43130_CH_EN_MASK      0x04
0134 #define CS43130_CH_EN_SHIFT     2
0135 #define CS43130_ASP_BITSIZE_MASK    0x03
0136 #define CS43130_XSP_BITSIZE_MASK    0x0C
0137 #define CS43130_XSP_BITSIZE_SHIFT   2
0138 #define CS43130_SP_BITSIZE_ASP_SHIFT    0
0139 #define CS43130_HP_DETECT_CTRL_SHIFT    6
0140 #define CS43130_HP_DETECT_CTRL_MASK     (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
0141 #define CS43130_HP_DETECT_INV_SHIFT 5
0142 #define CS43130_HP_DETECT_INV_MASK      (1 << CS43130_HP_DETECT_INV_SHIFT)
0143 
0144 /* CS43130_INT_MASK_1 */
0145 #define CS43130_HP_PLUG_INT_SHIFT       6
0146 #define CS43130_HP_PLUG_INT             (1 << CS43130_HP_PLUG_INT_SHIFT)
0147 #define CS43130_HP_UNPLUG_INT_SHIFT     5
0148 #define CS43130_HP_UNPLUG_INT           (1 << CS43130_HP_UNPLUG_INT_SHIFT)
0149 #define CS43130_XTAL_RDY_INT_SHIFT      4
0150 #define CS43130_XTAL_RDY_INT_MASK   0x10
0151 #define CS43130_XTAL_RDY_INT            (1 << CS43130_XTAL_RDY_INT_SHIFT)
0152 #define CS43130_XTAL_ERR_INT_SHIFT      3
0153 #define CS43130_XTAL_ERR_INT            (1 << CS43130_XTAL_ERR_INT_SHIFT)
0154 #define CS43130_PLL_RDY_INT_MASK    0x04
0155 #define CS43130_PLL_RDY_INT_SHIFT   2
0156 #define CS43130_PLL_RDY_INT     (1 << CS43130_PLL_RDY_INT_SHIFT)
0157 
0158 /* CS43130_INT_MASK_4 */
0159 #define CS43130_INT_MASK_ALL        0xFF
0160 #define CS43130_HPLOAD_NO_DC_INT_SHIFT  7
0161 #define CS43130_HPLOAD_NO_DC_INT    (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)
0162 #define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6
0163 #define CS43130_HPLOAD_UNPLUG_INT   (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)
0164 #define CS43130_HPLOAD_OOR_INT_SHIFT    4
0165 #define CS43130_HPLOAD_OOR_INT      (1 << CS43130_HPLOAD_OOR_INT_SHIFT)
0166 #define CS43130_HPLOAD_AC_INT_SHIFT 3
0167 #define CS43130_HPLOAD_AC_INT       (1 << CS43130_HPLOAD_AC_INT_SHIFT)
0168 #define CS43130_HPLOAD_DC_INT_SHIFT 2
0169 #define CS43130_HPLOAD_DC_INT       (1 << CS43130_HPLOAD_DC_INT_SHIFT)
0170 #define CS43130_HPLOAD_OFF_INT_SHIFT    1
0171 #define CS43130_HPLOAD_OFF_INT      (1 << CS43130_HPLOAD_OFF_INT_SHIFT)
0172 #define CS43130_HPLOAD_ON_INT       1
0173 
0174 /* CS43130_HP_LOAD_1 */
0175 #define CS43130_HPLOAD_EN_SHIFT     7
0176 #define CS43130_HPLOAD_EN       (1 << CS43130_HPLOAD_EN_SHIFT)
0177 #define CS43130_HPLOAD_CHN_SEL_SHIFT    4
0178 #define CS43130_HPLOAD_CHN_SEL      (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)
0179 #define CS43130_HPLOAD_AC_START_SHIFT   1
0180 #define CS43130_HPLOAD_AC_START     (1 << CS43130_HPLOAD_AC_START_SHIFT)
0181 #define CS43130_HPLOAD_DC_START     1
0182 
0183 /* Reg CS43130_SP_BITSIZE */
0184 #define CS43130_SP_BIT_SIZE_8   0x03
0185 #define CS43130_SP_BIT_SIZE_16  0x02
0186 #define CS43130_SP_BIT_SIZE_24  0x01
0187 #define CS43130_SP_BIT_SIZE_32  0x00
0188 
0189 /* Reg CS43130_SP_CH_SZ_EN */
0190 #define CS43130_CH_BIT_SIZE_8   0x00
0191 #define CS43130_CH_BIT_SIZE_16  0x01
0192 #define CS43130_CH_BIT_SIZE_24  0x02
0193 #define CS43130_CH_BIT_SIZE_32  0x03
0194 
0195 /* PLL */
0196 #define CS43130_PLL_START_MASK  0x01
0197 #define CS43130_PLL_MODE_MASK   0x02
0198 #define CS43130_PLL_MODE_SHIFT  1
0199 
0200 #define CS43130_PLL_REF_PREDIV_MASK 0x3
0201 
0202 #define CS43130_SP_STP_MASK 0x10
0203 #define CS43130_SP_STP_SHIFT    4
0204 #define CS43130_SP_5050_MASK    0x08
0205 #define CS43130_SP_5050_SHIFT   3
0206 #define CS43130_SP_FSD_MASK 0x07
0207 
0208 #define CS43130_SP_MODE_MASK    0x10
0209 #define CS43130_SP_MODE_SHIFT   4
0210 #define CS43130_SP_SCPOL_OUT_MASK   0x08
0211 #define CS43130_SP_SCPOL_OUT_SHIFT  3
0212 #define CS43130_SP_SCPOL_IN_MASK    0x04
0213 #define CS43130_SP_SCPOL_IN_SHIFT   2
0214 #define CS43130_SP_LCPOL_OUT_MASK   0x02
0215 #define CS43130_SP_LCPOL_OUT_SHIFT  1
0216 #define CS43130_SP_LCPOL_IN_MASK    0x01
0217 #define CS43130_SP_LCPOL_IN_SHIFT   0
0218 
0219 /* Reg CS43130_PWDN_CTL */
0220 #define CS43130_PDN_XSP_MASK    0x80
0221 #define CS43130_PDN_XSP_SHIFT   7
0222 #define CS43130_PDN_ASP_MASK    0x40
0223 #define CS43130_PDN_ASP_SHIFT   6
0224 #define CS43130_PDN_DSPIF_MASK  0x20
0225 #define CS43130_PDN_DSDIF_SHIFT 5
0226 #define CS43130_PDN_HP_MASK 0x10
0227 #define CS43130_PDN_HP_SHIFT    4
0228 #define CS43130_PDN_XTAL_MASK   0x08
0229 #define CS43130_PDN_XTAL_SHIFT  3
0230 #define CS43130_PDN_PLL_MASK    0x04
0231 #define CS43130_PDN_PLL_SHIFT   2
0232 #define CS43130_PDN_CLKOUT_MASK 0x02
0233 #define CS43130_PDN_CLKOUT_SHIFT    1
0234 
0235 /* Reg CS43130_HP_OUT_CTL_1 */
0236 #define CS43130_HP_IN_EN_SHIFT      3
0237 #define CS43130_HP_IN_EN_MASK       0x08
0238 
0239 /* Reg CS43130_PAD_INT_CFG */
0240 #define CS43130_ASP_3ST_MASK        0x01
0241 #define CS43130_XSP_3ST_MASK        0x02
0242 
0243 /* Reg CS43130_PLL_SET_2 */
0244 #define CS43130_PLL_DIV_DATA_MASK   0x000000FF
0245 #define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT   0
0246 
0247 /* Reg CS43130_PLL_SET_3 */
0248 #define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT   8
0249 
0250 /* Reg CS43130_PLL_SET_4 */
0251 #define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT   16
0252 
0253 /* Reg CS43130_SP_DEN_1 */
0254 #define CS43130_SP_M_LSB_DATA_MASK  0x00FF
0255 #define CS43130_SP_M_LSB_DATA_SHIFT 0
0256 
0257 /* Reg CS43130_SP_DEN_2 */
0258 #define CS43130_SP_M_MSB_DATA_MASK  0xFF00
0259 #define CS43130_SP_M_MSB_DATA_SHIFT 8
0260 
0261 /* Reg CS43130_SP_NUM_1 */
0262 #define CS43130_SP_N_LSB_DATA_MASK  0x00FF
0263 #define CS43130_SP_N_LSB_DATA_SHIFT 0
0264 
0265 /* Reg CS43130_SP_NUM_2 */
0266 #define CS43130_SP_N_MSB_DATA_MASK  0xFF00
0267 #define CS43130_SP_N_MSB_DATA_SHIFT 8
0268 
0269 /* Reg CS43130_SP_LRCK_HI_TIME_1 */
0270 #define CS43130_SP_LCHI_DATA_MASK   0x00FF
0271 #define CS43130_SP_LCHI_LSB_DATA_SHIFT  0
0272 
0273 /* Reg CS43130_SP_LRCK_HI_TIME_2 */
0274 #define CS43130_SP_LCHI_MSB_DATA_SHIFT  8
0275 
0276 /* Reg CS43130_SP_LRCK_PERIOD_1 */
0277 #define CS43130_SP_LCPR_DATA_MASK   0x00FF
0278 #define CS43130_SP_LCPR_LSB_DATA_SHIFT  0
0279 
0280 /* Reg CS43130_SP_LRCK_PERIOD_2 */
0281 #define CS43130_SP_LCPR_MSB_DATA_SHIFT  8
0282 
0283 #define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8  | \
0284             SNDRV_PCM_FMTBIT_S16_LE | \
0285             SNDRV_PCM_FMTBIT_S24_LE | \
0286             SNDRV_PCM_FMTBIT_S32_LE)
0287 
0288 #define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \
0289                  SNDRV_PCM_FMTBIT_DSD_U16_BE | \
0290                  SNDRV_PCM_FMTBIT_S24_LE)
0291 
0292 /* Reg CS43130_CRYSTAL_SET */
0293 #define CS43130_XTAL_IBIAS_MASK     0x07
0294 
0295 /* Reg CS43130_PATH_CTL_1 */
0296 #define CS43130_MUTE_MASK       0x03
0297 #define CS43130_MUTE_EN         0x03
0298 
0299 /* Reg CS43130_DSD_INT_CFG */
0300 #define CS43130_DSD_MASTER      0x04
0301 
0302 /* Reg CS43130_DSD_PATH_CTL_2 */
0303 #define CS43130_DSD_SRC_MASK        0x60
0304 #define CS43130_DSD_SRC_SHIFT       5
0305 #define CS43130_DSD_EN_SHIFT        4
0306 #define CS43130_DSD_SPEED_MASK      0x04
0307 #define CS43130_DSD_SPEED_SHIFT     2
0308 
0309 /* Reg CS43130_DSD_PCM_MIX_CTL  */
0310 #define CS43130_MIX_PCM_PREP_SHIFT  1
0311 #define CS43130_MIX_PCM_PREP_MASK   0x02
0312 
0313 #define CS43130_MIX_PCM_DSD_SHIFT   0
0314 #define CS43130_MIX_PCM_DSD_MASK    0x01
0315 
0316 /* Reg CS43130_HP_MEAS_LOAD */
0317 #define CS43130_HP_MEAS_LOAD_MASK   0x000000FF
0318 #define CS43130_HP_MEAS_LOAD_1_SHIFT    0
0319 #define CS43130_HP_MEAS_LOAD_2_SHIFT    8
0320 
0321 #define CS43130_MCLK_22M        22579200
0322 #define CS43130_MCLK_24M        24576000
0323 
0324 #define CS43130_LINEOUT_LOAD        5000
0325 #define CS43130_JACK_LINEOUT        (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
0326 #define CS43130_JACK_HEADPHONE      (SND_JACK_MECHANICAL | \
0327                      SND_JACK_HEADPHONE)
0328 #define CS43130_JACK_MASK       (SND_JACK_MECHANICAL | \
0329                      SND_JACK_LINEOUT | \
0330                      SND_JACK_HEADPHONE)
0331 
0332 enum cs43130_dsd_src {
0333     CS43130_DSD_SRC_DSD = 0,
0334     CS43130_DSD_SRC_ASP = 2,
0335     CS43130_DSD_SRC_XSP = 3,
0336 };
0337 
0338 enum cs43130_asp_rate {
0339     CS43130_ASP_SPRATE_32K = 0,
0340     CS43130_ASP_SPRATE_44_1K,
0341     CS43130_ASP_SPRATE_48K,
0342     CS43130_ASP_SPRATE_88_2K,
0343     CS43130_ASP_SPRATE_96K,
0344     CS43130_ASP_SPRATE_176_4K,
0345     CS43130_ASP_SPRATE_192K,
0346     CS43130_ASP_SPRATE_352_8K,
0347     CS43130_ASP_SPRATE_384K,
0348 };
0349 
0350 enum cs43130_mclk_src_sel {
0351     CS43130_MCLK_SRC_EXT = 0,
0352     CS43130_MCLK_SRC_PLL,
0353     CS43130_MCLK_SRC_RCO
0354 };
0355 
0356 enum cs43130_mclk_int_freq {
0357     CS43130_MCLK_24P5 = 0,
0358     CS43130_MCLK_22P5,
0359 };
0360 
0361 enum cs43130_xtal_ibias {
0362     CS43130_XTAL_UNUSED = -1,
0363     CS43130_XTAL_IBIAS_15UA = 2,
0364     CS43130_XTAL_IBIAS_12_5UA = 4,
0365     CS43130_XTAL_IBIAS_7_5UA = 6,
0366 };
0367 
0368 enum cs43130_dai_id {
0369     CS43130_ASP_PCM_DAI = 0,
0370     CS43130_ASP_DOP_DAI,
0371     CS43130_XSP_DOP_DAI,
0372     CS43130_XSP_DSD_DAI,
0373     CS43130_DAI_ID_MAX,
0374 };
0375 
0376 struct cs43130_clk_gen {
0377     unsigned int        mclk_int;
0378     int         fs;
0379     struct u16_fract    v;
0380 };
0381 
0382 /* frm_size = 16 */
0383 static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
0384     { 22579200, 32000,      .v = { 441, 10, }, },
0385     { 22579200, 44100,      .v = { 32,  1, }, },
0386     { 22579200, 48000,      .v = { 147, 5, }, },
0387     { 22579200, 88200,      .v = { 16,  1, }, },
0388     { 22579200, 96000,      .v = { 147, 10, }, },
0389     { 22579200, 176400,     .v = { 8,   1, }, },
0390     { 22579200, 192000,     .v = { 147, 20, }, },
0391     { 22579200, 352800,     .v = { 4,   1, }, },
0392     { 22579200, 384000,     .v = { 147, 40, }, },
0393     { 24576000, 32000,      .v = { 48,  1, }, },
0394     { 24576000, 44100,      .v = { 5120,    147, }, },
0395     { 24576000, 48000,      .v = { 32,  1, }, },
0396     { 24576000, 88200,      .v = { 2560,    147, }, },
0397     { 24576000, 96000,      .v = { 16,  1, }, },
0398     { 24576000, 176400,     .v = { 1280,    147, }, },
0399     { 24576000, 192000,     .v = { 8,   1, }, },
0400     { 24576000, 352800,     .v = { 640, 147, }, },
0401     { 24576000, 384000,     .v = { 4,   1, }, },
0402 };
0403 
0404 /* frm_size = 32 */
0405 static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
0406     { 22579200, 32000,      .v = { 441, 20, }, },
0407     { 22579200, 44100,      .v = { 16,  1, }, },
0408     { 22579200, 48000,      .v = { 147, 10, }, },
0409     { 22579200, 88200,      .v = { 8,   1, }, },
0410     { 22579200, 96000,      .v = { 147, 20, }, },
0411     { 22579200, 176400,     .v = { 4,   1, }, },
0412     { 22579200, 192000,     .v = { 147, 40, }, },
0413     { 22579200, 352800,     .v = { 2,   1, }, },
0414     { 22579200, 384000,     .v = { 147, 80, }, },
0415     { 24576000, 32000,      .v = { 24,  1, }, },
0416     { 24576000, 44100,      .v = { 2560,    147, }, },
0417     { 24576000, 48000,      .v = { 16,  1, }, },
0418     { 24576000, 88200,      .v = { 1280,    147, }, },
0419     { 24576000, 96000,      .v = { 8,   1, }, },
0420     { 24576000, 176400,     .v = { 640, 147, }, },
0421     { 24576000, 192000,     .v = { 4,   1, }, },
0422     { 24576000, 352800,     .v = { 320, 147, }, },
0423     { 24576000, 384000,     .v = { 2,   1, }, },
0424 };
0425 
0426 /* frm_size = 48 */
0427 static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
0428     { 22579200, 32000,      .v = { 147, 100, }, },
0429     { 22579200, 44100,      .v = { 32,  3, }, },
0430     { 22579200, 48000,      .v = { 49,  5, }, },
0431     { 22579200, 88200,      .v = { 16,  3, }, },
0432     { 22579200, 96000,      .v = { 49,  10, }, },
0433     { 22579200, 176400,     .v = { 8,   3, }, },
0434     { 22579200, 192000,     .v = { 49,  20, }, },
0435     { 22579200, 352800,     .v = { 4,   3, }, },
0436     { 22579200, 384000,     .v = { 49,  40, }, },
0437     { 24576000, 32000,      .v = { 16,  1, }, },
0438     { 24576000, 44100,      .v = { 5120,    441, }, },
0439     { 24576000, 48000,      .v = { 32,  3, }, },
0440     { 24576000, 88200,      .v = { 2560,    441, }, },
0441     { 24576000, 96000,      .v = { 16,  3, }, },
0442     { 24576000, 176400,     .v = { 1280,    441, }, },
0443     { 24576000, 192000,     .v = { 8,   3, }, },
0444     { 24576000, 352800,     .v = { 640, 441, }, },
0445     { 24576000, 384000,     .v = { 4,   3, }, },
0446 };
0447 
0448 /* frm_size = 64 */
0449 static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
0450     { 22579200, 32000,      .v = { 441, 40, }, },
0451     { 22579200, 44100,      .v = { 8,   1, }, },
0452     { 22579200, 48000,      .v = { 147, 20, }, },
0453     { 22579200, 88200,      .v = { 4,   1, }, },
0454     { 22579200, 96000,      .v = { 147, 40, }, },
0455     { 22579200, 176400,     .v = { 2,   1, }, },
0456     { 22579200, 192000,     .v = { 147, 80, }, },
0457     { 22579200, 352800,     .v = { 1,   1, }, },
0458     { 24576000, 32000,      .v = { 12,  1, }, },
0459     { 24576000, 44100,      .v = { 1280,    147, }, },
0460     { 24576000, 48000,      .v = { 8,   1, }, },
0461     { 24576000, 88200,      .v = { 640, 147, }, },
0462     { 24576000, 96000,      .v = { 4,   1, }, },
0463     { 24576000, 176400,     .v = { 320, 147, }, },
0464     { 24576000, 192000,     .v = { 2,   1, }, },
0465     { 24576000, 352800,     .v = { 160, 147, }, },
0466     { 24576000, 384000,     .v = { 1,   1, }, },
0467 };
0468 
0469 struct cs43130_bitwidth_map {
0470     unsigned int bitwidth;
0471     u8 sp_bit;
0472     u8 ch_bit;
0473 };
0474 
0475 struct cs43130_rate_map {
0476     int fs;
0477     int val;
0478 };
0479 
0480 #define HP_LEFT         0
0481 #define HP_RIGHT        1
0482 #define CS43130_AC_FREQ     10
0483 #define CS43130_DC_THRESHOLD    2
0484 
0485 #define CS43130_NUM_SUPPLIES    5
0486 static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
0487     "VA",
0488     "VP",
0489     "VCP",
0490     "VD",
0491     "VL",
0492 };
0493 
0494 #define CS43130_NUM_INT     5       /* number of interrupt status reg */
0495 
0496 struct cs43130_dai {
0497     unsigned int            sclk;
0498     unsigned int            dai_format;
0499     unsigned int            dai_mode;
0500 };
0501 
0502 struct  cs43130_private {
0503     struct snd_soc_component    *component;
0504     struct regmap           *regmap;
0505     struct regulator_bulk_data  supplies[CS43130_NUM_SUPPLIES];
0506     struct gpio_desc        *reset_gpio;
0507     unsigned int            dev_id; /* codec device ID */
0508     int             xtal_ibias;
0509 
0510     /* shared by both DAIs */
0511     struct mutex            clk_mutex;
0512     int             clk_req;
0513     bool                pll_bypass;
0514     struct completion       xtal_rdy;
0515     struct completion       pll_rdy;
0516     unsigned int            mclk;
0517     unsigned int            mclk_int;
0518     int             mclk_int_src;
0519 
0520     /* DAI specific */
0521     struct cs43130_dai      dais[CS43130_DAI_ID_MAX];
0522 
0523     /* HP load specific */
0524     bool                dc_meas;
0525     bool                ac_meas;
0526     bool                hpload_done;
0527     struct completion       hpload_evt;
0528     unsigned int            hpload_stat;
0529     u16             hpload_dc[2];
0530     u16             dc_threshold[CS43130_DC_THRESHOLD];
0531     u16             ac_freq[CS43130_AC_FREQ];
0532     u16             hpload_ac[CS43130_AC_FREQ][2];
0533     struct workqueue_struct     *wq;
0534     struct work_struct      work;
0535     struct snd_soc_jack     jack;
0536 };
0537 
0538 #endif  /* __CS43130_H__ */
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