soc/codecs/cs42xx8.h

0001 /*
0002  * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
0003  *
0004  * Copyright (C) 2014 Freescale Semiconductor, Inc.
0005  *
0006  * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public License
0009  * version 2. This program is licensed "as is" without any warranty of any
0010  * kind, whether express or implied.
0011  */
0012
0013 #ifndef _CS42XX8_H
0014 #define _CS42XX8_H
0015
0016 struct cs42xx8_driver_data {
0017     char name[32];
0018     int num_adcs;
0019 };
0020
0021 extern const struct dev_pm_ops cs42xx8_pm;
0022 extern const struct cs42xx8_driver_data cs42448_data;
0023 extern const struct cs42xx8_driver_data cs42888_data;
0024 extern const struct regmap_config cs42xx8_regmap_config;
0025 extern const struct of_device_id cs42xx8_of_match[];
0026 int cs42xx8_probe(struct device *dev, struct regmap *regmap);
0027
0028 /* CS42888 register map */
0029 #define CS42XX8_CHIPID              0x01    /* Chip ID */
0030 #define CS42XX8_PWRCTL              0x02    /* Power Control */
0031 #define CS42XX8_FUNCMOD             0x03    /* Functional Mode */
0032 #define CS42XX8_INTF                0x04    /* Interface Formats */
0033 #define CS42XX8_ADCCTL              0x05    /* ADC Control */
0034 #define CS42XX8_TXCTL               0x06    /* Transition Control */
0035 #define CS42XX8_DACMUTE             0x07    /* DAC Mute Control */
0036 #define CS42XX8_VOLAOUT1            0x08    /* Volume Control AOUT1 */
0037 #define CS42XX8_VOLAOUT2            0x09    /* Volume Control AOUT2 */
0038 #define CS42XX8_VOLAOUT3            0x0A    /* Volume Control AOUT3 */
0039 #define CS42XX8_VOLAOUT4            0x0B    /* Volume Control AOUT4 */
0040 #define CS42XX8_VOLAOUT5            0x0C    /* Volume Control AOUT5 */
0041 #define CS42XX8_VOLAOUT6            0x0D    /* Volume Control AOUT6 */
0042 #define CS42XX8_VOLAOUT7            0x0E    /* Volume Control AOUT7 */
0043 #define CS42XX8_VOLAOUT8            0x0F    /* Volume Control AOUT8 */
0044 #define CS42XX8_DACINV              0x10    /* DAC Channel Invert */
0045 #define CS42XX8_VOLAIN1             0x11    /* Volume Control AIN1 */
0046 #define CS42XX8_VOLAIN2             0x12    /* Volume Control AIN2 */
0047 #define CS42XX8_VOLAIN3             0x13    /* Volume Control AIN3 */
0048 #define CS42XX8_VOLAIN4             0x14    /* Volume Control AIN4 */
0049 #define CS42XX8_VOLAIN5             0x15    /* Volume Control AIN5 */
0050 #define CS42XX8_VOLAIN6             0x16    /* Volume Control AIN6 */
0051 #define CS42XX8_ADCINV              0x17    /* ADC Channel Invert */
0052 #define CS42XX8_STATUSCTL           0x18    /* Status Control */
0053 #define CS42XX8_STATUS              0x19    /* Status */
0054 #define CS42XX8_STATUSM             0x1A    /* Status Mask */
0055 #define CS42XX8_MUTEC               0x1B    /* MUTEC Pin Control */
0056
0057 #define CS42XX8_FIRSTREG            CS42XX8_CHIPID
0058 #define CS42XX8_LASTREG             CS42XX8_MUTEC
0059 #define CS42XX8_NUMREGS             (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
0060 #define CS42XX8_I2C_INCR            0x80
0061
0062 /* Chip I.D. and Revision Register (Address 01h) */
0063 #define CS42XX8_CHIPID_CHIP_ID_MASK     0xF0
0064 #define CS42XX8_CHIPID_REV_ID_MASK      0x0F
0065
0066 /* Power Control (Address 02h) */
0067 #define CS42XX8_PWRCTL_PDN_ADC3_SHIFT       7
0068 #define CS42XX8_PWRCTL_PDN_ADC3_MASK        (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
0069 #define CS42XX8_PWRCTL_PDN_ADC3         (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
0070 #define CS42XX8_PWRCTL_PDN_ADC2_SHIFT       6
0071 #define CS42XX8_PWRCTL_PDN_ADC2_MASK        (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
0072 #define CS42XX8_PWRCTL_PDN_ADC2         (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
0073 #define CS42XX8_PWRCTL_PDN_ADC1_SHIFT       5
0074 #define CS42XX8_PWRCTL_PDN_ADC1_MASK        (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
0075 #define CS42XX8_PWRCTL_PDN_ADC1         (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
0076 #define CS42XX8_PWRCTL_PDN_DAC4_SHIFT       4
0077 #define CS42XX8_PWRCTL_PDN_DAC4_MASK        (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
0078 #define CS42XX8_PWRCTL_PDN_DAC4         (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
0079 #define CS42XX8_PWRCTL_PDN_DAC3_SHIFT       3
0080 #define CS42XX8_PWRCTL_PDN_DAC3_MASK        (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
0081 #define CS42XX8_PWRCTL_PDN_DAC3         (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
0082 #define CS42XX8_PWRCTL_PDN_DAC2_SHIFT       2
0083 #define CS42XX8_PWRCTL_PDN_DAC2_MASK        (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
0084 #define CS42XX8_PWRCTL_PDN_DAC2         (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
0085 #define CS42XX8_PWRCTL_PDN_DAC1_SHIFT       1
0086 #define CS42XX8_PWRCTL_PDN_DAC1_MASK        (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
0087 #define CS42XX8_PWRCTL_PDN_DAC1         (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
0088 #define CS42XX8_PWRCTL_PDN_SHIFT        0
0089 #define CS42XX8_PWRCTL_PDN_MASK         (1 << CS42XX8_PWRCTL_PDN_SHIFT)
0090 #define CS42XX8_PWRCTL_PDN          (1 << CS42XX8_PWRCTL_PDN_SHIFT)
0091
0092 /* Functional Mode (Address 03h) */
0093 #define CS42XX8_FUNCMOD_DAC_FM_SHIFT        6
0094 #define CS42XX8_FUNCMOD_DAC_FM_WIDTH        2
0095 #define CS42XX8_FUNCMOD_DAC_FM_MASK     (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
0096 #define CS42XX8_FUNCMOD_DAC_FM(v)       ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
0097 #define CS42XX8_FUNCMOD_ADC_FM_SHIFT        4
0098 #define CS42XX8_FUNCMOD_ADC_FM_WIDTH        2
0099 #define CS42XX8_FUNCMOD_ADC_FM_MASK     (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
0100 #define CS42XX8_FUNCMOD_ADC_FM(v)       ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
0101 #define CS42XX8_FUNCMOD_xC_FM_MASK(x)       ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK)
0102 #define CS42XX8_FUNCMOD_xC_FM(x, v)     ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v))
0103 #define CS42XX8_FUNCMOD_MFREQ_SHIFT     1
0104 #define CS42XX8_FUNCMOD_MFREQ_WIDTH     3
0105 #define CS42XX8_FUNCMOD_MFREQ_MASK      (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT)
0106 #define CS42XX8_FUNCMOD_MFREQ_256(s)        ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
0107 #define CS42XX8_FUNCMOD_MFREQ_384(s)        ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
0108 #define CS42XX8_FUNCMOD_MFREQ_512(s)        ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
0109 #define CS42XX8_FUNCMOD_MFREQ_768(s)        ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
0110 #define CS42XX8_FUNCMOD_MFREQ_1024(s)       ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
0111
0112 #define CS42XX8_FM_SINGLE           0
0113 #define CS42XX8_FM_DOUBLE           1
0114 #define CS42XX8_FM_QUAD             2
0115 #define CS42XX8_FM_AUTO             3
0116
0117 /* Interface Formats (Address 04h) */
0118 #define CS42XX8_INTF_FREEZE_SHIFT       7
0119 #define CS42XX8_INTF_FREEZE_MASK        (1 << CS42XX8_INTF_FREEZE_SHIFT)
0120 #define CS42XX8_INTF_FREEZE         (1 << CS42XX8_INTF_FREEZE_SHIFT)
0121 #define CS42XX8_INTF_AUX_DIF_SHIFT      6
0122 #define CS42XX8_INTF_AUX_DIF_MASK       (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
0123 #define CS42XX8_INTF_AUX_DIF            (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
0124 #define CS42XX8_INTF_DAC_DIF_SHIFT      3
0125 #define CS42XX8_INTF_DAC_DIF_WIDTH      3
0126 #define CS42XX8_INTF_DAC_DIF_MASK       (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT)
0127 #define CS42XX8_INTF_DAC_DIF_LEFTJ      (0 << CS42XX8_INTF_DAC_DIF_SHIFT)
0128 #define CS42XX8_INTF_DAC_DIF_I2S        (1 << CS42XX8_INTF_DAC_DIF_SHIFT)
0129 #define CS42XX8_INTF_DAC_DIF_RIGHTJ     (2 << CS42XX8_INTF_DAC_DIF_SHIFT)
0130 #define CS42XX8_INTF_DAC_DIF_RIGHTJ_16      (3 << CS42XX8_INTF_DAC_DIF_SHIFT)
0131 #define CS42XX8_INTF_DAC_DIF_ONELINE_20     (4 << CS42XX8_INTF_DAC_DIF_SHIFT)
0132 #define CS42XX8_INTF_DAC_DIF_ONELINE_24     (5 << CS42XX8_INTF_DAC_DIF_SHIFT)
0133 #define CS42XX8_INTF_DAC_DIF_TDM        (6 << CS42XX8_INTF_DAC_DIF_SHIFT)
0134 #define CS42XX8_INTF_ADC_DIF_SHIFT      0
0135 #define CS42XX8_INTF_ADC_DIF_WIDTH      3
0136 #define CS42XX8_INTF_ADC_DIF_MASK       (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT)
0137 #define CS42XX8_INTF_ADC_DIF_LEFTJ      (0 << CS42XX8_INTF_ADC_DIF_SHIFT)
0138 #define CS42XX8_INTF_ADC_DIF_I2S        (1 << CS42XX8_INTF_ADC_DIF_SHIFT)
0139 #define CS42XX8_INTF_ADC_DIF_RIGHTJ     (2 << CS42XX8_INTF_ADC_DIF_SHIFT)
0140 #define CS42XX8_INTF_ADC_DIF_RIGHTJ_16      (3 << CS42XX8_INTF_ADC_DIF_SHIFT)
0141 #define CS42XX8_INTF_ADC_DIF_ONELINE_20     (4 << CS42XX8_INTF_ADC_DIF_SHIFT)
0142 #define CS42XX8_INTF_ADC_DIF_ONELINE_24     (5 << CS42XX8_INTF_ADC_DIF_SHIFT)
0143 #define CS42XX8_INTF_ADC_DIF_TDM        (6 << CS42XX8_INTF_ADC_DIF_SHIFT)
0144
0145 /* ADC Control & DAC De-Emphasis (Address 05h) */
0146 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7
0147 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK  (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
0148 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE       (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
0149 #define CS42XX8_ADCCTL_DAC_DEM_SHIFT        5
0150 #define CS42XX8_ADCCTL_DAC_DEM_MASK     (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
0151 #define CS42XX8_ADCCTL_DAC_DEM          (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
0152 #define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT    4
0153 #define CS42XX8_ADCCTL_ADC1_SINGLE_MASK     (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
0154 #define CS42XX8_ADCCTL_ADC1_SINGLE      (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
0155 #define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT    3
0156 #define CS42XX8_ADCCTL_ADC2_SINGLE_MASK     (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
0157 #define CS42XX8_ADCCTL_ADC2_SINGLE      (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
0158 #define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT    2
0159 #define CS42XX8_ADCCTL_ADC3_SINGLE_MASK     (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
0160 #define CS42XX8_ADCCTL_ADC3_SINGLE      (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
0161 #define CS42XX8_ADCCTL_AIN5_MUX_SHIFT       1
0162 #define CS42XX8_ADCCTL_AIN5_MUX_MASK        (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
0163 #define CS42XX8_ADCCTL_AIN5_MUX         (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
0164 #define CS42XX8_ADCCTL_AIN6_MUX_SHIFT       0
0165 #define CS42XX8_ADCCTL_AIN6_MUX_MASK        (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
0166 #define CS42XX8_ADCCTL_AIN6_MUX         (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
0167
0168 /* Transition Control (Address 06h) */
0169 #define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT      7
0170 #define CS42XX8_TXCTL_DAC_SNGVOL_MASK       (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
0171 #define CS42XX8_TXCTL_DAC_SNGVOL        (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
0172 #define CS42XX8_TXCTL_DAC_SZC_SHIFT     5
0173 #define CS42XX8_TXCTL_DAC_SZC_WIDTH     2
0174 #define CS42XX8_TXCTL_DAC_SZC_MASK      (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT)
0175 #define CS42XX8_TXCTL_DAC_SZC_IC        (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
0176 #define CS42XX8_TXCTL_DAC_SZC_ZC        (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
0177 #define CS42XX8_TXCTL_DAC_SZC_SR        (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
0178 #define CS42XX8_TXCTL_DAC_SZC_SRZC      (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
0179 #define CS42XX8_TXCTL_AMUTE_SHIFT       4
0180 #define CS42XX8_TXCTL_AMUTE_MASK        (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
0181 #define CS42XX8_TXCTL_AMUTE         (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
0182 #define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT     3
0183 #define CS42XX8_TXCTL_MUTE_ADC_SP_MASK      (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
0184 #define CS42XX8_TXCTL_MUTE_ADC_SP       (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
0185 #define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT      2
0186 #define CS42XX8_TXCTL_ADC_SNGVOL_MASK       (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
0187 #define CS42XX8_TXCTL_ADC_SNGVOL        (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
0188 #define CS42XX8_TXCTL_ADC_SZC_SHIFT     0
0189 #define CS42XX8_TXCTL_ADC_SZC_MASK      (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT)
0190 #define CS42XX8_TXCTL_ADC_SZC_IC        (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
0191 #define CS42XX8_TXCTL_ADC_SZC_ZC        (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
0192 #define CS42XX8_TXCTL_ADC_SZC_SR        (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
0193 #define CS42XX8_TXCTL_ADC_SZC_SRZC      (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
0194
0195 /* DAC Channel Mute (Address 07h) */
0196 #define CS42XX8_DACMUTE_AOUT(n)         (0x1 << n)
0197 #define CS42XX8_DACMUTE_ALL         0xff
0198
0199 /* Status Control (Address 18h)*/
0200 #define CS42XX8_STATUSCTL_INI_SHIFT     2
0201 #define CS42XX8_STATUSCTL_INI_WIDTH     2
0202 #define CS42XX8_STATUSCTL_INI_MASK      (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT)
0203 #define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH   (0 << CS42XX8_STATUSCTL_INI_SHIFT)
0204 #define CS42XX8_STATUSCTL_INT_ACTIVE_LOW    (1 << CS42XX8_STATUSCTL_INI_SHIFT)
0205 #define CS42XX8_STATUSCTL_INT_OPEN_DRAIN    (2 << CS42XX8_STATUSCTL_INI_SHIFT)
0206
0207 /* Status (Address 19h)*/
0208 #define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT    4
0209 #define CS42XX8_STATUS_DAC_CLK_ERR_MASK     (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT)
0210 #define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT    3
0211 #define CS42XX8_STATUS_ADC_CLK_ERR_MASK     (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT)
0212 #define CS42XX8_STATUS_ADC3_OVFL_SHIFT      2
0213 #define CS42XX8_STATUS_ADC3_OVFL_MASK       (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT)
0214 #define CS42XX8_STATUS_ADC2_OVFL_SHIFT      1
0215 #define CS42XX8_STATUS_ADC2_OVFL_MASK       (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT)
0216 #define CS42XX8_STATUS_ADC1_OVFL_SHIFT      0
0217 #define CS42XX8_STATUS_ADC1_OVFL_MASK       (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT)
0218
0219 /* Status Mask (Address 1Ah) */
0220 #define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT  4
0221 #define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK   (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT)
0222 #define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT  3
0223 #define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK   (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT)
0224 #define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT    2
0225 #define CS42XX8_STATUS_ADC3_OVFL_M_MASK     (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT)
0226 #define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT    1
0227 #define CS42XX8_STATUS_ADC2_OVFL_M_MASK     (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT)
0228 #define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT    0
0229 #define CS42XX8_STATUS_ADC1_OVFL_M_MASK     (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT)
0230
0231 /* MUTEC Pin Control (Address 1Bh) */
0232 #define CS42XX8_MUTEC_MCPOLARITY_SHIFT      1
0233 #define CS42XX8_MUTEC_MCPOLARITY_MASK       (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
0234 #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
0235 #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH    (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
0236 #define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT    0
0237 #define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK     (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
0238 #define CS42XX8_MUTEC_MUTEC_ACTIVE      (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
0239 #endif /* _CS42XX8_H */