soc/codecs/cs42l73.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ALSA SoC CS42L73 codec driver
0004  *
0005  * Copyright 2011 Cirrus Logic, Inc.
0006  *
0007  * Author: Georgi Vlaev <joe@nucleusys.com>
0008  *     Brian Austin <brian.austin@cirrus.com>
0009  */
0010
0011 #ifndef __CS42L73_H__
0012 #define __CS42L73_H__
0013
0014 /* I2C Registers */
0015 /* I2C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read) */
0016 #define CS42L73_CHIP_ID     0x4a
0017 #define CS42L73_DEVID_AB    0x01    /* Device ID A & B [RO]. */
0018 #define CS42L73_DEVID_CD    0x02    /* Device ID C & D [RO]. */
0019 #define CS42L73_DEVID_E     0x03    /* Device ID E [RO]. */
0020 #define CS42L73_REVID       0x05    /* Revision ID [RO]. */
0021 #define CS42L73_PWRCTL1     0x06    /* Power Control 1. */
0022 #define CS42L73_PWRCTL2     0x07    /* Power Control 2. */
0023 #define CS42L73_PWRCTL3     0x08    /* Power Control 3. */
0024 #define CS42L73_CPFCHC      0x09    /* Charge Pump Freq. Class H Ctl. */
0025 #define CS42L73_OLMBMSDC    0x0A    /* Output Load, MIC Bias, MIC2 SDT */
0026 #define CS42L73_DMMCC       0x0B    /* Digital MIC & Master Clock Ctl. */
0027 #define CS42L73_XSPC        0x0C    /* Auxiliary Serial Port (XSP) Ctl. */
0028 #define CS42L73_XSPMMCC     0x0D    /* XSP Master Mode Clocking Control. */
0029 #define CS42L73_ASPC        0x0E    /* Audio Serial Port (ASP) Control. */
0030 #define CS42L73_ASPMMCC     0x0F    /* ASP Master Mode Clocking Control. */
0031 #define CS42L73_VSPC        0x10    /* Voice Serial Port (VSP) Control. */
0032 #define CS42L73_VSPMMCC     0x11    /* VSP Master Mode Clocking Control. */
0033 #define CS42L73_VXSPFS      0x12    /* VSP & XSP Sample Rate. */
0034 #define CS42L73_MIOPC       0x13    /* Misc. Input & Output Path Control. */
0035 #define CS42L73_ADCIPC      0x14    /* ADC/IP Control. */
0036 #define CS42L73_MICAPREPGAAVOL  0x15    /* MIC 1 [A] PreAmp, PGAA Vol. */
0037 #define CS42L73_MICBPREPGABVOL  0x16    /* MIC 2 [B] PreAmp, PGAB Vol. */
0038 #define CS42L73_IPADVOL     0x17    /* Input Pat7h A Digital Volume. */
0039 #define CS42L73_IPBDVOL     0x18    /* Input Path B Digital Volume. */
0040 #define CS42L73_PBDC        0x19    /* Playback Digital Control. */
0041 #define CS42L73_HLADVOL     0x1A    /* HP/Line A Out Digital Vol. */
0042 #define CS42L73_HLBDVOL     0x1B    /* HP/Line B Out Digital Vol. */
0043 #define CS42L73_SPKDVOL     0x1C    /* Spkphone Out [A] Digital Vol. */
0044 #define CS42L73_ESLDVOL     0x1D    /* Ear/Spkphone LO [B] Digital */
0045 #define CS42L73_HPAAVOL     0x1E    /* HP A Analog Volume. */
0046 #define CS42L73_HPBAVOL     0x1F    /* HP B Analog Volume. */
0047 #define CS42L73_LOAAVOL     0x20    /* Line Out A Analog Volume. */
0048 #define CS42L73_LOBAVOL     0x21    /* Line Out B Analog Volume. */
0049 #define CS42L73_STRINV      0x22    /* Stereo Input Path Adv. Vol. */
0050 #define CS42L73_XSPINV      0x23    /* Auxiliary Port Input Advisory Vol. */
0051 #define CS42L73_ASPINV      0x24    /* Audio Port Input Advisory Vol. */
0052 #define CS42L73_VSPINV      0x25    /* Voice Port Input Advisory Vol. */
0053 #define CS42L73_LIMARATEHL  0x26    /* Lmtr Attack Rate HP/Line. */
0054 #define CS42L73_LIMRRATEHL  0x27    /* Lmtr Ctl, Rel.Rate HP/Line. */
0055 #define CS42L73_LMAXHL      0x28    /* Lmtr Thresholds HP/Line. */
0056 #define CS42L73_LIMARATESPK 0x29    /* Lmtr Attack Rate Spkphone [A]. */
0057 #define CS42L73_LIMRRATESPK 0x2A    /* Lmtr Ctl,Release Rate Spk. [A]. */
0058 #define CS42L73_LMAXSPK     0x2B    /* Lmtr Thresholds Spkphone [A]. */
0059 #define CS42L73_LIMARATEESL 0x2C    /* Lmtr Attack Rate  */
0060 #define CS42L73_LIMRRATEESL 0x2D    /* Lmtr Ctl,Release Rate */
0061 #define CS42L73_LMAXESL     0x2E    /* Lmtr Thresholds */
0062 #define CS42L73_ALCARATE    0x2F    /* ALC Enable, Attack Rate AB. */
0063 #define CS42L73_ALCRRATE    0x30    /* ALC Release Rate AB.  */
0064 #define CS42L73_ALCMINMAX   0x31    /* ALC Thresholds AB. */
0065 #define CS42L73_NGCAB       0x32    /* Noise Gate Ctl AB. */
0066 #define CS42L73_ALCNGMC     0x33    /* ALC & Noise Gate Misc Ctl. */
0067 #define CS42L73_MIXERCTL    0x34    /* Mixer Control. */
0068 #define CS42L73_HLAIPAA     0x35    /* HP/LO Left Mixer: L. */
0069 #define CS42L73_HLBIPBA     0x36    /* HP/LO Right Mixer: R.  */
0070 #define CS42L73_HLAXSPAA    0x37    /* HP/LO Left Mixer: XSP L */
0071 #define CS42L73_HLBXSPBA    0x38    /* HP/LO Right Mixer: XSP R */
0072 #define CS42L73_HLAASPAA    0x39    /* HP/LO Left Mixer: ASP L */
0073 #define CS42L73_HLBASPBA    0x3A    /* HP/LO Right Mixer: ASP R */
0074 #define CS42L73_HLAVSPMA    0x3B    /* HP/LO Left Mixer: VSP. */
0075 #define CS42L73_HLBVSPMA    0x3C    /* HP/LO Right Mixer: VSP */
0076 #define CS42L73_XSPAIPAA    0x3D    /* XSP Left Mixer: Left */
0077 #define CS42L73_XSPBIPBA    0x3E    /* XSP Rt. Mixer: Right */
0078 #define CS42L73_XSPAXSPAA   0x3F    /* XSP Left Mixer: XSP L */
0079 #define CS42L73_XSPBXSPBA   0x40    /* XSP Rt. Mixer: XSP R */
0080 #define CS42L73_XSPAASPAA   0x41    /* XSP Left Mixer: ASP L */
0081 #define CS42L73_XSPAASPBA   0x42    /* XSP Rt. Mixer: ASP R */
0082 #define CS42L73_XSPAVSPMA   0x43    /* XSP Left Mixer: VSP */
0083 #define CS42L73_XSPBVSPMA   0x44    /* XSP Rt. Mixer: VSP */
0084 #define CS42L73_ASPAIPAA    0x45    /* ASP Left Mixer: Left */
0085 #define CS42L73_ASPBIPBA    0x46    /* ASP Rt. Mixer: Right */
0086 #define CS42L73_ASPAXSPAA   0x47    /* ASP Left Mixer: XSP L */
0087 #define CS42L73_ASPBXSPBA   0x48    /* ASP Rt. Mixer: XSP R */
0088 #define CS42L73_ASPAASPAA   0x49    /* ASP Left Mixer: ASP L */
0089 #define CS42L73_ASPBASPBA   0x4A    /* ASP Rt. Mixer: ASP R */
0090 #define CS42L73_ASPAVSPMA   0x4B    /* ASP Left Mixer: VSP */
0091 #define CS42L73_ASPBVSPMA   0x4C    /* ASP Rt. Mixer: VSP */
0092 #define CS42L73_VSPAIPAA    0x4D    /* VSP Left Mixer: Left */
0093 #define CS42L73_VSPBIPBA    0x4E    /* VSP Rt. Mixer: Right */
0094 #define CS42L73_VSPAXSPAA   0x4F    /* VSP Left Mixer: XSP L */
0095 #define CS42L73_VSPBXSPBA   0x50    /* VSP Rt. Mixer: XSP R */
0096 #define CS42L73_VSPAASPAA   0x51    /* VSP Left Mixer: ASP Left */
0097 #define CS42L73_VSPBASPBA   0x52    /* VSP Rt. Mixer: ASP Right */
0098 #define CS42L73_VSPAVSPMA   0x53    /* VSP Left Mixer: VSP */
0099 #define CS42L73_VSPBVSPMA   0x54    /* VSP Rt. Mixer: VSP */
0100 #define CS42L73_MMIXCTL     0x55    /* Mono Mixer Controls. */
0101 #define CS42L73_SPKMIPMA    0x56    /* SPK Mono Mixer: In. Path */
0102 #define CS42L73_SPKMXSPA    0x57    /* SPK Mono Mixer: XSP Mono/L/R Att. */
0103 #define CS42L73_SPKMASPA    0x58    /* SPK Mono Mixer: ASP Mono/L/R Att. */
0104 #define CS42L73_SPKMVSPMA   0x59    /* SPK Mono Mixer: VSP Mono Atten. */
0105 #define CS42L73_ESLMIPMA    0x5A    /* Ear/SpLO Mono Mixer: */
0106 #define CS42L73_ESLMXSPA    0x5B    /* Ear/SpLO Mono Mixer: XSP */
0107 #define CS42L73_ESLMASPA    0x5C    /* Ear/SpLO Mono Mixer: ASP */
0108 #define CS42L73_ESLMVSPMA   0x5D    /* Ear/SpLO Mono Mixer: VSP */
0109 #define CS42L73_IM1     0x5E    /* Interrupt Mask 1.  */
0110 #define CS42L73_IM2     0x5F    /* Interrupt Mask 2. */
0111 #define CS42L73_IS1     0x60    /* Interrupt Status 1 [RO]. */
0112 #define CS42L73_IS2     0x61    /* Interrupt Status 2 [RO]. */
0113 #define CS42L73_MAX_REGISTER    0x61    /* Total Registers */
0114 /* Bitfield Definitions */
0115
0116 /* CS42L73_PWRCTL1 */
0117 #define CS42L73_PDN_ADCB        (1 << 7)
0118 #define CS42L73_PDN_DMICB       (1 << 6)
0119 #define CS42L73_PDN_ADCA        (1 << 5)
0120 #define CS42L73_PDN_DMICA       (1 << 4)
0121 #define CS42L73_PDN_LDO         (1 << 2)
0122 #define CS42L73_DISCHG_FILT     (1 << 1)
0123 #define CS42L73_PDN         (1 << 0)
0124
0125 /* CS42L73_PWRCTL2 */
0126 #define CS42L73_PDN_MIC2_BIAS       (1 << 7)
0127 #define CS42L73_PDN_MIC1_BIAS       (1 << 6)
0128 #define CS42L73_PDN_VSP         (1 << 4)
0129 #define CS42L73_PDN_ASP_SDOUT       (1 << 3)
0130 #define CS42L73_PDN_ASP_SDIN        (1 << 2)
0131 #define CS42L73_PDN_XSP_SDOUT       (1 << 1)
0132 #define CS42L73_PDN_XSP_SDIN        (1 << 0)
0133
0134 /* CS42L73_PWRCTL3 */
0135 #define CS42L73_PDN_THMS        (1 << 5)
0136 #define CS42L73_PDN_SPKLO       (1 << 4)
0137 #define CS42L73_PDN_EAR         (1 << 3)
0138 #define CS42L73_PDN_SPK         (1 << 2)
0139 #define CS42L73_PDN_LO          (1 << 1)
0140 #define CS42L73_PDN_HP          (1 << 0)
0141
0142 /* Thermal Overload Detect. Requires interrupt ... */
0143 #define CS42L73_THMOVLD_150C        0
0144 #define CS42L73_THMOVLD_132C        1
0145 #define CS42L73_THMOVLD_115C        2
0146 #define CS42L73_THMOVLD_098C        3
0147
0148 #define CS42L73_CHARGEPUMP_MASK (0xF0)
0149
0150 /* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */
0151 #define CS42L73_SP_3ST          (1 << 7)
0152 #define CS42L73_SPDIF_I2S       (0 << 6)
0153 #define CS42L73_SPDIF_PCM       (1 << 6)
0154 #define CS42L73_PCM_MODE0       (0 << 4)
0155 #define CS42L73_PCM_MODE1       (1 << 4)
0156 #define CS42L73_PCM_MODE2       (2 << 4)
0157 #define CS42L73_PCM_MODE_MASK       (3 << 4)
0158 #define CS42L73_PCM_BIT_ORDER       (1 << 3)
0159 #define CS42L73_MCK_SCLK_64FS       (0 << 0)
0160 #define CS42L73_MCK_SCLK_MCLK       (2 << 0)
0161 #define CS42L73_MCK_SCLK_PREMCLK    (3 << 0)
0162
0163 /* CS42L73_xSPMMCC */
0164 #define CS42L73_MS_MASTER       (1 << 7)
0165
0166
0167 /* CS42L73_DMMCC */
0168 #define CS42L73_MCLKDIS         (1 << 0)
0169 #define CS42L73_MCLKSEL_MCLK2       (1 << 4)
0170 #define CS42L73_MCLKSEL_MCLK1       (0 << 4)
0171
0172 /* CS42L73 MCLK derived from MCLK1 or MCLK2 */
0173 #define CS42L73_CLKID_MCLK1     0
0174 #define CS42L73_CLKID_MCLK2     1
0175
0176 #define CS42L73_MCLKXDIV    0
0177 #define CS42L73_MMCCDIV         1
0178
0179 #define CS42L73_XSP     0
0180 #define CS42L73_ASP     1
0181 #define CS42L73_VSP     2
0182
0183 /* IS1, IM1 */
0184 #define CS42L73_MIC2_SDET       (1 << 6)
0185 #define CS42L73_THMOVLD         (1 << 4)
0186 #define CS42L73_DIGMIXOVFL      (1 << 3)
0187 #define CS42L73_IPBOVFL         (1 << 1)
0188 #define CS42L73_IPAOVFL         (1 << 0)
0189
0190 /* Analog Softramp */
0191 #define CS42L73_ANLGOSFT        (1 << 0)
0192
0193 /* HP A/B Analog Mute */
0194 #define CS42L73_HPA_MUTE        (1 << 7)
0195 /* LO A/B Analog Mute   */
0196 #define CS42L73_LOA_MUTE        (1 << 7)
0197 /* Digital Mute */
0198 #define CS42L73_HLAD_MUTE       (1 << 0)
0199 #define CS42L73_HLBD_MUTE       (1 << 1)
0200 #define CS42L73_SPKD_MUTE       (1 << 2)
0201 #define CS42L73_ESLD_MUTE       (1 << 3)
0202
0203 /* Misc defines for codec */
0204 #define CS42L73_DEVID       0x00042A73
0205 #define CS42L73_MCLKX_MIN   5644800
0206 #define CS42L73_MCLKX_MAX   38400000
0207
0208 #define CS42L73_SPC(id)     (CS42L73_XSPC + (id << 1))
0209 #define CS42L73_MMCC(id)    (CS42L73_XSPMMCC + (id << 1))
0210 #define CS42L73_SPFS(id)    ((id == CS42L73_ASP) ? CS42L73_ASPC : CS42L73_VXSPFS)
0211
0212 #endif  /* __CS42L73_H__ */