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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cs42l73.c  --  CS42L73 ALSA Soc Audio driver
0004  *
0005  * Copyright 2011 Cirrus Logic, Inc.
0006  *
0007  * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
0008  *      Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/pm.h>
0018 #include <linux/i2c.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/soc-dapm.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028 #include <sound/cs42l73.h>
0029 #include "cs42l73.h"
0030 #include "cirrus_legacy.h"
0031 
0032 struct sp_config {
0033     u8 spc, mmcc, spfs;
0034     u32 srate;
0035 };
0036 struct  cs42l73_private {
0037     struct cs42l73_platform_data pdata;
0038     struct sp_config config[3];
0039     struct regmap *regmap;
0040     u32 sysclk;
0041     u8 mclksel;
0042     u32 mclk;
0043     int shutdwn_delay;
0044 };
0045 
0046 static const struct reg_default cs42l73_reg_defaults[] = {
0047     { 6, 0xF1 },    /* r06  - Power Ctl 1 */
0048     { 7, 0xDF },    /* r07  - Power Ctl 2 */
0049     { 8, 0x3F },    /* r08  - Power Ctl 3 */
0050     { 9, 0x50 },    /* r09  - Charge Pump Freq */
0051     { 10, 0x53 },   /* r0A  - Output Load MicBias Short Detect */
0052     { 11, 0x00 },   /* r0B  - DMIC Master Clock Ctl */
0053     { 12, 0x00 },   /* r0C  - Aux PCM Ctl */
0054     { 13, 0x15 },   /* r0D  - Aux PCM Master Clock Ctl */
0055     { 14, 0x00 },   /* r0E  - Audio PCM Ctl */
0056     { 15, 0x15 },   /* r0F  - Audio PCM Master Clock Ctl */
0057     { 16, 0x00 },   /* r10  - Voice PCM Ctl */
0058     { 17, 0x15 },   /* r11  - Voice PCM Master Clock Ctl */
0059     { 18, 0x00 },   /* r12  - Voice/Aux Sample Rate */
0060     { 19, 0x06 },   /* r13  - Misc I/O Path Ctl */
0061     { 20, 0x00 },   /* r14  - ADC Input Path Ctl */
0062     { 21, 0x00 },   /* r15  - MICA Preamp, PGA Volume */
0063     { 22, 0x00 },   /* r16  - MICB Preamp, PGA Volume */
0064     { 23, 0x00 },   /* r17  - Input Path A Digital Volume */
0065     { 24, 0x00 },   /* r18  - Input Path B Digital Volume */
0066     { 25, 0x00 },   /* r19  - Playback Digital Ctl */
0067     { 26, 0x00 },   /* r1A  - HP/LO Left Digital Volume */
0068     { 27, 0x00 },   /* r1B  - HP/LO Right Digital Volume */
0069     { 28, 0x00 },   /* r1C  - Speakerphone Digital Volume */
0070     { 29, 0x00 },   /* r1D  - Ear/SPKLO Digital Volume */
0071     { 30, 0x00 },   /* r1E  - HP Left Analog Volume */
0072     { 31, 0x00 },   /* r1F  - HP Right Analog Volume */
0073     { 32, 0x00 },   /* r20  - LO Left Analog Volume */
0074     { 33, 0x00 },   /* r21  - LO Right Analog Volume */
0075     { 34, 0x00 },   /* r22  - Stereo Input Path Advisory Volume */
0076     { 35, 0x00 },   /* r23  - Aux PCM Input Advisory Volume */
0077     { 36, 0x00 },   /* r24  - Audio PCM Input Advisory Volume */
0078     { 37, 0x00 },   /* r25  - Voice PCM Input Advisory Volume */
0079     { 38, 0x00 },   /* r26  - Limiter Attack Rate HP/LO */
0080     { 39, 0x7F },   /* r27  - Limter Ctl, Release Rate HP/LO */
0081     { 40, 0x00 },   /* r28  - Limter Threshold HP/LO */
0082     { 41, 0x00 },   /* r29  - Limiter Attack Rate Speakerphone */
0083     { 42, 0x3F },   /* r2A  - Limter Ctl, Release Rate Speakerphone */
0084     { 43, 0x00 },   /* r2B  - Limter Threshold Speakerphone */
0085     { 44, 0x00 },   /* r2C  - Limiter Attack Rate Ear/SPKLO */
0086     { 45, 0x3F },   /* r2D  - Limter Ctl, Release Rate Ear/SPKLO */
0087     { 46, 0x00 },   /* r2E  - Limter Threshold Ear/SPKLO */
0088     { 47, 0x00 },   /* r2F  - ALC Enable, Attack Rate Left/Right */
0089     { 48, 0x3F },   /* r30  - ALC Release Rate Left/Right */
0090     { 49, 0x00 },   /* r31  - ALC Threshold Left/Right */
0091     { 50, 0x00 },   /* r32  - Noise Gate Ctl Left/Right */
0092     { 51, 0x00 },   /* r33  - ALC/NG Misc Ctl */
0093     { 52, 0x18 },   /* r34  - Mixer Ctl */
0094     { 53, 0x3F },   /* r35  - HP/LO Left Mixer Input Path Volume */
0095     { 54, 0x3F },   /* r36  - HP/LO Right Mixer Input Path Volume */
0096     { 55, 0x3F },   /* r37  - HP/LO Left Mixer Aux PCM Volume */
0097     { 56, 0x3F },   /* r38  - HP/LO Right Mixer Aux PCM Volume */
0098     { 57, 0x3F },   /* r39  - HP/LO Left Mixer Audio PCM Volume */
0099     { 58, 0x3F },   /* r3A  - HP/LO Right Mixer Audio PCM Volume */
0100     { 59, 0x3F },   /* r3B  - HP/LO Left Mixer Voice PCM Mono Volume */
0101     { 60, 0x3F },   /* r3C  - HP/LO Right Mixer Voice PCM Mono Volume */
0102     { 61, 0x3F },   /* r3D  - Aux PCM Left Mixer Input Path Volume */
0103     { 62, 0x3F },   /* r3E  - Aux PCM Right Mixer Input Path Volume */
0104     { 63, 0x3F },   /* r3F  - Aux PCM Left Mixer Volume */
0105     { 64, 0x3F },   /* r40  - Aux PCM Left Mixer Volume */
0106     { 65, 0x3F },   /* r41  - Aux PCM Left Mixer Audio PCM L Volume */
0107     { 66, 0x3F },   /* r42  - Aux PCM Right Mixer Audio PCM R Volume */
0108     { 67, 0x3F },   /* r43  - Aux PCM Left Mixer Voice PCM Volume */
0109     { 68, 0x3F },   /* r44  - Aux PCM Right Mixer Voice PCM Volume */
0110     { 69, 0x3F },   /* r45  - Audio PCM Left Input Path Volume */
0111     { 70, 0x3F },   /* r46  - Audio PCM Right Input Path Volume */
0112     { 71, 0x3F },   /* r47  - Audio PCM Left Mixer Aux PCM L Volume */
0113     { 72, 0x3F },   /* r48  - Audio PCM Right Mixer Aux PCM R Volume */
0114     { 73, 0x3F },   /* r49  - Audio PCM Left Mixer Volume */
0115     { 74, 0x3F },   /* r4A  - Audio PCM Right Mixer Volume */
0116     { 75, 0x3F },   /* r4B  - Audio PCM Left Mixer Voice PCM Volume */
0117     { 76, 0x3F },   /* r4C  - Audio PCM Right Mixer Voice PCM Volume */
0118     { 77, 0x3F },   /* r4D  - Voice PCM Left Input Path Volume */
0119     { 78, 0x3F },   /* r4E  - Voice PCM Right Input Path Volume */
0120     { 79, 0x3F },   /* r4F  - Voice PCM Left Mixer Aux PCM L Volume */
0121     { 80, 0x3F },   /* r50  - Voice PCM Right Mixer Aux PCM R Volume */
0122     { 81, 0x3F },   /* r51  - Voice PCM Left Mixer Audio PCM L Volume */
0123     { 82, 0x3F },   /* r52  - Voice PCM Right Mixer Audio PCM R Volume */
0124     { 83, 0x3F },   /* r53  - Voice PCM Left Mixer Voice PCM Volume */
0125     { 84, 0x3F },   /* r54  - Voice PCM Right Mixer Voice PCM Volume */
0126     { 85, 0xAA },   /* r55  - Mono Mixer Ctl */
0127     { 86, 0x3F },   /* r56  - SPK Mono Mixer Input Path Volume */
0128     { 87, 0x3F },   /* r57  - SPK Mono Mixer Aux PCM Mono/L/R Volume */
0129     { 88, 0x3F },   /* r58  - SPK Mono Mixer Audio PCM Mono/L/R Volume */
0130     { 89, 0x3F },   /* r59  - SPK Mono Mixer Voice PCM Mono Volume */
0131     { 90, 0x3F },   /* r5A  - SPKLO Mono Mixer Input Path Mono Volume */
0132     { 91, 0x3F },   /* r5B  - SPKLO Mono Mixer Aux Mono/L/R Volume */
0133     { 92, 0x3F },   /* r5C  - SPKLO Mono Mixer Audio Mono/L/R Volume */
0134     { 93, 0x3F },   /* r5D  - SPKLO Mono Mixer Voice Mono Volume */
0135     { 94, 0x00 },   /* r5E  - Interrupt Mask 1 */
0136     { 95, 0x00 },   /* r5F  - Interrupt Mask 2 */
0137 };
0138 
0139 static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
0140 {
0141     switch (reg) {
0142     case CS42L73_IS1:
0143     case CS42L73_IS2:
0144         return true;
0145     default:
0146         return false;
0147     }
0148 }
0149 
0150 static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
0151 {
0152     switch (reg) {
0153     case CS42L73_DEVID_AB ... CS42L73_DEVID_E:
0154     case CS42L73_REVID ... CS42L73_IM2:
0155         return true;
0156     default:
0157         return false;
0158     }
0159 }
0160 
0161 static const DECLARE_TLV_DB_RANGE(hpaloa_tlv,
0162     0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
0163     14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
0164 );
0165 
0166 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
0167 
0168 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
0169 
0170 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
0171 
0172 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
0173 
0174 static const DECLARE_TLV_DB_RANGE(limiter_tlv,
0175     0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
0176     3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
0177 );
0178 
0179 static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
0180 
0181 static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
0182 static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
0183 
0184 static SOC_ENUM_SINGLE_DECL(pgaa_enum,
0185                 CS42L73_ADCIPC, 3,
0186                 cs42l73_pgaa_text);
0187 
0188 static SOC_ENUM_SINGLE_DECL(pgab_enum,
0189                 CS42L73_ADCIPC, 7,
0190                 cs42l73_pgab_text);
0191 
0192 static const struct snd_kcontrol_new pgaa_mux =
0193     SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
0194 
0195 static const struct snd_kcontrol_new pgab_mux =
0196     SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
0197 
0198 static const struct snd_kcontrol_new input_left_mixer[] = {
0199     SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
0200             5, 1, 1),
0201     SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
0202             4, 1, 1),
0203 };
0204 
0205 static const struct snd_kcontrol_new input_right_mixer[] = {
0206     SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
0207             7, 1, 1),
0208     SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
0209             6, 1, 1),
0210 };
0211 
0212 static const char * const cs42l73_ng_delay_text[] = {
0213     "50ms", "100ms", "150ms", "200ms" };
0214 
0215 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
0216                 CS42L73_NGCAB, 0,
0217                 cs42l73_ng_delay_text);
0218 
0219 static const char * const cs42l73_mono_mix_texts[] = {
0220     "Left", "Right", "Mono Mix"};
0221 
0222 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
0223 
0224 static const struct soc_enum spk_asp_enum =
0225     SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3,
0226                   ARRAY_SIZE(cs42l73_mono_mix_texts),
0227                   cs42l73_mono_mix_texts,
0228                   cs42l73_mono_mix_values);
0229 
0230 static const struct snd_kcontrol_new spk_asp_mixer =
0231     SOC_DAPM_ENUM("Route", spk_asp_enum);
0232 
0233 static const struct soc_enum spk_xsp_enum =
0234     SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
0235                   ARRAY_SIZE(cs42l73_mono_mix_texts),
0236                   cs42l73_mono_mix_texts,
0237                   cs42l73_mono_mix_values);
0238 
0239 static const struct snd_kcontrol_new spk_xsp_mixer =
0240     SOC_DAPM_ENUM("Route", spk_xsp_enum);
0241 
0242 static const struct soc_enum esl_asp_enum =
0243     SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3,
0244                   ARRAY_SIZE(cs42l73_mono_mix_texts),
0245                   cs42l73_mono_mix_texts,
0246                   cs42l73_mono_mix_values);
0247 
0248 static const struct snd_kcontrol_new esl_asp_mixer =
0249     SOC_DAPM_ENUM("Route", esl_asp_enum);
0250 
0251 static const struct soc_enum esl_xsp_enum =
0252     SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
0253                   ARRAY_SIZE(cs42l73_mono_mix_texts),
0254                   cs42l73_mono_mix_texts,
0255                   cs42l73_mono_mix_values);
0256 
0257 static const struct snd_kcontrol_new esl_xsp_mixer =
0258     SOC_DAPM_ENUM("Route", esl_xsp_enum);
0259 
0260 static const char * const cs42l73_ip_swap_text[] = {
0261     "Stereo", "Mono A", "Mono B", "Swap A-B"};
0262 
0263 static SOC_ENUM_SINGLE_DECL(ip_swap_enum,
0264                 CS42L73_MIOPC, 6,
0265                 cs42l73_ip_swap_text);
0266 
0267 static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
0268 
0269 static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum,
0270                 CS42L73_MIXERCTL, 5,
0271                 cs42l73_spo_mixer_text);
0272 
0273 static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum,
0274                 CS42L73_MIXERCTL, 4,
0275                 cs42l73_spo_mixer_text);
0276 
0277 static const struct snd_kcontrol_new hp_amp_ctl =
0278     SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
0279 
0280 static const struct snd_kcontrol_new lo_amp_ctl =
0281     SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
0282 
0283 static const struct snd_kcontrol_new spk_amp_ctl =
0284     SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
0285 
0286 static const struct snd_kcontrol_new spklo_amp_ctl =
0287     SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
0288 
0289 static const struct snd_kcontrol_new ear_amp_ctl =
0290     SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
0291 
0292 static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
0293     SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
0294             CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
0295             0x41, 0x4B, hpaloa_tlv),
0296 
0297     SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
0298             CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
0299 
0300     SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
0301             CS42L73_MICBPREPGABVOL, 0, 0x34,
0302             0x24, micpga_tlv),
0303 
0304     SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
0305             CS42L73_MICBPREPGABVOL, 6, 1, 1),
0306 
0307     SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
0308             CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
0309 
0310     SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
0311             CS42L73_HLADVOL, CS42L73_HLBDVOL,
0312             0, 0x34, 0xE4, hl_tlv),
0313 
0314     SOC_SINGLE_TLV("ADC A Boost Volume",
0315             CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
0316 
0317     SOC_SINGLE_TLV("ADC B Boost Volume",
0318                CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
0319 
0320     SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
0321                 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
0322 
0323     SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
0324                 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
0325 
0326     SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
0327             CS42L73_HPBAVOL, 7, 1, 1),
0328 
0329     SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
0330             CS42L73_LOBAVOL, 7, 1, 1),
0331     SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
0332     SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
0333             1, 1, 1),
0334     SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
0335             1),
0336     SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
0337             1),
0338 
0339     SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
0340     SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
0341     SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
0342     SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
0343 
0344     SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
0345             0),
0346 
0347     SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
0348             0),
0349     SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
0350             0x3F, 0),
0351 
0352 
0353     SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
0354     SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
0355             0),
0356 
0357     SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
0358             1, limiter_tlv),
0359 
0360     SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
0361             limiter_tlv),
0362 
0363     SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
0364             0x3F, 0),
0365     SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
0366             0x3F, 0),
0367     SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
0368     SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
0369             6, 1, 0),
0370     SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
0371             7, 1, limiter_tlv),
0372 
0373     SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
0374             limiter_tlv),
0375 
0376     SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
0377             0x3F, 0),
0378     SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
0379             0x3F, 0),
0380     SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
0381     SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
0382             7, 1, limiter_tlv),
0383 
0384     SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
0385             limiter_tlv),
0386 
0387     SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
0388     SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
0389     SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
0390     SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
0391             limiter_tlv),
0392     SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
0393             limiter_tlv),
0394 
0395     SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
0396     SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
0397     /*
0398         NG Threshold depends on NG_BOOTSAB, which selects
0399         between two threshold scales in decibels.
0400         Set linear values for now ..
0401     */
0402     SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
0403     SOC_ENUM("NG Delay", ng_delay_enum),
0404 
0405     SOC_DOUBLE_R_TLV("XSP-IP Volume",
0406             CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
0407             attn_tlv),
0408     SOC_DOUBLE_R_TLV("XSP-XSP Volume",
0409             CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
0410             attn_tlv),
0411     SOC_DOUBLE_R_TLV("XSP-ASP Volume",
0412             CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
0413             attn_tlv),
0414     SOC_DOUBLE_R_TLV("XSP-VSP Volume",
0415             CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
0416             attn_tlv),
0417 
0418     SOC_DOUBLE_R_TLV("ASP-IP Volume",
0419             CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
0420             attn_tlv),
0421     SOC_DOUBLE_R_TLV("ASP-XSP Volume",
0422             CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
0423             attn_tlv),
0424     SOC_DOUBLE_R_TLV("ASP-ASP Volume",
0425             CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
0426             attn_tlv),
0427     SOC_DOUBLE_R_TLV("ASP-VSP Volume",
0428             CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
0429             attn_tlv),
0430 
0431     SOC_DOUBLE_R_TLV("VSP-IP Volume",
0432             CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
0433             attn_tlv),
0434     SOC_DOUBLE_R_TLV("VSP-XSP Volume",
0435             CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
0436             attn_tlv),
0437     SOC_DOUBLE_R_TLV("VSP-ASP Volume",
0438             CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
0439             attn_tlv),
0440     SOC_DOUBLE_R_TLV("VSP-VSP Volume",
0441             CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
0442             attn_tlv),
0443 
0444     SOC_DOUBLE_R_TLV("HL-IP Volume",
0445             CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
0446             attn_tlv),
0447     SOC_DOUBLE_R_TLV("HL-XSP Volume",
0448             CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
0449             attn_tlv),
0450     SOC_DOUBLE_R_TLV("HL-ASP Volume",
0451             CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
0452             attn_tlv),
0453     SOC_DOUBLE_R_TLV("HL-VSP Volume",
0454             CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
0455             attn_tlv),
0456 
0457     SOC_SINGLE_TLV("SPK-IP Mono Volume",
0458             CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
0459     SOC_SINGLE_TLV("SPK-XSP Mono Volume",
0460             CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
0461     SOC_SINGLE_TLV("SPK-ASP Mono Volume",
0462             CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
0463     SOC_SINGLE_TLV("SPK-VSP Mono Volume",
0464             CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
0465 
0466     SOC_SINGLE_TLV("ESL-IP Mono Volume",
0467             CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
0468     SOC_SINGLE_TLV("ESL-XSP Mono Volume",
0469             CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
0470     SOC_SINGLE_TLV("ESL-ASP Mono Volume",
0471             CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
0472     SOC_SINGLE_TLV("ESL-VSP Mono Volume",
0473             CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
0474 
0475     SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
0476 
0477     SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
0478     SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
0479 };
0480 
0481 static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
0482     struct snd_kcontrol *kcontrol, int event)
0483 {
0484     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0485     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0486     switch (event) {
0487     case SND_SOC_DAPM_POST_PMD:
0488         /* 150 ms delay between setting PDN and MCLKDIS */
0489         priv->shutdwn_delay = 150;
0490         break;
0491     default:
0492         pr_err("Invalid event = 0x%x\n", event);
0493     }
0494     return 0;
0495 }
0496 
0497 static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
0498     struct snd_kcontrol *kcontrol, int event)
0499 {
0500     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0501     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0502     switch (event) {
0503     case SND_SOC_DAPM_POST_PMD:
0504         /* 50 ms delay between setting PDN and MCLKDIS */
0505         if (priv->shutdwn_delay < 50)
0506             priv->shutdwn_delay = 50;
0507         break;
0508     default:
0509         pr_err("Invalid event = 0x%x\n", event);
0510     }
0511     return 0;
0512 }
0513 
0514 
0515 static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
0516     struct snd_kcontrol *kcontrol, int event)
0517 {
0518     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0519     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0520     switch (event) {
0521     case SND_SOC_DAPM_POST_PMD:
0522         /* 30 ms delay between setting PDN and MCLKDIS */
0523         if (priv->shutdwn_delay < 30)
0524             priv->shutdwn_delay = 30;
0525         break;
0526     default:
0527         pr_err("Invalid event = 0x%x\n", event);
0528     }
0529     return 0;
0530 }
0531 
0532 static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
0533     SND_SOC_DAPM_INPUT("DMICA"),
0534     SND_SOC_DAPM_INPUT("DMICB"),
0535     SND_SOC_DAPM_INPUT("LINEINA"),
0536     SND_SOC_DAPM_INPUT("LINEINB"),
0537     SND_SOC_DAPM_INPUT("MIC1"),
0538     SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
0539     SND_SOC_DAPM_INPUT("MIC2"),
0540     SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
0541 
0542     SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL,  0,
0543             CS42L73_PWRCTL2, 1, 1),
0544     SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL,  0,
0545             CS42L73_PWRCTL2, 1, 1),
0546     SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL,  0,
0547             CS42L73_PWRCTL2, 3, 1),
0548     SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL,  0,
0549             CS42L73_PWRCTL2, 3, 1),
0550     SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL,  0,
0551             CS42L73_PWRCTL2, 4, 1),
0552 
0553     SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
0554     SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
0555 
0556     SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
0557     SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
0558 
0559     SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
0560     SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
0561     SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
0562     SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
0563 
0564     SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
0565              0, 0, input_left_mixer,
0566              ARRAY_SIZE(input_left_mixer)),
0567 
0568     SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
0569             0, 0, input_right_mixer,
0570             ARRAY_SIZE(input_right_mixer)),
0571 
0572     SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0573     SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0574     SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0575     SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0576     SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0577 
0578     SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
0579                 CS42L73_PWRCTL2, 0, 1),
0580     SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
0581                 CS42L73_PWRCTL2, 0, 1),
0582     SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
0583                 CS42L73_PWRCTL2, 0, 1),
0584 
0585     SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
0586                 CS42L73_PWRCTL2, 2, 1),
0587     SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
0588                 CS42L73_PWRCTL2, 2, 1),
0589     SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
0590                 CS42L73_PWRCTL2, 2, 1),
0591 
0592     SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
0593                 CS42L73_PWRCTL2, 4, 1),
0594 
0595     SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0596     SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0597     SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0598     SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0599 
0600     SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
0601              0, 0, &esl_xsp_mixer),
0602 
0603     SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
0604              0, 0, &esl_asp_mixer),
0605 
0606     SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
0607              0, 0, &spk_asp_mixer),
0608 
0609     SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
0610              0, 0, &spk_xsp_mixer),
0611 
0612     SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
0613     SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
0614     SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
0615     SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
0616 
0617     SND_SOC_DAPM_SWITCH_E("HP Amp",  CS42L73_PWRCTL3, 0, 1,
0618                 &hp_amp_ctl, cs42l73_hp_amp_event,
0619             SND_SOC_DAPM_POST_PMD),
0620     SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
0621                 &lo_amp_ctl),
0622     SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
0623             &spk_amp_ctl, cs42l73_spklo_spk_amp_event,
0624             SND_SOC_DAPM_POST_PMD),
0625     SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
0626                 &ear_amp_ctl, cs42l73_ear_amp_event,
0627             SND_SOC_DAPM_POST_PMD),
0628     SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
0629                 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
0630             SND_SOC_DAPM_POST_PMD),
0631 
0632     SND_SOC_DAPM_OUTPUT("HPOUTA"),
0633     SND_SOC_DAPM_OUTPUT("HPOUTB"),
0634     SND_SOC_DAPM_OUTPUT("LINEOUTA"),
0635     SND_SOC_DAPM_OUTPUT("LINEOUTB"),
0636     SND_SOC_DAPM_OUTPUT("EAROUT"),
0637     SND_SOC_DAPM_OUTPUT("SPKOUT"),
0638     SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
0639 };
0640 
0641 static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
0642 
0643     /* SPKLO EARSPK Paths */
0644     {"EAROUT", NULL, "EAR Amp"},
0645     {"SPKLINEOUT", NULL, "SPKLO Amp"},
0646 
0647     {"EAR Amp", "Switch", "ESL DAC"},
0648     {"SPKLO Amp", "Switch", "ESL DAC"},
0649 
0650     {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
0651     {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
0652     {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
0653     /* Loopback */
0654     {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
0655     {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
0656 
0657     {"ESL Mixer", NULL, "ESL-ASP Mux"},
0658     {"ESL Mixer", NULL, "ESL-XSP Mux"},
0659 
0660     {"ESL-ASP Mux", "Left", "ASPINL"},
0661     {"ESL-ASP Mux", "Right", "ASPINR"},
0662     {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
0663 
0664     {"ESL-XSP Mux", "Left", "XSPINL"},
0665     {"ESL-XSP Mux", "Right", "XSPINR"},
0666     {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
0667 
0668     /* Speakerphone Paths */
0669     {"SPKOUT", NULL, "SPK Amp"},
0670     {"SPK Amp", "Switch", "SPK DAC"},
0671 
0672     {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
0673     {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
0674     {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
0675     /* Loopback */
0676     {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
0677     {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
0678 
0679     {"SPK Mixer", NULL, "SPK-ASP Mux"},
0680     {"SPK Mixer", NULL, "SPK-XSP Mux"},
0681 
0682     {"SPK-ASP Mux", "Left", "ASPINL"},
0683     {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
0684     {"SPK-ASP Mux", "Right", "ASPINR"},
0685 
0686     {"SPK-XSP Mux", "Left", "XSPINL"},
0687     {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
0688     {"SPK-XSP Mux", "Right", "XSPINR"},
0689 
0690     /* HP LineOUT Paths */
0691     {"HPOUTA", NULL, "HP Amp"},
0692     {"HPOUTB", NULL, "HP Amp"},
0693     {"LINEOUTA", NULL, "LO Amp"},
0694     {"LINEOUTB", NULL, "LO Amp"},
0695 
0696     {"HP Amp", "Switch", "HL Left DAC"},
0697     {"HP Amp", "Switch", "HL Right DAC"},
0698     {"LO Amp", "Switch", "HL Left DAC"},
0699     {"LO Amp", "Switch", "HL Right DAC"},
0700 
0701     {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
0702     {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
0703     {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
0704     {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
0705     {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
0706     {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
0707     /* Loopback */
0708     {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
0709     {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
0710     {"HL Left Mixer", NULL, "Input Left Capture"},
0711     {"HL Right Mixer", NULL, "Input Right Capture"},
0712 
0713     {"HL Left Mixer", NULL, "ASPINL"},
0714     {"HL Right Mixer", NULL, "ASPINR"},
0715     {"HL Left Mixer", NULL, "XSPINL"},
0716     {"HL Right Mixer", NULL, "XSPINR"},
0717     {"HL Left Mixer", NULL, "VSPINOUT"},
0718     {"HL Right Mixer", NULL, "VSPINOUT"},
0719 
0720     {"ASPINL", NULL, "ASP Playback"},
0721     {"ASPINM", NULL, "ASP Playback"},
0722     {"ASPINR", NULL, "ASP Playback"},
0723     {"XSPINL", NULL, "XSP Playback"},
0724     {"XSPINM", NULL, "XSP Playback"},
0725     {"XSPINR", NULL, "XSP Playback"},
0726     {"VSPINOUT", NULL, "VSP Playback"},
0727 
0728     /* Capture Paths */
0729     {"MIC1", NULL, "MIC1 Bias"},
0730     {"PGA Left Mux", "Mic 1", "MIC1"},
0731     {"MIC2", NULL, "MIC2 Bias"},
0732     {"PGA Right Mux", "Mic 2", "MIC2"},
0733 
0734     {"PGA Left Mux", "Line A", "LINEINA"},
0735     {"PGA Right Mux", "Line B", "LINEINB"},
0736 
0737     {"PGA Left", NULL, "PGA Left Mux"},
0738     {"PGA Right", NULL, "PGA Right Mux"},
0739 
0740     {"ADC Left", NULL, "PGA Left"},
0741     {"ADC Right", NULL, "PGA Right"},
0742     {"DMIC Left", NULL, "DMICA"},
0743     {"DMIC Right", NULL, "DMICB"},
0744 
0745     {"Input Left Capture", "ADC Left Input", "ADC Left"},
0746     {"Input Right Capture", "ADC Right Input", "ADC Right"},
0747     {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
0748     {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
0749 
0750     /* Audio Capture */
0751     {"ASPL Output Mixer", NULL, "Input Left Capture"},
0752     {"ASPR Output Mixer", NULL, "Input Right Capture"},
0753 
0754     {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
0755     {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
0756 
0757     /* Auxillary Capture */
0758     {"XSPL Output Mixer", NULL, "Input Left Capture"},
0759     {"XSPR Output Mixer", NULL, "Input Right Capture"},
0760 
0761     {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
0762     {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
0763 
0764     {"XSPOUTL", NULL, "XSPL Output Mixer"},
0765     {"XSPOUTR", NULL, "XSPR Output Mixer"},
0766 
0767     /* Voice Capture */
0768     {"VSP Output Mixer", NULL, "Input Left Capture"},
0769     {"VSP Output Mixer", NULL, "Input Right Capture"},
0770 
0771     {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
0772 
0773     {"VSPINOUT", NULL, "VSP Output Mixer"},
0774 
0775     {"ASP Capture", NULL, "ASPOUTL"},
0776     {"ASP Capture", NULL, "ASPOUTR"},
0777     {"XSP Capture", NULL, "XSPOUTL"},
0778     {"XSP Capture", NULL, "XSPOUTR"},
0779     {"VSP Capture", NULL, "VSPINOUT"},
0780 };
0781 
0782 struct cs42l73_mclk_div {
0783     u32 mclk;
0784     u32 srate;
0785     u8 mmcc;
0786 };
0787 
0788 static const struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
0789     /* MCLK, Sample Rate, xMMCC[5:0] */
0790     {5644800, 11025, 0x30},
0791     {5644800, 22050, 0x20},
0792     {5644800, 44100, 0x10},
0793 
0794     {6000000,  8000, 0x39},
0795     {6000000, 11025, 0x33},
0796     {6000000, 12000, 0x31},
0797     {6000000, 16000, 0x29},
0798     {6000000, 22050, 0x23},
0799     {6000000, 24000, 0x21},
0800     {6000000, 32000, 0x19},
0801     {6000000, 44100, 0x13},
0802     {6000000, 48000, 0x11},
0803 
0804     {6144000,  8000, 0x38},
0805     {6144000, 12000, 0x30},
0806     {6144000, 16000, 0x28},
0807     {6144000, 24000, 0x20},
0808     {6144000, 32000, 0x18},
0809     {6144000, 48000, 0x10},
0810 
0811     {6500000,  8000, 0x3C},
0812     {6500000, 11025, 0x35},
0813     {6500000, 12000, 0x34},
0814     {6500000, 16000, 0x2C},
0815     {6500000, 22050, 0x25},
0816     {6500000, 24000, 0x24},
0817     {6500000, 32000, 0x1C},
0818     {6500000, 44100, 0x15},
0819     {6500000, 48000, 0x14},
0820 
0821     {6400000,  8000, 0x3E},
0822     {6400000, 11025, 0x37},
0823     {6400000, 12000, 0x36},
0824     {6400000, 16000, 0x2E},
0825     {6400000, 22050, 0x27},
0826     {6400000, 24000, 0x26},
0827     {6400000, 32000, 0x1E},
0828     {6400000, 44100, 0x17},
0829     {6400000, 48000, 0x16},
0830 };
0831 
0832 struct cs42l73_mclkx_div {
0833     u32 mclkx;
0834     u8 ratio;
0835     u8 mclkdiv;
0836 };
0837 
0838 static const struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
0839     {5644800,  1, 0},   /* 5644800 */
0840     {6000000,  1, 0},   /* 6000000 */
0841     {6144000,  1, 0},   /* 6144000 */
0842     {11289600, 2, 2},   /* 5644800 */
0843     {12288000, 2, 2},   /* 6144000 */
0844     {12000000, 2, 2},   /* 6000000 */
0845     {13000000, 2, 2},   /* 6500000 */
0846     {19200000, 3, 3},   /* 6400000 */
0847     {24000000, 4, 4},   /* 6000000 */
0848     {26000000, 4, 4},   /* 6500000 */
0849     {38400000, 6, 5}    /* 6400000 */
0850 };
0851 
0852 static int cs42l73_get_mclkx_coeff(int mclkx)
0853 {
0854     int i;
0855 
0856     for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
0857         if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
0858             return i;
0859     }
0860     return -EINVAL;
0861 }
0862 
0863 static int cs42l73_get_mclk_coeff(int mclk, int srate)
0864 {
0865     int i;
0866 
0867     for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
0868         if (cs42l73_mclk_coeffs[i].mclk == mclk &&
0869             cs42l73_mclk_coeffs[i].srate == srate)
0870             return i;
0871     }
0872     return -EINVAL;
0873 
0874 }
0875 
0876 static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
0877 {
0878     struct snd_soc_component *component = dai->component;
0879     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0880 
0881     int mclkx_coeff;
0882     u32 mclk = 0;
0883     u8 dmmcc = 0;
0884 
0885     /* MCLKX -> MCLK */
0886     mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
0887     if (mclkx_coeff < 0)
0888         return mclkx_coeff;
0889 
0890     mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
0891         cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
0892 
0893     dev_dbg(component->dev, "MCLK%u %u  <-> internal MCLK %u\n",
0894          priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
0895          mclk);
0896 
0897     dmmcc = (priv->mclksel << 4) |
0898         (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
0899 
0900     snd_soc_component_write(component, CS42L73_DMMCC, dmmcc);
0901 
0902     priv->sysclk = mclkx_coeff;
0903     priv->mclk = mclk;
0904 
0905     return 0;
0906 }
0907 
0908 static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
0909                   int clk_id, unsigned int freq, int dir)
0910 {
0911     struct snd_soc_component *component = dai->component;
0912     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0913 
0914     switch (clk_id) {
0915     case CS42L73_CLKID_MCLK1:
0916         break;
0917     case CS42L73_CLKID_MCLK2:
0918         break;
0919     default:
0920         return -EINVAL;
0921     }
0922 
0923     if ((cs42l73_set_mclk(dai, freq)) < 0) {
0924         dev_err(component->dev, "Unable to set MCLK for dai %s\n",
0925             dai->name);
0926         return -EINVAL;
0927     }
0928 
0929     priv->mclksel = clk_id;
0930 
0931     return 0;
0932 }
0933 
0934 static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0935 {
0936     struct snd_soc_component *component = codec_dai->component;
0937     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
0938     u8 id = codec_dai->id;
0939     unsigned int inv, format;
0940     u8 spc, mmcc;
0941 
0942     spc = snd_soc_component_read(component, CS42L73_SPC(id));
0943     mmcc = snd_soc_component_read(component, CS42L73_MMCC(id));
0944 
0945     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0946     case SND_SOC_DAIFMT_CBM_CFM:
0947         mmcc |= CS42L73_MS_MASTER;
0948         break;
0949 
0950     case SND_SOC_DAIFMT_CBS_CFS:
0951         mmcc &= ~CS42L73_MS_MASTER;
0952         break;
0953 
0954     default:
0955         return -EINVAL;
0956     }
0957 
0958     format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
0959     inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
0960 
0961     switch (format) {
0962     case SND_SOC_DAIFMT_I2S:
0963         spc &= ~CS42L73_SPDIF_PCM;
0964         break;
0965     case SND_SOC_DAIFMT_DSP_A:
0966     case SND_SOC_DAIFMT_DSP_B:
0967         if (mmcc & CS42L73_MS_MASTER) {
0968             dev_err(component->dev,
0969                 "PCM format in slave mode only\n");
0970             return -EINVAL;
0971         }
0972         if (id == CS42L73_ASP) {
0973             dev_err(component->dev,
0974                 "PCM format is not supported on ASP port\n");
0975             return -EINVAL;
0976         }
0977         spc |= CS42L73_SPDIF_PCM;
0978         break;
0979     default:
0980         return -EINVAL;
0981     }
0982 
0983     if (spc & CS42L73_SPDIF_PCM) {
0984         /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
0985         spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
0986         switch (format) {
0987         case SND_SOC_DAIFMT_DSP_B:
0988             if (inv == SND_SOC_DAIFMT_IB_IF)
0989                 spc |= CS42L73_PCM_MODE0;
0990             if (inv == SND_SOC_DAIFMT_IB_NF)
0991                 spc |= CS42L73_PCM_MODE1;
0992         break;
0993         case SND_SOC_DAIFMT_DSP_A:
0994             if (inv == SND_SOC_DAIFMT_IB_IF)
0995                 spc |= CS42L73_PCM_MODE1;
0996             break;
0997         default:
0998             return -EINVAL;
0999         }
1000     }
1001 
1002     priv->config[id].spc = spc;
1003     priv->config[id].mmcc = mmcc;
1004 
1005     return 0;
1006 }
1007 
1008 static const unsigned int cs42l73_asrc_rates[] = {
1009     8000, 11025, 12000, 16000, 22050,
1010     24000, 32000, 44100, 48000
1011 };
1012 
1013 static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
1014 {
1015     int i;
1016     for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
1017         if (cs42l73_asrc_rates[i] == rate)
1018             return i + 1;
1019     }
1020     return 0;       /* 0 = Don't know */
1021 }
1022 
1023 static void cs42l73_update_asrc(struct snd_soc_component *component, int id, int srate)
1024 {
1025     u8 spfs = 0;
1026 
1027     if (srate > 0)
1028         spfs = cs42l73_get_xspfs_coeff(srate);
1029 
1030     switch (id) {
1031     case CS42L73_XSP:
1032         snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs);
1033     break;
1034     case CS42L73_ASP:
1035         snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2);
1036     break;
1037     case CS42L73_VSP:
1038         snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4);
1039     break;
1040     default:
1041     break;
1042     }
1043 }
1044 
1045 static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1046                  struct snd_pcm_hw_params *params,
1047                  struct snd_soc_dai *dai)
1048 {
1049     struct snd_soc_component *component = dai->component;
1050     struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
1051     int id = dai->id;
1052     int mclk_coeff;
1053     int srate = params_rate(params);
1054 
1055     if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
1056         /* CS42L73 Master */
1057         /* MCLK -> srate */
1058         mclk_coeff =
1059             cs42l73_get_mclk_coeff(priv->mclk, srate);
1060 
1061         if (mclk_coeff < 0)
1062             return -EINVAL;
1063 
1064         dev_dbg(component->dev,
1065              "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
1066              id, priv->mclk, srate,
1067              cs42l73_mclk_coeffs[mclk_coeff].mmcc);
1068 
1069         priv->config[id].mmcc &= 0xC0;
1070         priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
1071         priv->config[id].spc &= 0xFC;
1072         /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
1073         if (priv->mclk >= 6400000)
1074             priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1075         else
1076             priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
1077     } else {
1078         /* CS42L73 Slave */
1079         priv->config[id].spc &= 0xFC;
1080         priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1081     }
1082     /* Update ASRCs */
1083     priv->config[id].srate = srate;
1084 
1085     snd_soc_component_write(component, CS42L73_SPC(id), priv->config[id].spc);
1086     snd_soc_component_write(component, CS42L73_MMCC(id), priv->config[id].mmcc);
1087 
1088     cs42l73_update_asrc(component, id, srate);
1089 
1090     return 0;
1091 }
1092 
1093 static int cs42l73_set_bias_level(struct snd_soc_component *component,
1094                   enum snd_soc_bias_level level)
1095 {
1096     struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
1097 
1098     switch (level) {
1099     case SND_SOC_BIAS_ON:
1100         snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
1101         snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0);
1102         break;
1103 
1104     case SND_SOC_BIAS_PREPARE:
1105         break;
1106 
1107     case SND_SOC_BIAS_STANDBY:
1108         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1109             regcache_cache_only(cs42l73->regmap, false);
1110             regcache_sync(cs42l73->regmap);
1111         }
1112         snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1113         break;
1114 
1115     case SND_SOC_BIAS_OFF:
1116         snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1117         if (cs42l73->shutdwn_delay > 0) {
1118             mdelay(cs42l73->shutdwn_delay);
1119             cs42l73->shutdwn_delay = 0;
1120         } else {
1121             mdelay(15); /* Min amount of time requred to power
1122                      * down.
1123                      */
1124         }
1125         snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
1126         break;
1127     }
1128     return 0;
1129 }
1130 
1131 static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
1132 {
1133     struct snd_soc_component *component = dai->component;
1134     int id = dai->id;
1135 
1136     return snd_soc_component_update_bits(component, CS42L73_SPC(id), CS42L73_SP_3ST,
1137                    tristate << 7);
1138 }
1139 
1140 static const struct snd_pcm_hw_constraint_list constraints_12_24 = {
1141     .count  = ARRAY_SIZE(cs42l73_asrc_rates),
1142     .list   = cs42l73_asrc_rates,
1143 };
1144 
1145 static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
1146                    struct snd_soc_dai *dai)
1147 {
1148     snd_pcm_hw_constraint_list(substream->runtime, 0,
1149                     SNDRV_PCM_HW_PARAM_RATE,
1150                     &constraints_12_24);
1151     return 0;
1152 }
1153 
1154 
1155 #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1156     SNDRV_PCM_FMTBIT_S24_LE)
1157 
1158 static const struct snd_soc_dai_ops cs42l73_ops = {
1159     .startup = cs42l73_pcm_startup,
1160     .hw_params = cs42l73_pcm_hw_params,
1161     .set_fmt = cs42l73_set_dai_fmt,
1162     .set_sysclk = cs42l73_set_sysclk,
1163     .set_tristate = cs42l73_set_tristate,
1164 };
1165 
1166 static struct snd_soc_dai_driver cs42l73_dai[] = {
1167     {
1168         .name = "cs42l73-xsp",
1169         .id = CS42L73_XSP,
1170         .playback = {
1171             .stream_name = "XSP Playback",
1172             .channels_min = 1,
1173             .channels_max = 2,
1174             .rates = SNDRV_PCM_RATE_KNOT,
1175             .formats = CS42L73_FORMATS,
1176         },
1177         .capture = {
1178             .stream_name = "XSP Capture",
1179             .channels_min = 1,
1180             .channels_max = 2,
1181             .rates = SNDRV_PCM_RATE_KNOT,
1182             .formats = CS42L73_FORMATS,
1183         },
1184         .ops = &cs42l73_ops,
1185         .symmetric_rate = 1,
1186      },
1187     {
1188         .name = "cs42l73-asp",
1189         .id = CS42L73_ASP,
1190         .playback = {
1191             .stream_name = "ASP Playback",
1192             .channels_min = 2,
1193             .channels_max = 2,
1194             .rates = SNDRV_PCM_RATE_KNOT,
1195             .formats = CS42L73_FORMATS,
1196         },
1197         .capture = {
1198             .stream_name = "ASP Capture",
1199             .channels_min = 2,
1200             .channels_max = 2,
1201             .rates = SNDRV_PCM_RATE_KNOT,
1202             .formats = CS42L73_FORMATS,
1203         },
1204         .ops = &cs42l73_ops,
1205         .symmetric_rate = 1,
1206      },
1207     {
1208         .name = "cs42l73-vsp",
1209         .id = CS42L73_VSP,
1210         .playback = {
1211             .stream_name = "VSP Playback",
1212             .channels_min = 1,
1213             .channels_max = 2,
1214             .rates = SNDRV_PCM_RATE_KNOT,
1215             .formats = CS42L73_FORMATS,
1216         },
1217         .capture = {
1218             .stream_name = "VSP Capture",
1219             .channels_min = 1,
1220             .channels_max = 2,
1221             .rates = SNDRV_PCM_RATE_KNOT,
1222             .formats = CS42L73_FORMATS,
1223         },
1224         .ops = &cs42l73_ops,
1225         .symmetric_rate = 1,
1226      }
1227 };
1228 
1229 static int cs42l73_probe(struct snd_soc_component *component)
1230 {
1231     struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
1232 
1233     /* Set Charge Pump Frequency */
1234     if (cs42l73->pdata.chgfreq)
1235         snd_soc_component_update_bits(component, CS42L73_CPFCHC,
1236                     CS42L73_CHARGEPUMP_MASK,
1237                     cs42l73->pdata.chgfreq << 4);
1238 
1239     /* MCLK1 as master clk */
1240     cs42l73->mclksel = CS42L73_CLKID_MCLK1;
1241     cs42l73->mclk = 0;
1242 
1243     return 0;
1244 }
1245 
1246 static const struct snd_soc_component_driver soc_component_dev_cs42l73 = {
1247     .probe          = cs42l73_probe,
1248     .set_bias_level     = cs42l73_set_bias_level,
1249     .controls       = cs42l73_snd_controls,
1250     .num_controls       = ARRAY_SIZE(cs42l73_snd_controls),
1251     .dapm_widgets       = cs42l73_dapm_widgets,
1252     .num_dapm_widgets   = ARRAY_SIZE(cs42l73_dapm_widgets),
1253     .dapm_routes        = cs42l73_audio_map,
1254     .num_dapm_routes    = ARRAY_SIZE(cs42l73_audio_map),
1255     .suspend_bias_off   = 1,
1256     .idle_bias_on       = 1,
1257     .use_pmdown_time    = 1,
1258     .endianness     = 1,
1259 };
1260 
1261 static const struct regmap_config cs42l73_regmap = {
1262     .reg_bits = 8,
1263     .val_bits = 8,
1264 
1265     .max_register = CS42L73_MAX_REGISTER,
1266     .reg_defaults = cs42l73_reg_defaults,
1267     .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
1268     .volatile_reg = cs42l73_volatile_register,
1269     .readable_reg = cs42l73_readable_register,
1270     .cache_type = REGCACHE_RBTREE,
1271 
1272     .use_single_read = true,
1273     .use_single_write = true,
1274 };
1275 
1276 static int cs42l73_i2c_probe(struct i2c_client *i2c_client)
1277 {
1278     struct cs42l73_private *cs42l73;
1279     struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1280     int ret, devid;
1281     unsigned int reg;
1282     u32 val32;
1283 
1284     cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL);
1285     if (!cs42l73)
1286         return -ENOMEM;
1287 
1288     cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
1289     if (IS_ERR(cs42l73->regmap)) {
1290         ret = PTR_ERR(cs42l73->regmap);
1291         dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1292         return ret;
1293     }
1294 
1295     if (pdata) {
1296         cs42l73->pdata = *pdata;
1297     } else {
1298         pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1299                      GFP_KERNEL);
1300         if (!pdata)
1301             return -ENOMEM;
1302 
1303         if (i2c_client->dev.of_node) {
1304             if (of_property_read_u32(i2c_client->dev.of_node,
1305                 "chgfreq", &val32) >= 0)
1306                 pdata->chgfreq = val32;
1307         }
1308         pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
1309                         "reset-gpio", 0);
1310         cs42l73->pdata = *pdata;
1311     }
1312 
1313     i2c_set_clientdata(i2c_client, cs42l73);
1314 
1315     if (cs42l73->pdata.reset_gpio) {
1316         ret = devm_gpio_request_one(&i2c_client->dev,
1317                         cs42l73->pdata.reset_gpio,
1318                         GPIOF_OUT_INIT_HIGH,
1319                         "CS42L73 /RST");
1320         if (ret < 0) {
1321             dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1322                 cs42l73->pdata.reset_gpio, ret);
1323             return ret;
1324         }
1325         gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
1326         gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
1327     }
1328 
1329     /* initialize codec */
1330     devid = cirrus_read_device_id(cs42l73->regmap, CS42L73_DEVID_AB);
1331     if (devid < 0) {
1332         ret = devid;
1333         dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1334         goto err_reset;
1335     }
1336 
1337     if (devid != CS42L73_DEVID) {
1338         ret = -ENODEV;
1339         dev_err(&i2c_client->dev,
1340             "CS42L73 Device ID (%X). Expected %X\n",
1341             devid, CS42L73_DEVID);
1342         goto err_reset;
1343     }
1344 
1345     ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
1346     if (ret < 0) {
1347         dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1348         goto err_reset;
1349     }
1350 
1351     dev_info(&i2c_client->dev,
1352          "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
1353 
1354     ret = devm_snd_soc_register_component(&i2c_client->dev,
1355             &soc_component_dev_cs42l73, cs42l73_dai,
1356             ARRAY_SIZE(cs42l73_dai));
1357     if (ret < 0)
1358         goto err_reset;
1359 
1360     return 0;
1361 
1362 err_reset:
1363     gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
1364 
1365     return ret;
1366 }
1367 
1368 static const struct of_device_id cs42l73_of_match[] = {
1369     { .compatible = "cirrus,cs42l73", },
1370     {},
1371 };
1372 MODULE_DEVICE_TABLE(of, cs42l73_of_match);
1373 
1374 static const struct i2c_device_id cs42l73_id[] = {
1375     {"cs42l73", 0},
1376     {}
1377 };
1378 
1379 MODULE_DEVICE_TABLE(i2c, cs42l73_id);
1380 
1381 static struct i2c_driver cs42l73_i2c_driver = {
1382     .driver = {
1383            .name = "cs42l73",
1384            .of_match_table = cs42l73_of_match,
1385            },
1386     .id_table = cs42l73_id,
1387     .probe_new = cs42l73_i2c_probe,
1388 
1389 };
1390 
1391 module_i2c_driver(cs42l73_i2c_driver);
1392 
1393 MODULE_DESCRIPTION("ASoC CS42L73 driver");
1394 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1395 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1396 MODULE_LICENSE("GPL");
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