soc/codecs/cs42l56.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * cs42l52.h -- CS42L56 ALSA SoC audio driver
0004  *
0005  * Copyright 2014 CirrusLogic, Inc.
0006  *
0007  * Author: Brian Austin <brian.austin@cirrus.com>
0008  */
0009
0010 #ifndef __CS42L56_H__
0011 #define __CS42L56_H__
0012
0013 #define CS42L56_CHIP_ID_1       0x01
0014 #define CS42L56_CHIP_ID_2       0x02
0015 #define CS42L56_PWRCTL_1        0x03
0016 #define CS42L56_PWRCTL_2        0x04
0017 #define CS42L56_CLKCTL_1        0x05
0018 #define CS42L56_CLKCTL_2        0x06
0019 #define CS42L56_SERIAL_FMT      0x07
0020 #define CS42L56_CLASSH_CTL      0x08
0021 #define CS42L56_MISC_CTL        0x09
0022 #define CS42L56_INT_STATUS      0x0a
0023 #define CS42L56_PLAYBACK_CTL        0x0b
0024 #define CS42L56_DSP_MUTE_CTL        0x0c
0025 #define CS42L56_ADCA_MIX_VOLUME     0x0d
0026 #define CS42L56_ADCB_MIX_VOLUME     0x0e
0027 #define CS42L56_PCMA_MIX_VOLUME     0x0f
0028 #define CS42L56_PCMB_MIX_VOLUME     0x10
0029 #define CS42L56_ANAINPUT_ADV_VOLUME 0x11
0030 #define CS42L56_DIGINPUT_ADV_VOLUME 0x12
0031 #define CS42L56_MASTER_A_VOLUME     0x13
0032 #define CS42L56_MASTER_B_VOLUME     0x14
0033 #define CS42L56_BEEP_FREQ_ONTIME    0x15
0034 #define CS42L56_BEEP_FREQ_OFFTIME   0x16
0035 #define CS42L56_BEEP_TONE_CFG       0x17
0036 #define CS42L56_TONE_CTL        0x18
0037 #define CS42L56_CHAN_MIX_SWAP       0x19
0038 #define CS42L56_AIN_REFCFG_ADC_MUX  0x1a
0039 #define CS42L56_HPF_CTL         0x1b
0040 #define CS42L56_MISC_ADC_CTL        0x1c
0041 #define CS42L56_GAIN_BIAS_CTL       0x1d
0042 #define CS42L56_PGAA_MUX_VOLUME     0x1e
0043 #define CS42L56_PGAB_MUX_VOLUME     0x1f
0044 #define CS42L56_ADCA_ATTENUATOR     0x20
0045 #define CS42L56_ADCB_ATTENUATOR     0x21
0046 #define CS42L56_ALC_EN_ATTACK_RATE  0x22
0047 #define CS42L56_ALC_RELEASE_RATE    0x23
0048 #define CS42L56_ALC_THRESHOLD       0x24
0049 #define CS42L56_NOISE_GATE_CTL      0x25
0050 #define CS42L56_ALC_LIM_SFT_ZC      0x26
0051 #define CS42L56_AMUTE_HPLO_MUX      0x27
0052 #define CS42L56_HPA_VOLUME      0x28
0053 #define CS42L56_HPB_VOLUME      0x29
0054 #define CS42L56_LOA_VOLUME      0x2a
0055 #define CS42L56_LOB_VOLUME      0x2b
0056 #define CS42L56_LIM_THRESHOLD_CTL   0x2c
0057 #define CS42L56_LIM_CTL_RELEASE_RATE    0x2d
0058 #define CS42L56_LIM_ATTACK_RATE     0x2e
0059
0060 /* Device ID and Rev ID Masks */
0061 #define CS42L56_DEVID           0x56
0062 #define CS42L56_CHIP_ID_MASK        0xff
0063 #define CS42L56_AREV_MASK       0x1c
0064 #define CS42L56_MTLREV_MASK     0x03
0065
0066 /* Power bit masks */
0067 #define CS42L56_PDN_ALL_MASK        0x01
0068 #define CS42L56_PDN_ADCA_MASK       0x02
0069 #define CS42L56_PDN_ADCB_MASK       0x04
0070 #define CS42L56_PDN_CHRG_MASK       0x08
0071 #define CS42L56_PDN_BIAS_MASK       0x10
0072 #define CS42L56_PDN_VBUF_MASK       0x20
0073 #define CS42L56_PDN_LOA_MASK        0x03
0074 #define CS42L56_PDN_LOB_MASK        0x0c
0075 #define CS42L56_PDN_HPA_MASK        0x30
0076 #define CS42L56_PDN_HPB_MASK        0xc0
0077
0078 /* serial port and clk masks */
0079 #define CS42L56_MASTER_MODE     0x40
0080 #define CS42L56_SLAVE_MODE      0
0081 #define CS42L56_MS_MODE_MASK        0x40
0082 #define CS42L56_SCLK_INV        0x20
0083 #define CS42L56_SCLK_INV_MASK       0x20
0084 #define CS42L56_SCLK_MCLK_MASK      0x18
0085 #define CS42L56_MCLK_PREDIV     0x04
0086 #define CS42L56_MCLK_PREDIV_MASK    0x04
0087 #define CS42L56_MCLK_DIV2       0x02
0088 #define CS42L56_MCLK_DIV2_MASK      0x02
0089 #define CS42L56_MCLK_DIS_MASK       0x01
0090 #define CS42L56_CLK_AUTO_MASK       0x20
0091 #define CS42L56_CLK_RATIO_MASK      0x1f
0092 #define CS42L56_DIG_FMT_I2S     0
0093 #define CS42L56_DIG_FMT_LEFT_J      0x08
0094 #define CS42L56_DIG_FMT_MASK        0x08
0095
0096 /* Class H and misc ctl masks */
0097 #define CS42L56_ADAPT_PWR_MASK      0xc0
0098 #define CS42L56_CHRG_FREQ_MASK      0x0f
0099 #define CS42L56_DIG_MUX_MASK        0x80
0100 #define CS42L56_ANLGSFT_MASK        0x10
0101 #define CS42L56_ANLGZC_MASK     0x08
0102 #define CS42L56_DIGSFT_MASK     0x04
0103 #define CS42L56_FREEZE_MASK     0x01
0104 #define CS42L56_MIC_BIAS_MASK       0x03
0105 #define CS42L56_HPFA_FREQ_MASK      0x03
0106 #define CS42L56_HPFB_FREQ_MASK      0xc0
0107 #define CS42L56_AIN1A_REF_MASK      0x10
0108 #define CS42L56_AIN2A_REF_MASK      0x40
0109 #define CS42L56_AIN1B_REF_MASK      0x20
0110 #define CS42L56_AIN2B_REF_MASK      0x80
0111
0112 /* Playback Capture ctl masks */
0113 #define CS42L56_PDN_DSP_MASK        0x80
0114 #define CS42L56_DEEMPH_MASK     0x40
0115 #define CS42L56_PLYBCK_GANG_MASK    0x10
0116 #define CS42L56_PCM_INV_MASK        0x0c
0117 #define CS42L56_MUTE_ALL        0xff
0118 #define CS42L56_UNMUTE          0
0119 #define CS42L56_ADCAMIX_MUTE_MASK   0x40
0120 #define CS42L56_ADCBMIX_MUTE_MASK   0x80
0121 #define CS42L56_PCMAMIX_MUTE_MASK   0x10
0122 #define CS42L56_PCMBMIX_MUTE_MASK   0x20
0123 #define CS42L56_MSTB_MUTE_MASK      0x02
0124 #define CS42L56_MSTA_MUTE_MASK      0x01
0125 #define CS42L56_ADCA_MUTE_MASK      0x01
0126 #define CS42L56_ADCB_MUTE_MASK      0x02
0127 #define CS42L56_HP_MUTE_MASK        0x80
0128 #define CS42L56_LO_MUTE_MASK        0x80
0129
0130 /* Beep masks */
0131 #define CS42L56_BEEP_FREQ_MASK      0xf0
0132 #define CS42L56_BEEP_ONTIME_MASK    0x0f
0133 #define CS42L56_BEEP_OFFTIME_MASK   0xe0
0134 #define CS42L56_BEEP_CFG_MASK       0xc0
0135 #define CS42L56_BEEP_TREBCF_MASK    0x18
0136 #define CS42L56_BEEP_BASSCF_MASK    0x06
0137 #define CS42L56_BEEP_TCEN_MASK      0x01
0138 #define CS42L56_BEEP_RATE_SHIFT     4
0139 #define CS42L56_BEEP_EN_MASK        0x3f
0140
0141
0142 /* Supported MCLKS */
0143 #define CS42L56_MCLK_5P6448MHZ      5644800
0144 #define CS42L56_MCLK_6MHZ       6000000
0145 #define CS42L56_MCLK_6P144MHZ       6144000
0146 #define CS42L56_MCLK_11P2896MHZ     11289600
0147 #define CS42L56_MCLK_12MHZ      12000000
0148 #define CS42L56_MCLK_12P288MHZ      12288000
0149 #define CS42L56_MCLK_22P5792MHZ     22579200
0150 #define CS42L56_MCLK_24MHZ      24000000
0151 #define CS42L56_MCLK_24P576MHZ      24576000
0152
0153 /* Clock ratios */
0154 #define CS42L56_MCLK_LRCLK_128      0x08
0155 #define CS42L56_MCLK_LRCLK_125      0x09
0156 #define CS42L56_MCLK_LRCLK_136      0x0b
0157 #define CS42L56_MCLK_LRCLK_192      0x0c
0158 #define CS42L56_MCLK_LRCLK_187P5    0x0d
0159 #define CS42L56_MCLK_LRCLK_256      0x10
0160 #define CS42L56_MCLK_LRCLK_250      0x11
0161 #define CS42L56_MCLK_LRCLK_272      0x13
0162 #define CS42L56_MCLK_LRCLK_384      0x14
0163 #define CS42L56_MCLK_LRCLK_375      0x15
0164 #define CS42L56_MCLK_LRCLK_512      0x18
0165 #define CS42L56_MCLK_LRCLK_500      0x19
0166 #define CS42L56_MCLK_LRCLK_544      0x1b
0167 #define CS42L56_MCLK_LRCLK_750      0x1c
0168 #define CS42L56_MCLK_LRCLK_768      0x1d
0169
0170
0171 #define CS42L56_MAX_REGISTER        0x34
0172
0173 #endif