soc/codecs/cs42l51.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * cs42l51.h
0004  *
0005  * ASoC Driver for Cirrus Logic CS42L51 codecs
0006  *
0007  * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
0008  */
0009 #ifndef _CS42L51_H
0010 #define _CS42L51_H
0011
0012 struct device;
0013
0014 extern const struct regmap_config cs42l51_regmap;
0015 int cs42l51_probe(struct device *dev, struct regmap *regmap);
0016 void cs42l51_remove(struct device *dev);
0017 int __maybe_unused cs42l51_suspend(struct device *dev);
0018 int __maybe_unused cs42l51_resume(struct device *dev);
0019 extern const struct of_device_id cs42l51_of_match[];
0020
0021 #define CS42L51_CHIP_ID         0x1B
0022 #define CS42L51_CHIP_REV_A      0x00
0023 #define CS42L51_CHIP_REV_B      0x01
0024 #define CS42L51_CHIP_REV_MASK       0x07
0025
0026 #define CS42L51_CHIP_REV_ID     0x01
0027 #define CS42L51_MK_CHIP_REV(a, b)   ((a)<<3|(b))
0028
0029 #define CS42L51_POWER_CTL1      0x02
0030 #define CS42L51_POWER_CTL1_PDN_DACB (1<<6)
0031 #define CS42L51_POWER_CTL1_PDN_DACA (1<<5)
0032 #define CS42L51_POWER_CTL1_PDN_PGAB (1<<4)
0033 #define CS42L51_POWER_CTL1_PDN_PGAA (1<<3)
0034 #define CS42L51_POWER_CTL1_PDN_ADCB (1<<2)
0035 #define CS42L51_POWER_CTL1_PDN_ADCA (1<<1)
0036 #define CS42L51_POWER_CTL1_PDN      (1<<0)
0037
0038 #define CS42L51_MIC_POWER_CTL       0x03
0039 #define CS42L51_MIC_POWER_CTL_AUTO  (1<<7)
0040 #define CS42L51_MIC_POWER_CTL_SPEED(x)  (((x)&3)<<5)
0041 #define CS42L51_QSM_MODE        3
0042 #define CS42L51_HSM_MODE        2
0043 #define CS42L51_SSM_MODE        1
0044 #define CS42L51_DSM_MODE        0
0045 #define CS42L51_MIC_POWER_CTL_3ST_SP    (1<<4)
0046 #define CS42L51_MIC_POWER_CTL_PDN_MICB  (1<<3)
0047 #define CS42L51_MIC_POWER_CTL_PDN_MICA  (1<<2)
0048 #define CS42L51_MIC_POWER_CTL_PDN_BIAS  (1<<1)
0049 #define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0)
0050
0051 #define CS42L51_INTF_CTL        0x04
0052 #define CS42L51_INTF_CTL_LOOPBACK   (1<<7)
0053 #define CS42L51_INTF_CTL_MASTER     (1<<6)
0054 #define CS42L51_INTF_CTL_DAC_FORMAT(x)  (((x)&7)<<3)
0055 #define CS42L51_DAC_DIF_LJ24        0x00
0056 #define CS42L51_DAC_DIF_I2S     0x01
0057 #define CS42L51_DAC_DIF_RJ24        0x02
0058 #define CS42L51_DAC_DIF_RJ20        0x03
0059 #define CS42L51_DAC_DIF_RJ18        0x04
0060 #define CS42L51_DAC_DIF_RJ16        0x05
0061 #define CS42L51_INTF_CTL_ADC_I2S    (1<<2)
0062 #define CS42L51_INTF_CTL_DIGMIX     (1<<1)
0063 #define CS42L51_INTF_CTL_MICMIX     (1<<0)
0064
0065 #define CS42L51_MIC_CTL         0x05
0066 #define CS42L51_MIC_CTL_ADC_SNGVOL  (1<<7)
0067 #define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6)
0068 #define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5)
0069 #define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4)
0070 #define CS42L51_MIC_CTL_MICBIAS_LVL(x)  (((x)&3)<<2)
0071 #define CS42L51_MIC_CTL_MICB_BOOST  (1<<1)
0072 #define CS42L51_MIC_CTL_MICA_BOOST  (1<<0)
0073
0074 #define CS42L51_ADC_CTL         0x06
0075 #define CS42L51_ADC_CTL_ADCB_HPFEN  (1<<7)
0076 #define CS42L51_ADC_CTL_ADCB_HPFRZ  (1<<6)
0077 #define CS42L51_ADC_CTL_ADCA_HPFEN  (1<<5)
0078 #define CS42L51_ADC_CTL_ADCA_HPFRZ  (1<<4)
0079 #define CS42L51_ADC_CTL_SOFTB       (1<<3)
0080 #define CS42L51_ADC_CTL_ZCROSSB     (1<<2)
0081 #define CS42L51_ADC_CTL_SOFTA       (1<<1)
0082 #define CS42L51_ADC_CTL_ZCROSSA     (1<<0)
0083
0084 #define CS42L51_ADC_INPUT       0x07
0085 #define CS42L51_ADC_INPUT_AINB_MUX(x)   (((x)&3)<<6)
0086 #define CS42L51_ADC_INPUT_AINA_MUX(x)   (((x)&3)<<4)
0087 #define CS42L51_ADC_INPUT_INV_ADCB  (1<<3)
0088 #define CS42L51_ADC_INPUT_INV_ADCA  (1<<2)
0089 #define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1)
0090 #define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0)
0091
0092 #define CS42L51_DAC_OUT_CTL     0x08
0093 #define CS42L51_DAC_OUT_CTL_HP_GAIN(x)  (((x)&7)<<5)
0094 #define CS42L51_DAC_OUT_CTL_DAC_SNGVOL  (1<<4)
0095 #define CS42L51_DAC_OUT_CTL_INV_PCMB    (1<<3)
0096 #define CS42L51_DAC_OUT_CTL_INV_PCMA    (1<<2)
0097 #define CS42L51_DAC_OUT_CTL_DACB_MUTE   (1<<1)
0098 #define CS42L51_DAC_OUT_CTL_DACA_MUTE   (1<<0)
0099
0100 #define CS42L51_DAC_CTL         0x09
0101 #define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6)
0102 #define CS42L51_DAC_CTL_FREEZE      (1<<5)
0103 #define CS42L51_DAC_CTL_DEEMPH      (1<<3)
0104 #define CS42L51_DAC_CTL_AMUTE       (1<<2)
0105 #define CS42L51_DAC_CTL_DACSZ(x)    (((x)&3)<<0)
0106
0107 #define CS42L51_ALC_PGA_CTL     0x0A
0108 #define CS42L51_ALC_PGB_CTL     0x0B
0109 #define CS42L51_ALC_PGX_ALCX_SRDIS  (1<<7)
0110 #define CS42L51_ALC_PGX_ALCX_ZCDIS  (1<<6)
0111 #define CS42L51_ALC_PGX_PGX_VOL(x)  (((x)&0x1f)<<0)
0112
0113 #define CS42L51_ADCA_ATT        0x0C
0114 #define CS42L51_ADCB_ATT        0x0D
0115
0116 #define CS42L51_ADCA_VOL        0x0E
0117 #define CS42L51_ADCB_VOL        0x0F
0118 #define CS42L51_PCMA_VOL        0x10
0119 #define CS42L51_PCMB_VOL        0x11
0120 #define CS42L51_MIX_MUTE_ADCMIX     (1<<7)
0121 #define CS42L51_MIX_VOLUME(x)       (((x)&0x7f)<<0)
0122
0123 #define CS42L51_BEEP_FREQ       0x12
0124 #define CS42L51_BEEP_VOL        0x13
0125 #define CS42L51_BEEP_CONF       0x14
0126
0127 #define CS42L51_TONE_CTL        0x15
0128 #define CS42L51_TONE_CTL_TREB(x)    (((x)&0xf)<<4)
0129 #define CS42L51_TONE_CTL_BASS(x)    (((x)&0xf)<<0)
0130
0131 #define CS42L51_AOUTA_VOL       0x16
0132 #define CS42L51_AOUTB_VOL       0x17
0133 #define CS42L51_PCM_MIXER       0x18
0134 #define CS42L51_LIMIT_THRES_DIS     0x19
0135 #define CS42L51_LIMIT_REL       0x1A
0136 #define CS42L51_LIMIT_ATT       0x1B
0137 #define CS42L51_ALC_EN          0x1C
0138 #define CS42L51_ALC_REL         0x1D
0139 #define CS42L51_ALC_THRES       0x1E
0140 #define CS42L51_NOISE_CONF      0x1F
0141
0142 #define CS42L51_STATUS          0x20
0143 #define CS42L51_STATUS_SP_CLKERR    (1<<6)
0144 #define CS42L51_STATUS_SPEA_OVFL    (1<<5)
0145 #define CS42L51_STATUS_SPEB_OVFL    (1<<4)
0146 #define CS42L51_STATUS_PCMA_OVFL    (1<<3)
0147 #define CS42L51_STATUS_PCMB_OVFL    (1<<2)
0148 #define CS42L51_STATUS_ADCA_OVFL    (1<<1)
0149 #define CS42L51_STATUS_ADCB_OVFL    (1<<0)
0150
0151 #define CS42L51_CHARGE_FREQ     0x21
0152
0153 #define CS42L51_FIRSTREG    0x01
0154 /*
0155  * Hack: with register 0x21, it makes 33 registers. Looks like someone in the
0156  * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
0157  * 32 regs
0158  */
0159 #define CS42L51_LASTREG     0x20
0160 #define CS42L51_NUMREGS     (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
0161
0162 #endif