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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cs4265.c -- CS4265 ALSA SoC audio driver
0004  *
0005  * Copyright 2014 Cirrus Logic, Inc.
0006  *
0007  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/kernel.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/i2c.h>
0017 #include <linux/input.h>
0018 #include <linux/regmap.h>
0019 #include <linux/slab.h>
0020 #include <linux/platform_device.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/soc-dapm.h>
0026 #include <sound/initval.h>
0027 #include <sound/tlv.h>
0028 #include "cs4265.h"
0029 
0030 struct cs4265_private {
0031     struct regmap *regmap;
0032     struct gpio_desc *reset_gpio;
0033     u8 format;
0034     u32 sysclk;
0035 };
0036 
0037 static const struct reg_default cs4265_reg_defaults[] = {
0038     { CS4265_PWRCTL, 0x0F },
0039     { CS4265_DAC_CTL, 0x08 },
0040     { CS4265_ADC_CTL, 0x00 },
0041     { CS4265_MCLK_FREQ, 0x00 },
0042     { CS4265_SIG_SEL, 0x40 },
0043     { CS4265_CHB_PGA_CTL, 0x00 },
0044     { CS4265_CHA_PGA_CTL, 0x00 },
0045     { CS4265_ADC_CTL2, 0x19 },
0046     { CS4265_DAC_CHA_VOL, 0x00 },
0047     { CS4265_DAC_CHB_VOL, 0x00 },
0048     { CS4265_DAC_CTL2, 0xC0 },
0049     { CS4265_SPDIF_CTL1, 0x00 },
0050     { CS4265_SPDIF_CTL2, 0x00 },
0051     { CS4265_INT_MASK, 0x00 },
0052     { CS4265_STATUS_MODE_MSB, 0x00 },
0053     { CS4265_STATUS_MODE_LSB, 0x00 },
0054 };
0055 
0056 static bool cs4265_readable_register(struct device *dev, unsigned int reg)
0057 {
0058     switch (reg) {
0059     case CS4265_CHIP_ID ... CS4265_MAX_REGISTER:
0060         return true;
0061     default:
0062         return false;
0063     }
0064 }
0065 
0066 static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
0067 {
0068     switch (reg) {
0069     case CS4265_INT_STATUS:
0070         return true;
0071     default:
0072         return false;
0073     }
0074 }
0075 
0076 static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);
0077 
0078 static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);
0079 
0080 static const char * const digital_input_mux_text[] = {
0081     "SDIN1", "SDIN2"
0082 };
0083 
0084 static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
0085         digital_input_mux_text);
0086 
0087 static const struct snd_kcontrol_new digital_input_mux =
0088     SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);
0089 
0090 static const char * const mic_linein_text[] = {
0091     "MIC", "LINEIN"
0092 };
0093 
0094 static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
0095         mic_linein_text);
0096 
0097 static const char * const cam_mode_text[] = {
0098     "One Byte", "Two Byte"
0099 };
0100 
0101 static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
0102         cam_mode_text);
0103 
0104 static const char * const cam_mono_stereo_text[] = {
0105     "Stereo", "Mono"
0106 };
0107 
0108 static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
0109         cam_mono_stereo_text);
0110 
0111 static const char * const mono_select_text[] = {
0112     "Channel A", "Channel B"
0113 };
0114 
0115 static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
0116         mono_select_text);
0117 
0118 static const struct snd_kcontrol_new mic_linein_mux =
0119     SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);
0120 
0121 static const struct snd_kcontrol_new loopback_ctl =
0122     SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);
0123 
0124 static const struct snd_kcontrol_new spdif_switch =
0125     SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);
0126 
0127 static const struct snd_kcontrol_new dac_switch =
0128     SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);
0129 
0130 static const struct snd_kcontrol_new cs4265_snd_controls[] = {
0131 
0132     SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
0133                   CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
0134     SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
0135               CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
0136     SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
0137                 1, 0),
0138     SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
0139                 1, 0),
0140     SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
0141                 1, 0),
0142     SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
0143                 1, 0),
0144     SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
0145                 1, 0),
0146     SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
0147                 1, 1),
0148     SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
0149                 1, 0),
0150     SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
0151                 6, 1, 0),
0152     SOC_ENUM("C Data Access", cam_mode_enum),
0153     SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
0154                 3, 1, 0),
0155     SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
0156     SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
0157     SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
0158     SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
0159 };
0160 
0161 static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {
0162 
0163     SND_SOC_DAPM_INPUT("LINEINL"),
0164     SND_SOC_DAPM_INPUT("LINEINR"),
0165     SND_SOC_DAPM_INPUT("MICL"),
0166     SND_SOC_DAPM_INPUT("MICR"),
0167 
0168     SND_SOC_DAPM_AIF_OUT("DOUT", NULL,  0,
0169             SND_SOC_NOPM, 0, 0),
0170     SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL,  0,
0171             SND_SOC_NOPM, 0, 0),
0172 
0173     SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),
0174 
0175     SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
0176     SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
0177             1, NULL, 0),
0178 
0179     SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
0180              0, 0, &digital_input_mux),
0181 
0182     SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0183     SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0184     SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),
0185 
0186     SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
0187             &loopback_ctl),
0188     SND_SOC_DAPM_SWITCH("SPDIF", CS4265_SPDIF_CTL2, 5, 1,
0189             &spdif_switch),
0190     SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
0191             &dac_switch),
0192 
0193     SND_SOC_DAPM_AIF_IN("DIN1", NULL,  0,
0194             SND_SOC_NOPM, 0, 0),
0195     SND_SOC_DAPM_AIF_IN("DIN2", NULL,  0,
0196             SND_SOC_NOPM, 0, 0),
0197     SND_SOC_DAPM_AIF_IN("TXIN", NULL,  0,
0198             CS4265_SPDIF_CTL2, 5, 1),
0199 
0200     SND_SOC_DAPM_OUTPUT("LINEOUTL"),
0201     SND_SOC_DAPM_OUTPUT("LINEOUTR"),
0202 
0203 };
0204 
0205 static const struct snd_soc_dapm_route cs4265_audio_map[] = {
0206 
0207     {"DIN1", NULL, "DAI1 Playback"},
0208     {"DIN2", NULL, "DAI2 Playback"},
0209     {"SDIN1 Input Mixer", NULL, "DIN1"},
0210     {"SDIN2 Input Mixer", NULL, "DIN2"},
0211     {"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
0212     {"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
0213     {"DAC", "Switch", "Input Mux"},
0214     {"SPDIF", "Switch", "Input Mux"},
0215     {"LINEOUTL", NULL, "DAC"},
0216     {"LINEOUTR", NULL, "DAC"},
0217     {"SPDIFOUT", NULL, "SPDIF"},
0218 
0219     {"Pre-amp MIC", NULL, "MICL"},
0220     {"Pre-amp MIC", NULL, "MICR"},
0221     {"ADC Mux", "MIC", "Pre-amp MIC"},
0222     {"ADC Mux", "LINEIN", "LINEINL"},
0223     {"ADC Mux", "LINEIN", "LINEINR"},
0224     {"ADC", NULL, "ADC Mux"},
0225     {"DOUT", NULL, "ADC"},
0226     {"DAI1 Capture", NULL, "DOUT"},
0227     {"DAI2 Capture", NULL, "DOUT"},
0228 
0229     /* Loopback */
0230     {"Loopback", "Switch", "ADC"},
0231     {"DAC", NULL, "Loopback"},
0232 };
0233 
0234 struct cs4265_clk_para {
0235     u32 mclk;
0236     u32 rate;
0237     u8 fm_mode; /* values 1, 2, or 4 */
0238     u8 mclkdiv;
0239 };
0240 
0241 static const struct cs4265_clk_para clk_map_table[] = {
0242     /*32k*/
0243     {8192000, 32000, 0, 0},
0244     {12288000, 32000, 0, 1},
0245     {16384000, 32000, 0, 2},
0246     {24576000, 32000, 0, 3},
0247     {32768000, 32000, 0, 4},
0248 
0249     /*44.1k*/
0250     {11289600, 44100, 0, 0},
0251     {16934400, 44100, 0, 1},
0252     {22579200, 44100, 0, 2},
0253     {33868000, 44100, 0, 3},
0254     {45158400, 44100, 0, 4},
0255 
0256     /*48k*/
0257     {12288000, 48000, 0, 0},
0258     {18432000, 48000, 0, 1},
0259     {24576000, 48000, 0, 2},
0260     {36864000, 48000, 0, 3},
0261     {49152000, 48000, 0, 4},
0262 
0263     /*64k*/
0264     {8192000, 64000, 1, 0},
0265     {12288000, 64000, 1, 1},
0266     {16934400, 64000, 1, 2},
0267     {24576000, 64000, 1, 3},
0268     {32768000, 64000, 1, 4},
0269 
0270     /* 88.2k */
0271     {11289600, 88200, 1, 0},
0272     {16934400, 88200, 1, 1},
0273     {22579200, 88200, 1, 2},
0274     {33868000, 88200, 1, 3},
0275     {45158400, 88200, 1, 4},
0276 
0277     /* 96k */
0278     {12288000, 96000, 1, 0},
0279     {18432000, 96000, 1, 1},
0280     {24576000, 96000, 1, 2},
0281     {36864000, 96000, 1, 3},
0282     {49152000, 96000, 1, 4},
0283 
0284     /* 128k */
0285     {8192000, 128000, 2, 0},
0286     {12288000, 128000, 2, 1},
0287     {16934400, 128000, 2, 2},
0288     {24576000, 128000, 2, 3},
0289     {32768000, 128000, 2, 4},
0290 
0291     /* 176.4k */
0292     {11289600, 176400, 2, 0},
0293     {16934400, 176400, 2, 1},
0294     {22579200, 176400, 2, 2},
0295     {33868000, 176400, 2, 3},
0296     {49152000, 176400, 2, 4},
0297 
0298     /* 192k */
0299     {12288000, 192000, 2, 0},
0300     {18432000, 192000, 2, 1},
0301     {24576000, 192000, 2, 2},
0302     {36864000, 192000, 2, 3},
0303     {49152000, 192000, 2, 4},
0304 };
0305 
0306 static int cs4265_get_clk_index(int mclk, int rate)
0307 {
0308     int i;
0309 
0310     for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
0311         if (clk_map_table[i].rate == rate &&
0312                 clk_map_table[i].mclk == mclk)
0313             return i;
0314     }
0315     return -EINVAL;
0316 }
0317 
0318 static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
0319             unsigned int freq, int dir)
0320 {
0321     struct snd_soc_component *component = codec_dai->component;
0322     struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
0323     int i;
0324 
0325     if (clk_id != 0) {
0326         dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
0327         return -EINVAL;
0328     }
0329     for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
0330         if (clk_map_table[i].mclk == freq) {
0331             cs4265->sysclk = freq;
0332             return 0;
0333         }
0334     }
0335     cs4265->sysclk = 0;
0336     dev_err(component->dev, "Invalid freq parameter %d\n", freq);
0337     return -EINVAL;
0338 }
0339 
0340 static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0341 {
0342     struct snd_soc_component *component = codec_dai->component;
0343     struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
0344     u8 iface = 0;
0345 
0346     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0347     case SND_SOC_DAIFMT_CBM_CFM:
0348         snd_soc_component_update_bits(component, CS4265_ADC_CTL,
0349                 CS4265_ADC_MASTER,
0350                 CS4265_ADC_MASTER);
0351         break;
0352     case SND_SOC_DAIFMT_CBS_CFS:
0353         snd_soc_component_update_bits(component, CS4265_ADC_CTL,
0354                 CS4265_ADC_MASTER,
0355                 0);
0356         break;
0357     default:
0358         return -EINVAL;
0359     }
0360 
0361      /* interface format */
0362     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0363     case SND_SOC_DAIFMT_I2S:
0364         iface |= SND_SOC_DAIFMT_I2S;
0365         break;
0366     case SND_SOC_DAIFMT_RIGHT_J:
0367         iface |= SND_SOC_DAIFMT_RIGHT_J;
0368         break;
0369     case SND_SOC_DAIFMT_LEFT_J:
0370         iface |= SND_SOC_DAIFMT_LEFT_J;
0371         break;
0372     default:
0373         return -EINVAL;
0374     }
0375 
0376     cs4265->format = iface;
0377     return 0;
0378 }
0379 
0380 static int cs4265_mute(struct snd_soc_dai *dai, int mute, int direction)
0381 {
0382     struct snd_soc_component *component = dai->component;
0383 
0384     if (mute) {
0385         snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0386             CS4265_DAC_CTL_MUTE,
0387             CS4265_DAC_CTL_MUTE);
0388         snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0389             CS4265_SPDIF_CTL2_MUTE,
0390             CS4265_SPDIF_CTL2_MUTE);
0391     } else {
0392         snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0393             CS4265_DAC_CTL_MUTE,
0394             0);
0395         snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0396             CS4265_SPDIF_CTL2_MUTE,
0397             0);
0398     }
0399     return 0;
0400 }
0401 
0402 static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
0403                      struct snd_pcm_hw_params *params,
0404                      struct snd_soc_dai *dai)
0405 {
0406     struct snd_soc_component *component = dai->component;
0407     struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
0408     int index;
0409 
0410     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
0411         ((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
0412         == SND_SOC_DAIFMT_RIGHT_J))
0413         return -EINVAL;
0414 
0415     index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
0416     if (index >= 0) {
0417         snd_soc_component_update_bits(component, CS4265_ADC_CTL,
0418             CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
0419         snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
0420             CS4265_MCLK_FREQ_MASK,
0421             clk_map_table[index].mclkdiv << 4);
0422 
0423     } else {
0424         dev_err(component->dev, "can't get correct mclk\n");
0425         return -EINVAL;
0426     }
0427 
0428     switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
0429     case SND_SOC_DAIFMT_I2S:
0430         snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0431             CS4265_DAC_CTL_DIF, (1 << 4));
0432         snd_soc_component_update_bits(component, CS4265_ADC_CTL,
0433             CS4265_ADC_DIF, (1 << 4));
0434         snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0435             CS4265_SPDIF_CTL2_DIF, (1 << 6));
0436         break;
0437     case SND_SOC_DAIFMT_RIGHT_J:
0438         if (params_width(params) == 16) {
0439             snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0440                 CS4265_DAC_CTL_DIF, (2 << 4));
0441             snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0442                 CS4265_SPDIF_CTL2_DIF, (2 << 6));
0443         } else {
0444             snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0445                 CS4265_DAC_CTL_DIF, (3 << 4));
0446             snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0447                 CS4265_SPDIF_CTL2_DIF, (3 << 6));
0448         }
0449         break;
0450     case SND_SOC_DAIFMT_LEFT_J:
0451         snd_soc_component_update_bits(component, CS4265_DAC_CTL,
0452             CS4265_DAC_CTL_DIF, 0);
0453         snd_soc_component_update_bits(component, CS4265_ADC_CTL,
0454             CS4265_ADC_DIF, 0);
0455         snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
0456             CS4265_SPDIF_CTL2_DIF, 0);
0457 
0458         break;
0459     default:
0460         return -EINVAL;
0461     }
0462     return 0;
0463 }
0464 
0465 static int cs4265_set_bias_level(struct snd_soc_component *component,
0466                     enum snd_soc_bias_level level)
0467 {
0468     switch (level) {
0469     case SND_SOC_BIAS_ON:
0470         break;
0471     case SND_SOC_BIAS_PREPARE:
0472         snd_soc_component_update_bits(component, CS4265_PWRCTL,
0473             CS4265_PWRCTL_PDN, 0);
0474         break;
0475     case SND_SOC_BIAS_STANDBY:
0476         snd_soc_component_update_bits(component, CS4265_PWRCTL,
0477             CS4265_PWRCTL_PDN,
0478             CS4265_PWRCTL_PDN);
0479         break;
0480     case SND_SOC_BIAS_OFF:
0481         snd_soc_component_update_bits(component, CS4265_PWRCTL,
0482             CS4265_PWRCTL_PDN,
0483             CS4265_PWRCTL_PDN);
0484         break;
0485     }
0486     return 0;
0487 }
0488 
0489 #define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
0490             SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
0491             SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
0492             SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
0493 
0494 #define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
0495             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
0496             SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
0497 
0498 static const struct snd_soc_dai_ops cs4265_ops = {
0499     .hw_params  = cs4265_pcm_hw_params,
0500     .mute_stream    = cs4265_mute,
0501     .set_fmt    = cs4265_set_fmt,
0502     .set_sysclk = cs4265_set_sysclk,
0503     .no_capture_mute = 1,
0504 };
0505 
0506 static struct snd_soc_dai_driver cs4265_dai[] = {
0507     {
0508         .name = "cs4265-dai1",
0509         .playback = {
0510             .stream_name = "DAI1 Playback",
0511             .channels_min = 1,
0512             .channels_max = 2,
0513             .rates = CS4265_RATES,
0514             .formats = CS4265_FORMATS,
0515         },
0516         .capture = {
0517             .stream_name = "DAI1 Capture",
0518             .channels_min = 1,
0519             .channels_max = 2,
0520             .rates = CS4265_RATES,
0521             .formats = CS4265_FORMATS,
0522         },
0523         .ops = &cs4265_ops,
0524     },
0525     {
0526         .name = "cs4265-dai2",
0527         .playback = {
0528             .stream_name = "DAI2 Playback",
0529             .channels_min = 1,
0530             .channels_max = 2,
0531             .rates = CS4265_RATES,
0532             .formats = CS4265_FORMATS,
0533         },
0534         .capture = {
0535             .stream_name = "DAI2 Capture",
0536             .channels_min = 1,
0537             .channels_max = 2,
0538             .rates = CS4265_RATES,
0539             .formats = CS4265_FORMATS,
0540         },
0541         .ops = &cs4265_ops,
0542     },
0543 };
0544 
0545 static const struct snd_soc_component_driver soc_component_cs4265 = {
0546     .set_bias_level     = cs4265_set_bias_level,
0547     .controls       = cs4265_snd_controls,
0548     .num_controls       = ARRAY_SIZE(cs4265_snd_controls),
0549     .dapm_widgets       = cs4265_dapm_widgets,
0550     .num_dapm_widgets   = ARRAY_SIZE(cs4265_dapm_widgets),
0551     .dapm_routes        = cs4265_audio_map,
0552     .num_dapm_routes    = ARRAY_SIZE(cs4265_audio_map),
0553     .idle_bias_on       = 1,
0554     .use_pmdown_time    = 1,
0555     .endianness     = 1,
0556 };
0557 
0558 static const struct regmap_config cs4265_regmap = {
0559     .reg_bits = 8,
0560     .val_bits = 8,
0561 
0562     .max_register = CS4265_MAX_REGISTER,
0563     .reg_defaults = cs4265_reg_defaults,
0564     .num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
0565     .readable_reg = cs4265_readable_register,
0566     .volatile_reg = cs4265_volatile_register,
0567     .cache_type = REGCACHE_RBTREE,
0568 };
0569 
0570 static int cs4265_i2c_probe(struct i2c_client *i2c_client)
0571 {
0572     struct cs4265_private *cs4265;
0573     int ret;
0574     unsigned int devid = 0;
0575     unsigned int reg;
0576 
0577     cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
0578                    GFP_KERNEL);
0579     if (cs4265 == NULL)
0580         return -ENOMEM;
0581 
0582     cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
0583     if (IS_ERR(cs4265->regmap)) {
0584         ret = PTR_ERR(cs4265->regmap);
0585         dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
0586         return ret;
0587     }
0588 
0589     cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
0590         "reset", GPIOD_OUT_LOW);
0591     if (IS_ERR(cs4265->reset_gpio))
0592         return PTR_ERR(cs4265->reset_gpio);
0593 
0594     if (cs4265->reset_gpio) {
0595         mdelay(1);
0596         gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
0597     }
0598 
0599     i2c_set_clientdata(i2c_client, cs4265);
0600 
0601     ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, &reg);
0602     if (ret) {
0603         dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
0604         return ret;
0605     }
0606 
0607     devid = reg & CS4265_CHIP_ID_MASK;
0608     if (devid != CS4265_CHIP_ID_VAL) {
0609         ret = -ENODEV;
0610         dev_err(&i2c_client->dev,
0611             "CS4265 Part Number ID: 0x%x Expected: 0x%x\n",
0612             devid >> 4, CS4265_CHIP_ID_VAL >> 4);
0613         return ret;
0614     }
0615     dev_info(&i2c_client->dev,
0616         "CS4265 Version %x\n",
0617             reg & CS4265_REV_ID_MASK);
0618 
0619     regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);
0620 
0621     return devm_snd_soc_register_component(&i2c_client->dev,
0622             &soc_component_cs4265, cs4265_dai,
0623             ARRAY_SIZE(cs4265_dai));
0624 }
0625 
0626 static int cs4265_i2c_remove(struct i2c_client *i2c)
0627 {
0628     struct cs4265_private *cs4265 = i2c_get_clientdata(i2c);
0629 
0630     if (cs4265->reset_gpio)
0631         gpiod_set_value_cansleep(cs4265->reset_gpio, 0);
0632 
0633     return 0;
0634 }
0635 
0636 static const struct of_device_id cs4265_of_match[] = {
0637     { .compatible = "cirrus,cs4265", },
0638     { }
0639 };
0640 MODULE_DEVICE_TABLE(of, cs4265_of_match);
0641 
0642 static const struct i2c_device_id cs4265_id[] = {
0643     { "cs4265", 0 },
0644     { }
0645 };
0646 MODULE_DEVICE_TABLE(i2c, cs4265_id);
0647 
0648 static struct i2c_driver cs4265_i2c_driver = {
0649     .driver = {
0650         .name = "cs4265",
0651         .of_match_table = cs4265_of_match,
0652     },
0653     .id_table = cs4265_id,
0654     .probe_new = cs4265_i2c_probe,
0655     .remove =   cs4265_i2c_remove,
0656 };
0657 
0658 module_i2c_driver(cs4265_i2c_driver);
0659 
0660 MODULE_DESCRIPTION("ASoC CS4265 driver");
0661 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
0662 MODULE_LICENSE("GPL");
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