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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // cs4234.c -- ALSA SoC CS4234 driver
0003 //
0004 // Copyright (C) 2020 Cirrus Logic, Inc. and
0005 //                    Cirrus Logic International Semiconductor Ltd.
0006 //
0007 
0008 #include <linux/clk.h>
0009 #include <linux/completion.h>
0010 #include <linux/delay.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/i2c.h>
0013 #include <linux/jiffies.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/module.h>
0016 #include <sound/pcm.h>
0017 #include <sound/pcm_params.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/regmap.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/slab.h>
0022 #include <sound/soc.h>
0023 #include <sound/tlv.h>
0024 #include <linux/workqueue.h>
0025 
0026 #include "cs4234.h"
0027 
0028 struct cs4234 {
0029     struct device *dev;
0030     struct regmap *regmap;
0031     struct gpio_desc *reset_gpio;
0032     struct regulator_bulk_data core_supplies[2];
0033     int num_core_supplies;
0034     struct completion vq_ramp_complete;
0035     struct delayed_work vq_ramp_delay;
0036     struct clk *mclk;
0037     unsigned long mclk_rate;
0038     unsigned long lrclk_rate;
0039     unsigned int format;
0040     struct snd_ratnum rate_dividers[2];
0041     struct snd_pcm_hw_constraint_ratnums rate_constraint;
0042 };
0043 
0044 /* -89.92dB to +6.02dB with step of 0.38dB */
0045 static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0);
0046 
0047 static const char * const cs4234_dac14_delay_text[] = {
0048       "0us", "100us", "150us", "200us", "225us", "250us", "275us", "300us",
0049     "325us", "350us", "375us", "400us", "425us", "450us", "475us", "500us",
0050 };
0051 static SOC_ENUM_SINGLE_DECL(cs4234_dac14_group_delay, CS4234_TPS_CTRL,
0052                 CS4234_GRP_DELAY_SHIFT, cs4234_dac14_delay_text);
0053 
0054 static const char * const cs4234_noise_gate_text[] = {
0055     "72dB",  "78dB",  "84dB", "90dB", "96dB", "102dB", "138dB", "Disabled",
0056 };
0057 static SOC_ENUM_SINGLE_DECL(cs4234_ll_noise_gate, CS4234_LOW_LAT_CTRL1,
0058                 CS4234_LL_NG_SHIFT, cs4234_noise_gate_text);
0059 static SOC_ENUM_SINGLE_DECL(cs4234_dac14_noise_gate, CS4234_DAC_CTRL1,
0060                 CS4234_DAC14_NG_SHIFT, cs4234_noise_gate_text);
0061 static SOC_ENUM_SINGLE_DECL(cs4234_dac5_noise_gate, CS4234_DAC_CTRL2,
0062                 CS4234_DAC5_NG_SHIFT, cs4234_noise_gate_text);
0063 
0064 static const char * const cs4234_dac5_config_fltr_sel_text[] = {
0065     "Interpolation Filter", "Sample and Hold"
0066 };
0067 static SOC_ENUM_SINGLE_DECL(cs4234_dac5_config_fltr_sel, CS4234_DAC_CTRL1,
0068                 CS4234_DAC5_CFG_FLTR_SHIFT,
0069                 cs4234_dac5_config_fltr_sel_text);
0070 
0071 static const char * const cs4234_mute_delay_text[] = {
0072     "1x",  "4x",  "16x", "64x",
0073 };
0074 static SOC_ENUM_SINGLE_DECL(cs4234_mute_delay, CS4234_VOLUME_MODE,
0075                 CS4234_MUTE_DELAY_SHIFT, cs4234_mute_delay_text);
0076 
0077 static const char * const cs4234_minmax_delay_text[] = {
0078     "1x",  "2x",  "4x", "8x", "16x",  "32x", "64x", "128x",
0079 };
0080 static SOC_ENUM_SINGLE_DECL(cs4234_min_delay, CS4234_VOLUME_MODE,
0081                 CS4234_MIN_DELAY_SHIFT, cs4234_minmax_delay_text);
0082 static SOC_ENUM_SINGLE_DECL(cs4234_max_delay, CS4234_VOLUME_MODE,
0083                 CS4234_MAX_DELAY_SHIFT, cs4234_minmax_delay_text);
0084 
0085 static int cs4234_dac14_grp_delay_put(struct snd_kcontrol *kctrl,
0086                       struct snd_ctl_elem_value *uctrl)
0087 {
0088     struct snd_soc_component *component = snd_soc_kcontrol_component(kctrl);
0089     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
0090     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0091     unsigned int val = 0;
0092     int ret = 0;
0093 
0094     snd_soc_dapm_mutex_lock(dapm);
0095 
0096     regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val);
0097     if ((val & 0x0F) != 0x0F) { // are all the ADCs powerdown
0098         ret = -EBUSY;
0099         dev_err(component->dev, "Can't change group delay while ADC are ON\n");
0100         goto exit;
0101     }
0102 
0103     regmap_read(cs4234->regmap, CS4234_DAC_CTRL4, &val);
0104     if ((val & 0x1F) != 0x1F) { // are all the DACs powerdown
0105         ret = -EBUSY;
0106         dev_err(component->dev, "Can't change group delay while DAC are ON\n");
0107         goto exit;
0108     }
0109 
0110     ret = snd_soc_put_enum_double(kctrl, uctrl);
0111 exit:
0112     snd_soc_dapm_mutex_unlock(dapm);
0113 
0114     return ret;
0115 }
0116 
0117 static void cs4234_vq_ramp_done(struct work_struct *work)
0118 {
0119     struct delayed_work *dw = to_delayed_work(work);
0120     struct cs4234 *cs4234 = container_of(dw, struct cs4234, vq_ramp_delay);
0121 
0122     complete_all(&cs4234->vq_ramp_complete);
0123 }
0124 
0125 static int cs4234_set_bias_level(struct snd_soc_component *component,
0126                  enum snd_soc_bias_level level)
0127 {
0128     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
0129 
0130     switch (level) {
0131     case SND_SOC_BIAS_PREPARE:
0132         switch (snd_soc_component_get_bias_level(component)) {
0133         case SND_SOC_BIAS_STANDBY:
0134             wait_for_completion(&cs4234->vq_ramp_complete);
0135             break;
0136         default:
0137             break;
0138         }
0139         break;
0140     default:
0141         break;
0142     }
0143 
0144     return 0;
0145 }
0146 
0147 static const struct snd_soc_dapm_widget cs4234_dapm_widgets[] = {
0148     SND_SOC_DAPM_AIF_IN("SDRX1", NULL,  0, SND_SOC_NOPM, 0, 0),
0149     SND_SOC_DAPM_AIF_IN("SDRX2", NULL,  1, SND_SOC_NOPM, 0, 0),
0150     SND_SOC_DAPM_AIF_IN("SDRX3", NULL,  2, SND_SOC_NOPM, 0, 0),
0151     SND_SOC_DAPM_AIF_IN("SDRX4", NULL,  3, SND_SOC_NOPM, 0, 0),
0152     SND_SOC_DAPM_AIF_IN("SDRX5", NULL,  4, SND_SOC_NOPM, 0, 0),
0153 
0154     SND_SOC_DAPM_DAC("DAC1", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC1_SHIFT, 1),
0155     SND_SOC_DAPM_DAC("DAC2", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC2_SHIFT, 1),
0156     SND_SOC_DAPM_DAC("DAC3", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC3_SHIFT, 1),
0157     SND_SOC_DAPM_DAC("DAC4", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC4_SHIFT, 1),
0158     SND_SOC_DAPM_DAC("DAC5", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC5_SHIFT, 1),
0159 
0160     SND_SOC_DAPM_OUTPUT("AOUT1"),
0161     SND_SOC_DAPM_OUTPUT("AOUT2"),
0162     SND_SOC_DAPM_OUTPUT("AOUT3"),
0163     SND_SOC_DAPM_OUTPUT("AOUT4"),
0164     SND_SOC_DAPM_OUTPUT("AOUT5"),
0165 
0166     SND_SOC_DAPM_INPUT("AIN1"),
0167     SND_SOC_DAPM_INPUT("AIN2"),
0168     SND_SOC_DAPM_INPUT("AIN3"),
0169     SND_SOC_DAPM_INPUT("AIN4"),
0170 
0171     SND_SOC_DAPM_ADC("ADC1", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC1_SHIFT, 1),
0172     SND_SOC_DAPM_ADC("ADC2", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC2_SHIFT, 1),
0173     SND_SOC_DAPM_ADC("ADC3", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC3_SHIFT, 1),
0174     SND_SOC_DAPM_ADC("ADC4", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC4_SHIFT, 1),
0175 
0176     SND_SOC_DAPM_AIF_OUT("SDTX1", NULL, 0, SND_SOC_NOPM, 0, 1),
0177     SND_SOC_DAPM_AIF_OUT("SDTX2", NULL, 1, SND_SOC_NOPM, 0, 1),
0178     SND_SOC_DAPM_AIF_OUT("SDTX3", NULL, 2, SND_SOC_NOPM, 0, 1),
0179     SND_SOC_DAPM_AIF_OUT("SDTX4", NULL, 3, SND_SOC_NOPM, 0, 1),
0180 };
0181 
0182 static const struct snd_soc_dapm_route cs4234_dapm_routes[] = {
0183     /* Playback */
0184     { "AOUT1", NULL, "DAC1" },
0185     { "AOUT2", NULL, "DAC2" },
0186     { "AOUT3", NULL, "DAC3" },
0187     { "AOUT4", NULL, "DAC4" },
0188     { "AOUT5", NULL, "DAC5" },
0189 
0190     { "DAC1", NULL, "SDRX1" },
0191     { "DAC2", NULL, "SDRX2" },
0192     { "DAC3", NULL, "SDRX3" },
0193     { "DAC4", NULL, "SDRX4" },
0194     { "DAC5", NULL, "SDRX5" },
0195 
0196     { "SDRX1", NULL, "Playback" },
0197     { "SDRX2", NULL, "Playback" },
0198     { "SDRX3", NULL, "Playback" },
0199     { "SDRX4", NULL, "Playback" },
0200     { "SDRX5", NULL, "Playback" },
0201 
0202     /* Capture */
0203     { "ADC1", NULL, "AIN1" },
0204     { "ADC2", NULL, "AIN2" },
0205     { "ADC3", NULL, "AIN3" },
0206     { "ADC4", NULL, "AIN4" },
0207 
0208     { "SDTX1", NULL, "ADC1" },
0209     { "SDTX2", NULL, "ADC2" },
0210     { "SDTX3", NULL, "ADC3" },
0211     { "SDTX4", NULL, "ADC4" },
0212 
0213     { "Capture", NULL, "SDTX1" },
0214     { "Capture", NULL, "SDTX2" },
0215     { "Capture", NULL, "SDTX3" },
0216     { "Capture", NULL, "SDTX4" },
0217 };
0218 
0219 static const struct snd_kcontrol_new cs4234_snd_controls[] = {
0220     SOC_SINGLE_TLV("Master Volume", CS4234_MASTER_VOL, 0, 0xff, 1, dac_tlv),
0221     SOC_SINGLE_TLV("DAC1 Volume", CS4234_DAC1_VOL, 0, 0xff, 1, dac_tlv),
0222     SOC_SINGLE_TLV("DAC2 Volume", CS4234_DAC2_VOL, 0, 0xff, 1, dac_tlv),
0223     SOC_SINGLE_TLV("DAC3 Volume", CS4234_DAC3_VOL, 0, 0xff, 1, dac_tlv),
0224     SOC_SINGLE_TLV("DAC4 Volume", CS4234_DAC4_VOL, 0, 0xff, 1, dac_tlv),
0225     SOC_SINGLE_TLV("DAC5 Volume", CS4234_DAC5_VOL, 0, 0xff, 1, dac_tlv),
0226 
0227     SOC_SINGLE("DAC5 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC5_ATT_SHIFT, 1, 1),
0228     SOC_SINGLE("DAC1-4 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC14_ATT_SHIFT, 1, 1),
0229 
0230     SOC_SINGLE("ADC HPF Switch", CS4234_ADC_CTRL1, CS4234_ENA_HPF_SHIFT, 1, 0),
0231 
0232     SOC_ENUM_EXT("DAC1-4 Group Delay", cs4234_dac14_group_delay,
0233              snd_soc_get_enum_double, cs4234_dac14_grp_delay_put),
0234 
0235     SOC_SINGLE("ADC1 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC1_SHIFT, 1, 0),
0236     SOC_SINGLE("ADC2 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC2_SHIFT, 1, 0),
0237     SOC_SINGLE("ADC3 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC3_SHIFT, 1, 0),
0238     SOC_SINGLE("ADC4 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC4_SHIFT, 1, 0),
0239 
0240     SOC_SINGLE("DAC1 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC1_SHIFT, 1, 0),
0241     SOC_SINGLE("DAC2 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC2_SHIFT, 1, 0),
0242     SOC_SINGLE("DAC3 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC3_SHIFT, 1, 0),
0243     SOC_SINGLE("DAC4 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC4_SHIFT, 1, 0),
0244     SOC_SINGLE("DAC5 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC5_SHIFT, 1, 0),
0245 
0246     SOC_SINGLE("ADC1 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC1_SHIFT, 1, 1),
0247     SOC_SINGLE("ADC2 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC2_SHIFT, 1, 1),
0248     SOC_SINGLE("ADC3 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC3_SHIFT, 1, 1),
0249     SOC_SINGLE("ADC4 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC4_SHIFT, 1, 1),
0250 
0251     SOC_SINGLE("DAC1 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC1_SHIFT, 1, 1),
0252     SOC_SINGLE("DAC2 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC2_SHIFT, 1, 1),
0253     SOC_SINGLE("DAC3 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC3_SHIFT, 1, 1),
0254     SOC_SINGLE("DAC4 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC4_SHIFT, 1, 1),
0255     SOC_SINGLE("DAC5 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC5_SHIFT, 1, 1),
0256     SOC_SINGLE("Low-latency Switch", CS4234_DAC_CTRL3, CS4234_MUTE_LL_SHIFT, 1, 1),
0257 
0258     SOC_SINGLE("DAC1 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
0259            CS4234_INV_LL1_SHIFT, 1, 0),
0260     SOC_SINGLE("DAC2 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
0261            CS4234_INV_LL2_SHIFT, 1, 0),
0262     SOC_SINGLE("DAC3 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
0263            CS4234_INV_LL3_SHIFT, 1, 0),
0264     SOC_SINGLE("DAC4 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
0265            CS4234_INV_LL4_SHIFT, 1, 0),
0266 
0267     SOC_ENUM("Low-latency Noise Gate", cs4234_ll_noise_gate),
0268     SOC_ENUM("DAC1-4 Noise Gate", cs4234_dac14_noise_gate),
0269     SOC_ENUM("DAC5 Noise Gate", cs4234_dac5_noise_gate),
0270 
0271     SOC_SINGLE("DAC1-4 De-emphasis Switch", CS4234_DAC_CTRL1,
0272            CS4234_DAC14_DE_SHIFT, 1, 0),
0273     SOC_SINGLE("DAC5 De-emphasis Switch", CS4234_DAC_CTRL1,
0274            CS4234_DAC5_DE_SHIFT, 1, 0),
0275 
0276     SOC_SINGLE("DAC5 Master Controlled Switch", CS4234_DAC_CTRL1,
0277            CS4234_DAC5_MVC_SHIFT, 1, 0),
0278 
0279     SOC_ENUM("DAC5 Filter", cs4234_dac5_config_fltr_sel),
0280 
0281     SOC_ENUM("Mute Delay", cs4234_mute_delay),
0282     SOC_ENUM("Ramp Minimum Delay", cs4234_min_delay),
0283     SOC_ENUM("Ramp Maximum Delay", cs4234_max_delay),
0284 
0285 };
0286 
0287 static int cs4234_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int format)
0288 {
0289     struct snd_soc_component *component = codec_dai->component;
0290     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
0291     unsigned int sp_ctrl = 0;
0292 
0293     cs4234->format = format & SND_SOC_DAIFMT_FORMAT_MASK;
0294     switch (cs4234->format) {
0295     case SND_SOC_DAIFMT_LEFT_J:
0296         sp_ctrl |= CS4234_LEFT_J << CS4234_SP_FORMAT_SHIFT;
0297         break;
0298     case SND_SOC_DAIFMT_I2S:
0299         sp_ctrl |= CS4234_I2S << CS4234_SP_FORMAT_SHIFT;
0300         break;
0301     case SND_SOC_DAIFMT_DSP_A: /* TDM mode in datasheet */
0302         sp_ctrl |= CS4234_TDM << CS4234_SP_FORMAT_SHIFT;
0303         break;
0304     default:
0305         dev_err(component->dev, "Unsupported dai format\n");
0306         return -EINVAL;
0307     }
0308 
0309     switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
0310     case SND_SOC_DAIFMT_CBS_CFS:
0311         break;
0312     case SND_SOC_DAIFMT_CBM_CFM:
0313         if (cs4234->format == SND_SOC_DAIFMT_DSP_A) {
0314             dev_err(component->dev, "Unsupported DSP A format in master mode\n");
0315             return -EINVAL;
0316         }
0317         sp_ctrl |= CS4234_MST_SLV_MASK;
0318         break;
0319     default:
0320         dev_err(component->dev, "Unsupported master/slave mode\n");
0321         return -EINVAL;
0322     }
0323 
0324     switch (format & SND_SOC_DAIFMT_INV_MASK) {
0325     case SND_SOC_DAIFMT_NB_NF:
0326         break;
0327     case SND_SOC_DAIFMT_IB_NF:
0328         sp_ctrl |= CS4234_INVT_SCLK_MASK;
0329         break;
0330     default:
0331         dev_err(component->dev, "Unsupported inverted clock setting\n");
0332         return -EINVAL;
0333     }
0334 
0335     regmap_update_bits(cs4234->regmap, CS4234_SP_CTRL,
0336                CS4234_SP_FORMAT_MASK | CS4234_MST_SLV_MASK | CS4234_INVT_SCLK_MASK,
0337                sp_ctrl);
0338 
0339     return 0;
0340 }
0341 
0342 static int cs4234_dai_hw_params(struct snd_pcm_substream *sub,
0343                 struct snd_pcm_hw_params *params,
0344                 struct snd_soc_dai *dai)
0345 {
0346     struct snd_soc_component *component = dai->component;
0347     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
0348     unsigned int mclk_mult, double_speed = 0;
0349     int ret = 0, rate_ad, sample_width;
0350 
0351     cs4234->lrclk_rate = params_rate(params);
0352     mclk_mult = cs4234->mclk_rate / cs4234->lrclk_rate;
0353 
0354     if (cs4234->lrclk_rate > 48000) {
0355         double_speed = 1;
0356         mclk_mult *= 2;
0357     }
0358 
0359     switch (mclk_mult) {
0360     case 256:
0361     case 384:
0362     case 512:
0363         regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
0364                    CS4234_SPEED_MODE_MASK,
0365                    double_speed << CS4234_SPEED_MODE_SHIFT);
0366         regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
0367                    CS4234_MCLK_RATE_MASK,
0368                    ((mclk_mult / 128) - 2) << CS4234_MCLK_RATE_SHIFT);
0369         break;
0370     default:
0371         dev_err(component->dev, "Unsupported mclk/lrclk rate\n");
0372         return -EINVAL;
0373     }
0374 
0375     switch (cs4234->lrclk_rate) {
0376     case 48000:
0377     case 96000:
0378         rate_ad = CS4234_48K;
0379         break;
0380     case 44100:
0381     case 88200:
0382         rate_ad = CS4234_44K1;
0383         break;
0384     case 32000:
0385     case 64000:
0386         rate_ad = CS4234_32K;
0387         break;
0388     default:
0389         dev_err(component->dev, "Unsupported LR clock\n");
0390         return -EINVAL;
0391     }
0392     regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, CS4234_BASE_RATE_MASK,
0393                rate_ad << CS4234_BASE_RATE_SHIFT);
0394 
0395     sample_width = params_width(params);
0396     switch (sample_width) {
0397     case 16:
0398         sample_width = 0;
0399         break;
0400     case 18:
0401         sample_width = 1;
0402         break;
0403     case 20:
0404         sample_width = 2;
0405         break;
0406     case 24:
0407         sample_width = 3;
0408         break;
0409     default:
0410         dev_err(component->dev, "Unsupported sample width\n");
0411         return -EINVAL;
0412     }
0413     if (sub->stream == SNDRV_PCM_STREAM_CAPTURE)
0414         regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
0415                    CS4234_SDOUTX_SW_MASK,
0416                    sample_width << CS4234_SDOUTX_SW_SHIFT);
0417     else
0418         regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
0419                 CS4234_INPUT_SW_MASK | CS4234_LOW_LAT_SW_MASK | CS4234_DAC5_SW_MASK,
0420                 sample_width << CS4234_INPUT_SW_SHIFT |
0421                 sample_width << CS4234_LOW_LAT_SW_SHIFT |
0422                 sample_width << CS4234_DAC5_SW_SHIFT);
0423 
0424     return ret;
0425 }
0426 
0427 /* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */
0428 #define CS4234_MCLK_SCALE  64
0429 
0430 static const struct snd_ratnum cs4234_dividers[] = {
0431     {
0432         .num = 0,
0433         .den_min = 256 / CS4234_MCLK_SCALE,
0434         .den_max = 512 / CS4234_MCLK_SCALE,
0435         .den_step = 128 / CS4234_MCLK_SCALE,
0436     },
0437     {
0438         .num = 0,
0439         .den_min = 128 / CS4234_MCLK_SCALE,
0440         .den_max = 192 / CS4234_MCLK_SCALE,
0441         .den_step = 64 / CS4234_MCLK_SCALE,
0442     },
0443 };
0444 
0445 static int cs4234_dai_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
0446 {
0447     struct cs4234 *cs4234 = rule->private;
0448     int mclk = cs4234->mclk_rate;
0449     struct snd_interval ranges[] = {
0450         { /* Single Speed Mode */
0451             .min = mclk / clamp(mclk / 30000, 256, 512),
0452             .max = mclk / clamp(mclk / 50000, 256, 512),
0453         },
0454         { /* Double Speed Mode */
0455             .min = mclk / clamp(mclk / 60000,  128, 256),
0456             .max = mclk / clamp(mclk / 100000, 128, 256),
0457         },
0458     };
0459 
0460     return snd_interval_ranges(hw_param_interval(params, rule->var),
0461                    ARRAY_SIZE(ranges), ranges, 0);
0462 }
0463 
0464 static int cs4234_dai_startup(struct snd_pcm_substream *sub, struct snd_soc_dai *dai)
0465 {
0466     struct snd_soc_component *comp = dai->component;
0467     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(comp);
0468     int i, ret;
0469 
0470     switch (cs4234->format) {
0471     case SND_SOC_DAIFMT_LEFT_J:
0472     case SND_SOC_DAIFMT_I2S:
0473         cs4234->rate_constraint.nrats = 2;
0474 
0475         /*
0476          * Playback only supports 24-bit samples in these modes.
0477          * Note: SNDRV_PCM_HW_PARAM_SAMPLE_BITS constrains the physical
0478          * width, which we don't care about, so constrain the format.
0479          */
0480         if (sub->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0481             ret = snd_pcm_hw_constraint_mask64(
0482                         sub->runtime,
0483                         SNDRV_PCM_HW_PARAM_FORMAT,
0484                         SNDRV_PCM_FMTBIT_S24_LE |
0485                         SNDRV_PCM_FMTBIT_S24_3LE);
0486             if (ret < 0)
0487                 return ret;
0488 
0489             ret = snd_pcm_hw_constraint_minmax(sub->runtime,
0490                                SNDRV_PCM_HW_PARAM_CHANNELS,
0491                                1, 4);
0492             if (ret < 0)
0493                 return ret;
0494         }
0495 
0496         break;
0497     case SND_SOC_DAIFMT_DSP_A:
0498         cs4234->rate_constraint.nrats = 1;
0499         break;
0500     default:
0501         dev_err(comp->dev, "Startup unsupported DAI format\n");
0502         return -EINVAL;
0503     }
0504 
0505     for (i = 0; i < cs4234->rate_constraint.nrats; i++)
0506         cs4234->rate_dividers[i].num = cs4234->mclk_rate / CS4234_MCLK_SCALE;
0507 
0508     ret = snd_pcm_hw_constraint_ratnums(sub->runtime, 0,
0509                         SNDRV_PCM_HW_PARAM_RATE,
0510                         &cs4234->rate_constraint);
0511     if (ret < 0)
0512         return ret;
0513 
0514     /*
0515      * MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000)
0516      * so this rule limits the range of sample rate for given MCLK.
0517      */
0518     return snd_pcm_hw_rule_add(sub->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
0519                    cs4234_dai_rule_rate, cs4234, -1);
0520 }
0521 
0522 static int cs4234_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0523                    unsigned int rx_mask, int slots, int slot_width)
0524 {
0525     struct snd_soc_component *component = dai->component;
0526     struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
0527     unsigned int slot_offset, dac5_slot, dac5_mask_group;
0528     uint8_t dac5_masks[4];
0529 
0530     if (slot_width != 32) {
0531         dev_err(component->dev, "Unsupported slot width\n");
0532         return -EINVAL;
0533     }
0534 
0535     /* Either 4 or 5 consecutive bits, DAC5 is optional */
0536     slot_offset = ffs(tx_mask) - 1;
0537     tx_mask >>= slot_offset;
0538     if ((slot_offset % 4) || ((tx_mask != 0x0F) && (tx_mask != 0x1F))) {
0539         dev_err(component->dev, "Unsupported tx slots allocation\n");
0540         return -EINVAL;
0541     }
0542 
0543     regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_DAC14_SRC_MASK,
0544                (slot_offset / 4) << CS4234_DAC14_SRC_SHIFT);
0545     regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_LL_SRC_MASK,
0546                (slot_offset / 4) << CS4234_LL_SRC_SHIFT);
0547 
0548     if (tx_mask == 0x1F) {
0549         dac5_slot = slot_offset + 4;
0550         memset(dac5_masks, 0xFF, sizeof(dac5_masks));
0551         dac5_mask_group = dac5_slot / 8;
0552         dac5_slot %= 8;
0553         dac5_masks[dac5_mask_group] ^= BIT(7 - dac5_slot);
0554         regmap_bulk_write(cs4234->regmap,
0555                   CS4234_SDIN1_MASK1,
0556                   dac5_masks,
0557                   ARRAY_SIZE(dac5_masks));
0558     }
0559 
0560     return 0;
0561 }
0562 
0563 static const struct snd_soc_dai_ops cs4234_dai_ops = {
0564     .set_fmt    = cs4234_dai_set_fmt,
0565     .hw_params  = cs4234_dai_hw_params,
0566     .startup    = cs4234_dai_startup,
0567     .set_tdm_slot   = cs4234_dai_set_tdm_slot,
0568 };
0569 
0570 static struct snd_soc_dai_driver cs4234_dai[] = {
0571     {
0572         .name = "cs4234-dai",
0573         .playback = {
0574             .stream_name = "Playback",
0575             .channels_min = 1,
0576             .channels_max = 5,
0577             .rates = CS4234_PCM_RATES,
0578             .formats = CS4234_FORMATS,
0579         },
0580         .capture = {
0581             .stream_name = "Capture",
0582             .channels_min = 1,
0583             .channels_max = 4,
0584             .rates = CS4234_PCM_RATES,
0585             .formats = CS4234_FORMATS,
0586         },
0587         .ops = &cs4234_dai_ops,
0588         .symmetric_rate = 1,
0589     },
0590 };
0591 
0592 static const struct reg_default cs4234_default_reg[] = {
0593     { CS4234_CLOCK_SP,   0x04},
0594     { CS4234_SAMPLE_WIDTH,   0xFF},
0595     { CS4234_SP_CTRL,    0x48},
0596     { CS4234_SP_DATA_SEL,    0x01},
0597     { CS4234_SDIN1_MASK1,    0xFF},
0598     { CS4234_SDIN1_MASK2,    0xFF},
0599     { CS4234_SDIN2_MASK1,    0xFF},
0600     { CS4234_SDIN2_MASK2,    0xFF},
0601     { CS4234_TPS_CTRL,   0x00},
0602     { CS4234_ADC_CTRL1,  0xC0},
0603     { CS4234_ADC_CTRL2,  0xFF},
0604     { CS4234_LOW_LAT_CTRL1,  0xE0},
0605     { CS4234_DAC_CTRL1,  0xE0},
0606     { CS4234_DAC_CTRL2,  0xE0},
0607     { CS4234_DAC_CTRL3,  0xBF},
0608     { CS4234_DAC_CTRL4,  0x1F},
0609     { CS4234_VOLUME_MODE,    0x87},
0610     { CS4234_MASTER_VOL,     0x10},
0611     { CS4234_DAC1_VOL,   0x10},
0612     { CS4234_DAC2_VOL,   0x10},
0613     { CS4234_DAC3_VOL,   0x10},
0614     { CS4234_DAC4_VOL,   0x10},
0615     { CS4234_DAC5_VOL,   0x10},
0616     { CS4234_INT_CTRL,   0x40},
0617     { CS4234_INT_MASK1,  0x10},
0618     { CS4234_INT_MASK2,  0x20},
0619 };
0620 
0621 static bool cs4234_readable_register(struct device *dev, unsigned int reg)
0622 {
0623     switch (reg) {
0624     case CS4234_DEVID_AB ... CS4234_DEVID_EF:
0625     case CS4234_REVID ... CS4234_DAC5_VOL:
0626     case CS4234_INT_CTRL ... CS4234_MAX_REGISTER:
0627         return true;
0628     default:
0629         return false;
0630     }
0631 }
0632 
0633 static bool cs4234_volatile_reg(struct device *dev, unsigned int reg)
0634 {
0635     switch (reg) {
0636     case CS4234_INT_NOTIFY1:
0637     case CS4234_INT_NOTIFY2:
0638         return true;
0639     default:
0640         return false;
0641     }
0642 }
0643 
0644 static bool cs4234_writeable_register(struct device *dev, unsigned int reg)
0645 {
0646     switch (reg) {
0647     case CS4234_DEVID_AB ... CS4234_REVID:
0648     case CS4234_INT_NOTIFY1 ... CS4234_INT_NOTIFY2:
0649         return false;
0650     default:
0651         return true;
0652     }
0653 }
0654 
0655 static const struct snd_soc_component_driver soc_component_cs4234 = {
0656     .dapm_widgets       = cs4234_dapm_widgets,
0657     .num_dapm_widgets   = ARRAY_SIZE(cs4234_dapm_widgets),
0658     .dapm_routes        = cs4234_dapm_routes,
0659     .num_dapm_routes    = ARRAY_SIZE(cs4234_dapm_routes),
0660     .controls       = cs4234_snd_controls,
0661     .num_controls       = ARRAY_SIZE(cs4234_snd_controls),
0662     .set_bias_level     = cs4234_set_bias_level,
0663     .idle_bias_on       = 1,
0664     .suspend_bias_off   = 1,
0665     .endianness     = 1,
0666 };
0667 
0668 static const struct regmap_config cs4234_regmap = {
0669     .reg_bits = 8,
0670     .val_bits = 8,
0671 
0672     .max_register = CS4234_MAX_REGISTER,
0673     .readable_reg = cs4234_readable_register,
0674     .volatile_reg = cs4234_volatile_reg,
0675     .writeable_reg = cs4234_writeable_register,
0676     .reg_defaults = cs4234_default_reg,
0677     .num_reg_defaults = ARRAY_SIZE(cs4234_default_reg),
0678     .cache_type = REGCACHE_RBTREE,
0679     .use_single_read = true,
0680     .use_single_write = true,
0681 };
0682 
0683 static const char * const cs4234_core_supplies[] = {
0684     "VA",
0685     "VL",
0686 };
0687 
0688 static void cs4234_shutdown(struct cs4234 *cs4234)
0689 {
0690     cancel_delayed_work_sync(&cs4234->vq_ramp_delay);
0691     reinit_completion(&cs4234->vq_ramp_complete);
0692 
0693     regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK,
0694                CS4234_VQ_RAMP_MASK);
0695     msleep(50);
0696     regcache_cache_only(cs4234->regmap, true);
0697     /* Clear VQ Ramp Bit in cache for the next PowerUp */
0698     regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK, 0);
0699     gpiod_set_value_cansleep(cs4234->reset_gpio, 0);
0700     regulator_bulk_disable(cs4234->num_core_supplies, cs4234->core_supplies);
0701     clk_disable_unprepare(cs4234->mclk);
0702 }
0703 
0704 static int cs4234_powerup(struct cs4234 *cs4234)
0705 {
0706     int ret;
0707 
0708     ret = clk_prepare_enable(cs4234->mclk);
0709     if (ret) {
0710         dev_err(cs4234->dev, "Failed to enable mclk: %d\n", ret);
0711         return ret;
0712     }
0713 
0714     ret = regulator_bulk_enable(cs4234->num_core_supplies, cs4234->core_supplies);
0715     if (ret) {
0716         dev_err(cs4234->dev, "Failed to enable core supplies: %d\n", ret);
0717         clk_disable_unprepare(cs4234->mclk);
0718         return ret;
0719     }
0720 
0721     usleep_range(CS4234_HOLD_RESET_TIME_US, 2 * CS4234_HOLD_RESET_TIME_US);
0722     gpiod_set_value_cansleep(cs4234->reset_gpio, 1);
0723 
0724     /* Make sure hardware reset done 2 ms + (3000/MCLK) */
0725     usleep_range(CS4234_BOOT_TIME_US, CS4234_BOOT_TIME_US * 2);
0726 
0727     queue_delayed_work(system_power_efficient_wq,
0728                &cs4234->vq_ramp_delay,
0729                msecs_to_jiffies(CS4234_VQ_CHARGE_MS));
0730 
0731     return 0;
0732 }
0733 
0734 static int cs4234_i2c_probe(struct i2c_client *i2c_client)
0735 {
0736     struct cs4234 *cs4234;
0737     struct device *dev = &i2c_client->dev;
0738     unsigned int revid;
0739     uint32_t devid;
0740     uint8_t ids[3];
0741     int ret = 0, i;
0742 
0743     cs4234 = devm_kzalloc(dev, sizeof(*cs4234), GFP_KERNEL);
0744     if (!cs4234)
0745         return -ENOMEM;
0746     i2c_set_clientdata(i2c_client, cs4234);
0747     cs4234->dev = dev;
0748     init_completion(&cs4234->vq_ramp_complete);
0749     INIT_DELAYED_WORK(&cs4234->vq_ramp_delay, cs4234_vq_ramp_done);
0750 
0751     cs4234->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
0752     if (IS_ERR(cs4234->reset_gpio))
0753         return PTR_ERR(cs4234->reset_gpio);
0754 
0755     BUILD_BUG_ON(ARRAY_SIZE(cs4234->core_supplies) < ARRAY_SIZE(cs4234_core_supplies));
0756 
0757     cs4234->num_core_supplies = ARRAY_SIZE(cs4234_core_supplies);
0758     for (i = 0; i < ARRAY_SIZE(cs4234_core_supplies); i++)
0759         cs4234->core_supplies[i].supply = cs4234_core_supplies[i];
0760 
0761     ret = devm_regulator_bulk_get(dev, cs4234->num_core_supplies, cs4234->core_supplies);
0762     if (ret) {
0763         dev_err(dev, "Failed to request core supplies %d\n", ret);
0764         return ret;
0765     }
0766 
0767     cs4234->mclk = devm_clk_get(dev, "mclk");
0768     if (IS_ERR(cs4234->mclk)) {
0769         ret = PTR_ERR(cs4234->mclk);
0770         dev_err(dev, "Failed to get the mclk: %d\n", ret);
0771         return ret;
0772     }
0773     cs4234->mclk_rate = clk_get_rate(cs4234->mclk);
0774 
0775     if (cs4234->mclk_rate < 7680000 || cs4234->mclk_rate > 25600000) {
0776         dev_err(dev, "Invalid Master Clock rate\n");
0777         return -EINVAL;
0778     }
0779 
0780     cs4234->regmap = devm_regmap_init_i2c(i2c_client, &cs4234_regmap);
0781     if (IS_ERR(cs4234->regmap)) {
0782         ret = PTR_ERR(cs4234->regmap);
0783         dev_err(dev, "regmap_init() failed: %d\n", ret);
0784         return ret;
0785     }
0786 
0787     ret = cs4234_powerup(cs4234);
0788     if (ret)
0789         return ret;
0790 
0791     ret = regmap_bulk_read(cs4234->regmap, CS4234_DEVID_AB, ids, ARRAY_SIZE(ids));
0792     if (ret < 0) {
0793         dev_err(dev, "Failed to read DEVID: %d\n", ret);
0794         goto fail_shutdown;
0795     }
0796 
0797     devid = (ids[0] << 16) | (ids[1] << 8) | ids[2];
0798     if (devid != CS4234_SUPPORTED_ID) {
0799         dev_err(dev, "Unknown device ID: %x\n", devid);
0800         ret = -EINVAL;
0801         goto fail_shutdown;
0802     }
0803 
0804     ret = regmap_read(cs4234->regmap, CS4234_REVID, &revid);
0805     if (ret < 0) {
0806         dev_err(dev, "Failed to read CS4234_REVID: %d\n", ret);
0807         goto fail_shutdown;
0808     }
0809 
0810     dev_info(dev, "Cirrus Logic CS4234, Alpha Rev: %02X, Numeric Rev: %02X\n",
0811          (revid & 0xF0) >> 4, revid & 0x0F);
0812 
0813     ret = regulator_get_voltage(cs4234->core_supplies[CS4234_SUPPLY_VA].consumer);
0814     switch (ret) {
0815     case 3135000 ... 3650000:
0816         regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
0817                    CS4234_VA_SEL_MASK,
0818                    CS4234_3V3 << CS4234_VA_SEL_SHIFT);
0819         break;
0820     case 4750000 ... 5250000:
0821         regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
0822                    CS4234_VA_SEL_MASK,
0823                    CS4234_5V << CS4234_VA_SEL_SHIFT);
0824         break;
0825     default:
0826         dev_err(dev, "Invalid VA voltage\n");
0827         ret = -EINVAL;
0828         goto fail_shutdown;
0829     }
0830 
0831     pm_runtime_set_active(&i2c_client->dev);
0832     pm_runtime_enable(&i2c_client->dev);
0833 
0834     memcpy(&cs4234->rate_dividers, &cs4234_dividers, sizeof(cs4234_dividers));
0835     cs4234->rate_constraint.rats = cs4234->rate_dividers;
0836 
0837     ret = snd_soc_register_component(dev, &soc_component_cs4234, cs4234_dai,
0838                      ARRAY_SIZE(cs4234_dai));
0839     if (ret < 0) {
0840         dev_err(dev, "Failed to register component:%d\n", ret);
0841         pm_runtime_disable(&i2c_client->dev);
0842         goto fail_shutdown;
0843     }
0844 
0845     return ret;
0846 
0847 fail_shutdown:
0848     cs4234_shutdown(cs4234);
0849 
0850     return ret;
0851 }
0852 
0853 static int cs4234_i2c_remove(struct i2c_client *i2c_client)
0854 {
0855     struct cs4234 *cs4234 = i2c_get_clientdata(i2c_client);
0856     struct device *dev = &i2c_client->dev;
0857 
0858     snd_soc_unregister_component(dev);
0859     pm_runtime_disable(dev);
0860     cs4234_shutdown(cs4234);
0861 
0862     return 0;
0863 }
0864 
0865 static int __maybe_unused cs4234_runtime_resume(struct device *dev)
0866 {
0867     struct cs4234 *cs4234 = dev_get_drvdata(dev);
0868     int ret;
0869 
0870     ret = cs4234_powerup(cs4234);
0871     if (ret)
0872         return ret;
0873 
0874     regcache_mark_dirty(cs4234->regmap);
0875     regcache_cache_only(cs4234->regmap, false);
0876     ret = regcache_sync(cs4234->regmap);
0877     if (ret) {
0878         dev_err(dev, "Failed to sync regmap: %d\n", ret);
0879         cs4234_shutdown(cs4234);
0880         return ret;
0881     }
0882 
0883     return 0;
0884 }
0885 
0886 static int __maybe_unused cs4234_runtime_suspend(struct device *dev)
0887 {
0888     struct cs4234 *cs4234 = dev_get_drvdata(dev);
0889 
0890     cs4234_shutdown(cs4234);
0891 
0892     return 0;
0893 }
0894 
0895 static const struct dev_pm_ops cs4234_pm = {
0896     SET_RUNTIME_PM_OPS(cs4234_runtime_suspend, cs4234_runtime_resume, NULL)
0897 };
0898 
0899 static const struct of_device_id cs4234_of_match[] = {
0900     { .compatible = "cirrus,cs4234", },
0901     { }
0902 };
0903 MODULE_DEVICE_TABLE(of, cs4234_of_match);
0904 
0905 static struct i2c_driver cs4234_i2c_driver = {
0906     .driver = {
0907         .name = "cs4234",
0908         .pm = &cs4234_pm,
0909         .of_match_table = cs4234_of_match,
0910     },
0911     .probe_new =    cs4234_i2c_probe,
0912     .remove =   cs4234_i2c_remove,
0913 };
0914 module_i2c_driver(cs4234_i2c_driver);
0915 
0916 MODULE_DESCRIPTION("ASoC Cirrus Logic CS4234 driver");
0917 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
0918 MODULE_LICENSE("GPL v2");
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