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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * cs35l45.h - CS35L45 ALSA SoC audio driver
0004  *
0005  * Copyright 2019-2022 Cirrus Logic, Inc.
0006  *
0007  * Author: James Schulman <james.schulman@cirrus.com>
0008  *
0009  */
0010 
0011 #ifndef CS35L45_H
0012 #define CS35L45_H
0013 
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 
0018 #define CS35L45_DEVID               0x00000000
0019 #define CS35L45_REVID               0x00000004
0020 #define CS35L45_RELID               0x0000000C
0021 #define CS35L45_OTPID               0x00000010
0022 #define CS35L45_SFT_RESET           0x00000020
0023 #define CS35L45_GLOBAL_ENABLES          0x00002014
0024 #define CS35L45_BLOCK_ENABLES           0x00002018
0025 #define CS35L45_BLOCK_ENABLES2          0x0000201C
0026 #define CS35L45_ERROR_RELEASE           0x00002034
0027 #define CS35L45_REFCLK_INPUT            0x00002C04
0028 #define CS35L45_GLOBAL_SAMPLE_RATE      0x00002C0C
0029 #define CS35L45_BOOST_CCM_CFG           0x00003808
0030 #define CS35L45_BOOST_DCM_CFG           0x0000380C
0031 #define CS35L45_BOOST_OV_CFG            0x0000382C
0032 #define CS35L45_ASP_ENABLES1            0x00004800
0033 #define CS35L45_ASP_CONTROL1            0x00004804
0034 #define CS35L45_ASP_CONTROL2            0x00004808
0035 #define CS35L45_ASP_CONTROL3            0x0000480C
0036 #define CS35L45_ASP_FRAME_CONTROL1      0x00004810
0037 #define CS35L45_ASP_FRAME_CONTROL2      0x00004814
0038 #define CS35L45_ASP_FRAME_CONTROL5      0x00004820
0039 #define CS35L45_ASP_DATA_CONTROL1       0x00004830
0040 #define CS35L45_ASP_DATA_CONTROL5       0x00004840
0041 #define CS35L45_DACPCM1_INPUT           0x00004C00
0042 #define CS35L45_ASPTX1_INPUT            0x00004C20
0043 #define CS35L45_ASPTX2_INPUT            0x00004C24
0044 #define CS35L45_ASPTX3_INPUT            0x00004C28
0045 #define CS35L45_ASPTX4_INPUT            0x00004C2C
0046 #define CS35L45_ASPTX5_INPUT            0x00004C30
0047 #define CS35L45_LDPM_CONFIG         0x00006404
0048 #define CS35L45_AMP_PCM_CONTROL         0x00007000
0049 #define CS35L45_AMP_PCM_HPF_TST         0x00007004
0050 #define CS35L45_IRQ1_EINT_4         0x0000E01C
0051 #define CS35L45_LASTREG             0x0000E01C
0052 
0053 /* SFT_RESET */
0054 #define CS35L45_SOFT_RESET_TRIGGER      0x5A000000
0055 
0056 /* GLOBAL_ENABLES */
0057 #define CS35L45_GLOBAL_EN_SHIFT         0
0058 #define CS35L45_GLOBAL_EN_MASK          BIT(0)
0059 
0060 /* BLOCK_ENABLES */
0061 #define CS35L45_IMON_EN_SHIFT           13
0062 #define CS35L45_VMON_EN_SHIFT           12
0063 #define CS35L45_VDD_BSTMON_EN_SHIFT     9
0064 #define CS35L45_VDD_BATTMON_EN_SHIFT        8
0065 #define CS35L45_BST_EN_SHIFT            4
0066 #define CS35L45_BST_EN_MASK         GENMASK(5, 4)
0067 
0068 #define CS35L45_BST_DISABLE_FET_ON              0x01
0069 
0070 /* BLOCK_ENABLES2 */
0071 #define CS35L45_ASP_EN_SHIFT            27
0072 
0073 /* ERROR_RELEASE */
0074 #define CS35L45_GLOBAL_ERR_RLS_MASK     BIT(11)
0075 
0076 /* REFCLK_INPUT */
0077 #define CS35L45_PLL_FORCE_EN_SHIFT      16
0078 #define CS35L45_PLL_FORCE_EN_MASK       BIT(16)
0079 #define CS35L45_PLL_OPEN_LOOP_SHIFT     11
0080 #define CS35L45_PLL_OPEN_LOOP_MASK      BIT(11)
0081 #define CS35L45_PLL_REFCLK_FREQ_SHIFT       5
0082 #define CS35L45_PLL_REFCLK_FREQ_MASK        GENMASK(10, 5)
0083 #define CS35L45_PLL_REFCLK_EN_SHIFT     4
0084 #define CS35L45_PLL_REFCLK_EN_MASK      BIT(4)
0085 #define CS35L45_PLL_REFCLK_SEL_SHIFT        0
0086 #define CS35L45_PLL_REFCLK_SEL_MASK     GENMASK(2, 0)
0087 
0088 #define CS35L45_PLL_REFCLK_SEL_BCLK     0x0
0089 
0090 /* GLOBAL_SAMPLE_RATE */
0091 #define CS35L45_GLOBAL_FS_SHIFT         0
0092 #define CS35L45_GLOBAL_FS_MASK          GENMASK(4, 0)
0093 
0094 #define CS35L45_48P0_KHZ            0x03
0095 #define CS35L45_96P0_KHZ            0x04
0096 #define CS35L45_44P100_KHZ          0x0B
0097 #define CS35L45_88P200_KHZ          0x0C
0098 
0099 /* ASP_ENABLES_1 */
0100 #define CS35L45_ASP_RX2_EN_SHIFT        17
0101 #define CS35L45_ASP_RX1_EN_SHIFT        16
0102 #define CS35L45_ASP_TX5_EN_SHIFT        4
0103 #define CS35L45_ASP_TX4_EN_SHIFT        3
0104 #define CS35L45_ASP_TX3_EN_SHIFT        2
0105 #define CS35L45_ASP_TX2_EN_SHIFT        1
0106 #define CS35L45_ASP_TX1_EN_SHIFT        0
0107 
0108 /* ASP_CONTROL2 */
0109 #define CS35L45_ASP_WIDTH_RX_SHIFT      24
0110 #define CS35L45_ASP_WIDTH_RX_MASK       GENMASK(31, 24)
0111 #define CS35L45_ASP_WIDTH_TX_SHIFT      16
0112 #define CS35L45_ASP_WIDTH_TX_MASK       GENMASK(23, 16)
0113 #define CS35L45_ASP_FMT_SHIFT           8
0114 #define CS35L45_ASP_FMT_MASK            GENMASK(10, 8)
0115 #define CS35L45_ASP_BCLK_INV_SHIFT      6
0116 #define CS35L45_ASP_BCLK_INV_MASK       BIT(6)
0117 #define CS35L45_ASP_FSYNC_INV_SHIFT     2
0118 #define CS35L45_ASP_FSYNC_INV_MASK      BIT(2)
0119 
0120 #define CS35l45_ASP_FMT_DSP_A           0
0121 #define CS35L45_ASP_FMT_I2S         2
0122 
0123 /* ASP_CONTROL3 */
0124 #define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT     0
0125 #define CS35L45_ASP_DOUT_HIZ_CTRL_MASK      GENMASK(1, 0)
0126 
0127 /* ASP_FRAME_CONTROL1 */
0128 #define CS35L45_ASP_TX4_SLOT_SHIFT      24
0129 #define CS35L45_ASP_TX4_SLOT_MASK       GENMASK(29, 24)
0130 #define CS35L45_ASP_TX3_SLOT_SHIFT      16
0131 #define CS35L45_ASP_TX3_SLOT_MASK       GENMASK(21, 16)
0132 #define CS35L45_ASP_TX2_SLOT_SHIFT      8
0133 #define CS35L45_ASP_TX2_SLOT_MASK       GENMASK(13, 8)
0134 #define CS35L45_ASP_TX1_SLOT_SHIFT      0
0135 #define CS35L45_ASP_TX1_SLOT_MASK       GENMASK(5, 0)
0136 
0137 #define CS35L45_ASP_TX_ALL_SLOTS        (CS35L45_ASP_TX4_SLOT_MASK | \
0138                         CS35L45_ASP_TX3_SLOT_MASK  | \
0139                         CS35L45_ASP_TX2_SLOT_MASK  | \
0140                         CS35L45_ASP_TX1_SLOT_MASK)
0141 /* ASP_FRAME_CONTROL5 */
0142 #define CS35L45_ASP_RX2_SLOT_SHIFT      8
0143 #define CS35L45_ASP_RX2_SLOT_MASK       GENMASK(13, 8)
0144 #define CS35L45_ASP_RX1_SLOT_SHIFT      0
0145 #define CS35L45_ASP_RX1_SLOT_MASK       GENMASK(5, 0)
0146 
0147 #define CS35L45_ASP_RX_ALL_SLOTS        (CS35L45_ASP_RX2_SLOT_MASK | \
0148                         CS35L45_ASP_RX1_SLOT_MASK)
0149 
0150 /* ASP_DATA_CONTROL1 */
0151 /* ASP_DATA_CONTROL5 */
0152 #define CS35L45_ASP_WL_SHIFT            0
0153 #define CS35L45_ASP_WL_MASK         GENMASK(5, 0)
0154 
0155 /* AMP_PCM_CONTROL */
0156 #define CS35L45_AMP_VOL_PCM_SHIFT       0
0157 #define CS35L45_AMP_VOL_PCM_WIDTH       11
0158 
0159 /* AMP_PCM_HPF_TST */
0160 #define CS35l45_HPF_DEFAULT         0x00000000
0161 #define CS35L45_HPF_44P1            0x000108BD
0162 #define CS35L45_HPF_88P2            0x0001045F
0163 
0164 /* IRQ1_EINT_4 */
0165 #define CS35L45_OTP_BOOT_DONE_STS_MASK      BIT(1)
0166 #define CS35L45_OTP_BUSY_MASK           BIT(0)
0167 
0168 /* Mixer sources */
0169 #define CS35L45_PCM_SRC_MASK            0x7F
0170 #define CS35L45_PCM_SRC_ZERO            0x00
0171 #define CS35L45_PCM_SRC_ASP_RX1         0x08
0172 #define CS35L45_PCM_SRC_ASP_RX2         0x09
0173 #define CS35L45_PCM_SRC_VMON            0x18
0174 #define CS35L45_PCM_SRC_IMON            0x19
0175 #define CS35L45_PCM_SRC_ERR_VOL         0x20
0176 #define CS35L45_PCM_SRC_CLASSH_TGT      0x21
0177 #define CS35L45_PCM_SRC_VDD_BATTMON     0x28
0178 #define CS35L45_PCM_SRC_VDD_BSTMON      0x29
0179 #define CS35L45_PCM_SRC_TEMPMON         0x3A
0180 #define CS35L45_PCM_SRC_INTERPOLATOR        0x40
0181 #define CS35L45_PCM_SRC_IL_TARGET       0x48
0182 
0183 #define CS35L45_RESET_HOLD_US           2000
0184 #define CS35L45_RESET_US            2000
0185 #define CS35L45_POST_GLOBAL_EN_US       5000
0186 #define CS35L45_PRE_GLOBAL_DIS_US       3000
0187 
0188 #define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
0189              SNDRV_PCM_FMTBIT_S24_3LE| \
0190              SNDRV_PCM_FMTBIT_S24_LE)
0191 
0192 #define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \
0193                SNDRV_PCM_RATE_48000 | \
0194                SNDRV_PCM_RATE_88200 | \
0195                SNDRV_PCM_RATE_96000)
0196 
0197 struct cs35l45_private {
0198     struct device *dev;
0199     struct regmap *regmap;
0200     struct gpio_desc *reset_gpio;
0201     struct regulator *vdd_batt;
0202     struct regulator *vdd_a;
0203     bool initialized;
0204     bool sysclk_set;
0205     u8 slot_width;
0206     u8 slot_count;
0207 };
0208 
0209 extern const struct dev_pm_ops cs35l45_pm_ops;
0210 extern const struct regmap_config cs35l45_i2c_regmap;
0211 extern const struct regmap_config cs35l45_spi_regmap;
0212 int cs35l45_apply_patch(struct cs35l45_private *cs35l45);
0213 unsigned int cs35l45_get_clk_freq_id(unsigned int freq);
0214 int cs35l45_probe(struct cs35l45_private *cs35l45);
0215 void cs35l45_remove(struct cs35l45_private *cs35l45);
0216 
0217 #endif /* CS35L45_H */
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