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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // cs35l36.c -- CS35L36 ALSA SoC audio driver
0004 //
0005 // Copyright 2018 Cirrus Logic, Inc.
0006 //
0007 // Author: James Schulman <james.schulman@cirrus.com>
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/i2c.h>
0015 #include <linux/slab.h>
0016 #include <linux/workqueue.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <linux/of_device.h>
0021 #include <linux/of_gpio.h>
0022 #include <linux/regmap.h>
0023 #include <sound/core.h>
0024 #include <sound/pcm.h>
0025 #include <sound/pcm_params.h>
0026 #include <sound/soc.h>
0027 #include <sound/soc-dapm.h>
0028 #include <linux/gpio.h>
0029 #include <sound/initval.h>
0030 #include <sound/tlv.h>
0031 #include <sound/cs35l36.h>
0032 #include <linux/of_irq.h>
0033 #include <linux/completion.h>
0034 
0035 #include "cs35l36.h"
0036 
0037 /*
0038  * Some fields take zero as a valid value so use a high bit flag that won't
0039  * get written to the device to mark those.
0040  */
0041 #define CS35L36_VALID_PDATA 0x80000000
0042 
0043 static const char * const cs35l36_supplies[] = {
0044     "VA",
0045     "VP",
0046 };
0047 
0048 struct  cs35l36_private {
0049     struct device *dev;
0050     struct cs35l36_platform_data pdata;
0051     struct regmap *regmap;
0052     struct regulator_bulk_data supplies[2];
0053     int num_supplies;
0054     int clksrc;
0055     int chip_version;
0056     int rev_id;
0057     int ldm_mode_sel;
0058     struct gpio_desc *reset_gpio;
0059 };
0060 
0061 struct cs35l36_pll_config {
0062     int freq;
0063     int clk_cfg;
0064     int fll_igain;
0065 };
0066 
0067 static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
0068     {32768,     0x00, 0x05},
0069     {8000,      0x01, 0x03},
0070     {11025,     0x02, 0x03},
0071     {12000,     0x03, 0x03},
0072     {16000,     0x04, 0x04},
0073     {22050,     0x05, 0x04},
0074     {24000,     0x06, 0x04},
0075     {32000,     0x07, 0x05},
0076     {44100,     0x08, 0x05},
0077     {48000,     0x09, 0x05},
0078     {88200,     0x0A, 0x06},
0079     {96000,     0x0B, 0x06},
0080     {128000,    0x0C, 0x07},
0081     {176400,    0x0D, 0x07},
0082     {192000,    0x0E, 0x07},
0083     {256000,    0x0F, 0x08},
0084     {352800,    0x10, 0x08},
0085     {384000,    0x11, 0x08},
0086     {512000,    0x12, 0x09},
0087     {705600,    0x13, 0x09},
0088     {750000,    0x14, 0x09},
0089     {768000,    0x15, 0x09},
0090     {1000000,   0x16, 0x0A},
0091     {1024000,   0x17, 0x0A},
0092     {1200000,   0x18, 0x0A},
0093     {1411200,   0x19, 0x0A},
0094     {1500000,   0x1A, 0x0A},
0095     {1536000,   0x1B, 0x0A},
0096     {2000000,   0x1C, 0x0A},
0097     {2048000,   0x1D, 0x0A},
0098     {2400000,   0x1E, 0x0A},
0099     {2822400,   0x1F, 0x0A},
0100     {3000000,   0x20, 0x0A},
0101     {3072000,   0x21, 0x0A},
0102     {3200000,   0x22, 0x0A},
0103     {4000000,   0x23, 0x0A},
0104     {4096000,   0x24, 0x0A},
0105     {4800000,   0x25, 0x0A},
0106     {5644800,   0x26, 0x0A},
0107     {6000000,   0x27, 0x0A},
0108     {6144000,   0x28, 0x0A},
0109     {6250000,   0x29, 0x08},
0110     {6400000,   0x2A, 0x0A},
0111     {6500000,   0x2B, 0x08},
0112     {6750000,   0x2C, 0x09},
0113     {7526400,   0x2D, 0x0A},
0114     {8000000,   0x2E, 0x0A},
0115     {8192000,   0x2F, 0x0A},
0116     {9600000,   0x30, 0x0A},
0117     {11289600,  0x31, 0x0A},
0118     {12000000,  0x32, 0x0A},
0119     {12288000,  0x33, 0x0A},
0120     {12500000,  0x34, 0x08},
0121     {12800000,  0x35, 0x0A},
0122     {13000000,  0x36, 0x0A},
0123     {13500000,  0x37, 0x0A},
0124     {19200000,  0x38, 0x0A},
0125     {22579200,  0x39, 0x0A},
0126     {24000000,  0x3A, 0x0A},
0127     {24576000,  0x3B, 0x0A},
0128     {25000000,  0x3C, 0x0A},
0129     {25600000,  0x3D, 0x0A},
0130     {26000000,  0x3E, 0x0A},
0131     {27000000,  0x3F, 0x0A},
0132 };
0133 
0134 static struct reg_default cs35l36_reg[] = {
0135     {CS35L36_TESTKEY_CTRL,          0x00000000},
0136     {CS35L36_USERKEY_CTL,           0x00000000},
0137     {CS35L36_OTP_CTRL1,         0x00002460},
0138     {CS35L36_OTP_CTRL2,         0x00000000},
0139     {CS35L36_OTP_CTRL3,         0x00000000},
0140     {CS35L36_OTP_CTRL4,         0x00000000},
0141     {CS35L36_OTP_CTRL5,         0x00000000},
0142     {CS35L36_PAC_CTL1,          0x00000004},
0143     {CS35L36_PAC_CTL2,          0x00000000},
0144     {CS35L36_PAC_CTL3,          0x00000000},
0145     {CS35L36_PWR_CTRL1,         0x00000000},
0146     {CS35L36_PWR_CTRL2,         0x00003321},
0147     {CS35L36_PWR_CTRL3,         0x01000010},
0148     {CS35L36_CTRL_OVRRIDE,          0x00000002},
0149     {CS35L36_AMP_OUT_MUTE,          0x00000000},
0150     {CS35L36_OTP_TRIM_STATUS,       0x00000000},
0151     {CS35L36_DISCH_FILT,            0x00000000},
0152     {CS35L36_PROTECT_REL_ERR,       0x00000000},
0153     {CS35L36_PAD_INTERFACE,         0x00000038},
0154     {CS35L36_PLL_CLK_CTRL,          0x00000010},
0155     {CS35L36_GLOBAL_CLK_CTRL,       0x00000003},
0156     {CS35L36_ADC_CLK_CTRL,          0x00000000},
0157     {CS35L36_SWIRE_CLK_CTRL,        0x00000000},
0158     {CS35L36_SP_SCLK_CLK_CTRL,      0x00000000},
0159     {CS35L36_MDSYNC_EN,         0x00000000},
0160     {CS35L36_MDSYNC_TX_ID,          0x00000000},
0161     {CS35L36_MDSYNC_PWR_CTRL,       0x00000000},
0162     {CS35L36_MDSYNC_DATA_TX,        0x00000000},
0163     {CS35L36_MDSYNC_TX_STATUS,      0x00000002},
0164     {CS35L36_MDSYNC_RX_STATUS,      0x00000000},
0165     {CS35L36_MDSYNC_ERR_STATUS,     0x00000000},
0166     {CS35L36_BSTCVRT_VCTRL1,        0x00000000},
0167     {CS35L36_BSTCVRT_VCTRL2,        0x00000001},
0168     {CS35L36_BSTCVRT_PEAK_CUR,      0x0000004A},
0169     {CS35L36_BSTCVRT_SFT_RAMP,      0x00000003},
0170     {CS35L36_BSTCVRT_COEFF,         0x00002424},
0171     {CS35L36_BSTCVRT_SLOPE_LBST,        0x00005800},
0172     {CS35L36_BSTCVRT_SW_FREQ,       0x00010000},
0173     {CS35L36_BSTCVRT_DCM_CTRL,      0x00002001},
0174     {CS35L36_BSTCVRT_DCM_MODE_FORCE,    0x00000000},
0175     {CS35L36_BSTCVRT_OVERVOLT_CTRL,     0x00000130},
0176     {CS35L36_VPI_LIMIT_MODE,        0x00000000},
0177     {CS35L36_VPI_LIMIT_MINMAX,      0x00003000},
0178     {CS35L36_VPI_VP_THLD,           0x00101010},
0179     {CS35L36_VPI_TRACK_CTRL,        0x00000000},
0180     {CS35L36_VPI_TRIG_MODE_CTRL,        0x00000000},
0181     {CS35L36_VPI_TRIG_STEPS,        0x00000000},
0182     {CS35L36_VI_SPKMON_FILT,        0x00000003},
0183     {CS35L36_VI_SPKMON_GAIN,        0x00000909},
0184     {CS35L36_VI_SPKMON_IP_SEL,      0x00000000},
0185     {CS35L36_DTEMP_WARN_THLD,       0x00000002},
0186     {CS35L36_DTEMP_STATUS,          0x00000000},
0187     {CS35L36_VPVBST_FS_SEL,         0x00000001},
0188     {CS35L36_VPVBST_VP_CTRL,        0x000001C0},
0189     {CS35L36_VPVBST_VBST_CTRL,      0x000001C0},
0190     {CS35L36_ASP_TX_PIN_CTRL,       0x00000028},
0191     {CS35L36_ASP_RATE_CTRL,         0x00090000},
0192     {CS35L36_ASP_FORMAT,            0x00000002},
0193     {CS35L36_ASP_FRAME_CTRL,        0x00180018},
0194     {CS35L36_ASP_TX1_TX2_SLOT,      0x00010000},
0195     {CS35L36_ASP_TX3_TX4_SLOT,      0x00030002},
0196     {CS35L36_ASP_TX5_TX6_SLOT,      0x00050004},
0197     {CS35L36_ASP_TX7_TX8_SLOT,      0x00070006},
0198     {CS35L36_ASP_RX1_SLOT,          0x00000000},
0199     {CS35L36_ASP_RX_TX_EN,          0x00000000},
0200     {CS35L36_ASP_RX1_SEL,           0x00000008},
0201     {CS35L36_ASP_TX1_SEL,           0x00000018},
0202     {CS35L36_ASP_TX2_SEL,           0x00000019},
0203     {CS35L36_ASP_TX3_SEL,           0x00000028},
0204     {CS35L36_ASP_TX4_SEL,           0x00000029},
0205     {CS35L36_ASP_TX5_SEL,           0x00000020},
0206     {CS35L36_ASP_TX6_SEL,           0x00000000},
0207     {CS35L36_SWIRE_P1_TX1_SEL,      0x00000018},
0208     {CS35L36_SWIRE_P1_TX2_SEL,      0x00000019},
0209     {CS35L36_SWIRE_P2_TX1_SEL,      0x00000028},
0210     {CS35L36_SWIRE_P2_TX2_SEL,      0x00000029},
0211     {CS35L36_SWIRE_P2_TX3_SEL,      0x00000020},
0212     {CS35L36_SWIRE_DP1_FIFO_CFG,        0x0000001B},
0213     {CS35L36_SWIRE_DP2_FIFO_CFG,        0x0000001B},
0214     {CS35L36_SWIRE_DP3_FIFO_CFG,        0x0000001B},
0215     {CS35L36_SWIRE_PCM_RX_DATA,     0x00000000},
0216     {CS35L36_SWIRE_FS_SEL,          0x00000001},
0217     {CS35L36_AMP_DIG_VOL_CTRL,      0x00008000},
0218     {CS35L36_VPBR_CFG,          0x02AA1905},
0219     {CS35L36_VBBR_CFG,          0x02AA1905},
0220     {CS35L36_VPBR_STATUS,           0x00000000},
0221     {CS35L36_VBBR_STATUS,           0x00000000},
0222     {CS35L36_OVERTEMP_CFG,          0x00000001},
0223     {CS35L36_AMP_ERR_VOL,           0x00000000},
0224     {CS35L36_CLASSH_CFG,            0x000B0405},
0225     {CS35L36_CLASSH_FET_DRV_CFG,        0x00000111},
0226     {CS35L36_NG_CFG,            0x00000033},
0227     {CS35L36_AMP_GAIN_CTRL,         0x00000273},
0228     {CS35L36_PWM_MOD_IO_CTRL,       0x00000000},
0229     {CS35L36_PWM_MOD_STATUS,        0x00000000},
0230     {CS35L36_DAC_MSM_CFG,           0x00000000},
0231     {CS35L36_AMP_SLOPE_CTRL,        0x00000B00},
0232     {CS35L36_AMP_PDM_VOLUME,        0x00000000},
0233     {CS35L36_AMP_PDM_RATE_CTRL,     0x00000000},
0234     {CS35L36_PDM_CH_SEL,            0x00000000},
0235     {CS35L36_AMP_NG_CTRL,           0x0000212F},
0236     {CS35L36_PDM_HIGHFILT_CTRL,     0x00000000},
0237     {CS35L36_PAC_INT0_CTRL,         0x00000001},
0238     {CS35L36_PAC_INT1_CTRL,         0x00000001},
0239     {CS35L36_PAC_INT2_CTRL,         0x00000001},
0240     {CS35L36_PAC_INT3_CTRL,         0x00000001},
0241     {CS35L36_PAC_INT4_CTRL,         0x00000001},
0242     {CS35L36_PAC_INT5_CTRL,         0x00000001},
0243     {CS35L36_PAC_INT6_CTRL,         0x00000001},
0244     {CS35L36_PAC_INT7_CTRL,         0x00000001},
0245 };
0246 
0247 static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
0248 {
0249     switch (reg) {
0250     case CS35L36_SW_RESET:
0251     case CS35L36_SW_REV:
0252     case CS35L36_HW_REV:
0253     case CS35L36_TESTKEY_CTRL:
0254     case CS35L36_USERKEY_CTL:
0255     case CS35L36_OTP_MEM30:
0256     case CS35L36_OTP_CTRL1:
0257     case CS35L36_OTP_CTRL2:
0258     case CS35L36_OTP_CTRL3:
0259     case CS35L36_OTP_CTRL4:
0260     case CS35L36_OTP_CTRL5:
0261     case CS35L36_PAC_CTL1:
0262     case CS35L36_PAC_CTL2:
0263     case CS35L36_PAC_CTL3:
0264     case CS35L36_DEVICE_ID:
0265     case CS35L36_FAB_ID:
0266     case CS35L36_REV_ID:
0267     case CS35L36_PWR_CTRL1:
0268     case CS35L36_PWR_CTRL2:
0269     case CS35L36_PWR_CTRL3:
0270     case CS35L36_CTRL_OVRRIDE:
0271     case CS35L36_AMP_OUT_MUTE:
0272     case CS35L36_OTP_TRIM_STATUS:
0273     case CS35L36_DISCH_FILT:
0274     case CS35L36_PROTECT_REL_ERR:
0275     case CS35L36_PAD_INTERFACE:
0276     case CS35L36_PLL_CLK_CTRL:
0277     case CS35L36_GLOBAL_CLK_CTRL:
0278     case CS35L36_ADC_CLK_CTRL:
0279     case CS35L36_SWIRE_CLK_CTRL:
0280     case CS35L36_SP_SCLK_CLK_CTRL:
0281     case CS35L36_TST_FS_MON0:
0282     case CS35L36_MDSYNC_EN:
0283     case CS35L36_MDSYNC_TX_ID:
0284     case CS35L36_MDSYNC_PWR_CTRL:
0285     case CS35L36_MDSYNC_DATA_TX:
0286     case CS35L36_MDSYNC_TX_STATUS:
0287     case CS35L36_MDSYNC_RX_STATUS:
0288     case CS35L36_MDSYNC_ERR_STATUS:
0289     case CS35L36_BSTCVRT_VCTRL1:
0290     case CS35L36_BSTCVRT_VCTRL2:
0291     case CS35L36_BSTCVRT_PEAK_CUR:
0292     case CS35L36_BSTCVRT_SFT_RAMP:
0293     case CS35L36_BSTCVRT_COEFF:
0294     case CS35L36_BSTCVRT_SLOPE_LBST:
0295     case CS35L36_BSTCVRT_SW_FREQ:
0296     case CS35L36_BSTCVRT_DCM_CTRL:
0297     case CS35L36_BSTCVRT_DCM_MODE_FORCE:
0298     case CS35L36_BSTCVRT_OVERVOLT_CTRL:
0299     case CS35L36_BST_TST_MANUAL:
0300     case CS35L36_BST_ANA2_TEST:
0301     case CS35L36_VPI_LIMIT_MODE:
0302     case CS35L36_VPI_LIMIT_MINMAX:
0303     case CS35L36_VPI_VP_THLD:
0304     case CS35L36_VPI_TRACK_CTRL:
0305     case CS35L36_VPI_TRIG_MODE_CTRL:
0306     case CS35L36_VPI_TRIG_STEPS:
0307     case CS35L36_VI_SPKMON_FILT:
0308     case CS35L36_VI_SPKMON_GAIN:
0309     case CS35L36_VI_SPKMON_IP_SEL:
0310     case CS35L36_DTEMP_WARN_THLD:
0311     case CS35L36_DTEMP_STATUS:
0312     case CS35L36_VPVBST_FS_SEL:
0313     case CS35L36_VPVBST_VP_CTRL:
0314     case CS35L36_VPVBST_VBST_CTRL:
0315     case CS35L36_ASP_TX_PIN_CTRL:
0316     case CS35L36_ASP_RATE_CTRL:
0317     case CS35L36_ASP_FORMAT:
0318     case CS35L36_ASP_FRAME_CTRL:
0319     case CS35L36_ASP_TX1_TX2_SLOT:
0320     case CS35L36_ASP_TX3_TX4_SLOT:
0321     case CS35L36_ASP_TX5_TX6_SLOT:
0322     case CS35L36_ASP_TX7_TX8_SLOT:
0323     case CS35L36_ASP_RX1_SLOT:
0324     case CS35L36_ASP_RX_TX_EN:
0325     case CS35L36_ASP_RX1_SEL:
0326     case CS35L36_ASP_TX1_SEL:
0327     case CS35L36_ASP_TX2_SEL:
0328     case CS35L36_ASP_TX3_SEL:
0329     case CS35L36_ASP_TX4_SEL:
0330     case CS35L36_ASP_TX5_SEL:
0331     case CS35L36_ASP_TX6_SEL:
0332     case CS35L36_SWIRE_P1_TX1_SEL:
0333     case CS35L36_SWIRE_P1_TX2_SEL:
0334     case CS35L36_SWIRE_P2_TX1_SEL:
0335     case CS35L36_SWIRE_P2_TX2_SEL:
0336     case CS35L36_SWIRE_P2_TX3_SEL:
0337     case CS35L36_SWIRE_DP1_FIFO_CFG:
0338     case CS35L36_SWIRE_DP2_FIFO_CFG:
0339     case CS35L36_SWIRE_DP3_FIFO_CFG:
0340     case CS35L36_SWIRE_PCM_RX_DATA:
0341     case CS35L36_SWIRE_FS_SEL:
0342     case CS35L36_AMP_DIG_VOL_CTRL:
0343     case CS35L36_VPBR_CFG:
0344     case CS35L36_VBBR_CFG:
0345     case CS35L36_VPBR_STATUS:
0346     case CS35L36_VBBR_STATUS:
0347     case CS35L36_OVERTEMP_CFG:
0348     case CS35L36_AMP_ERR_VOL:
0349     case CS35L36_CLASSH_CFG:
0350     case CS35L36_CLASSH_FET_DRV_CFG:
0351     case CS35L36_NG_CFG:
0352     case CS35L36_AMP_GAIN_CTRL:
0353     case CS35L36_PWM_MOD_IO_CTRL:
0354     case CS35L36_PWM_MOD_STATUS:
0355     case CS35L36_DAC_MSM_CFG:
0356     case CS35L36_AMP_SLOPE_CTRL:
0357     case CS35L36_AMP_PDM_VOLUME:
0358     case CS35L36_AMP_PDM_RATE_CTRL:
0359     case CS35L36_PDM_CH_SEL:
0360     case CS35L36_AMP_NG_CTRL:
0361     case CS35L36_PDM_HIGHFILT_CTRL:
0362     case CS35L36_INT1_STATUS:
0363     case CS35L36_INT2_STATUS:
0364     case CS35L36_INT3_STATUS:
0365     case CS35L36_INT4_STATUS:
0366     case CS35L36_INT1_RAW_STATUS:
0367     case CS35L36_INT2_RAW_STATUS:
0368     case CS35L36_INT3_RAW_STATUS:
0369     case CS35L36_INT4_RAW_STATUS:
0370     case CS35L36_INT1_MASK:
0371     case CS35L36_INT2_MASK:
0372     case CS35L36_INT3_MASK:
0373     case CS35L36_INT4_MASK:
0374     case CS35L36_INT1_EDGE_LVL_CTRL:
0375     case CS35L36_INT3_EDGE_LVL_CTRL:
0376     case CS35L36_PAC_INT_STATUS:
0377     case CS35L36_PAC_INT_RAW_STATUS:
0378     case CS35L36_PAC_INT_FLUSH_CTRL:
0379     case CS35L36_PAC_INT0_CTRL:
0380     case CS35L36_PAC_INT1_CTRL:
0381     case CS35L36_PAC_INT2_CTRL:
0382     case CS35L36_PAC_INT3_CTRL:
0383     case CS35L36_PAC_INT4_CTRL:
0384     case CS35L36_PAC_INT5_CTRL:
0385     case CS35L36_PAC_INT6_CTRL:
0386     case CS35L36_PAC_INT7_CTRL:
0387         return true;
0388     default:
0389         if (reg >= CS35L36_PAC_PMEM_WORD0 &&
0390             reg <= CS35L36_PAC_PMEM_WORD1023)
0391             return true;
0392         else
0393             return false;
0394     }
0395 }
0396 
0397 static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
0398 {
0399     switch (reg) {
0400     case CS35L36_TESTKEY_CTRL:
0401     case CS35L36_USERKEY_CTL:
0402     case CS35L36_TST_FS_MON0:
0403         return true;
0404     default:
0405         return false;
0406     }
0407 }
0408 
0409 static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
0410 {
0411     switch (reg) {
0412     case CS35L36_SW_RESET:
0413     case CS35L36_SW_REV:
0414     case CS35L36_HW_REV:
0415     case CS35L36_TESTKEY_CTRL:
0416     case CS35L36_USERKEY_CTL:
0417     case CS35L36_DEVICE_ID:
0418     case CS35L36_FAB_ID:
0419     case CS35L36_REV_ID:
0420     case CS35L36_INT1_STATUS:
0421     case CS35L36_INT2_STATUS:
0422     case CS35L36_INT3_STATUS:
0423     case CS35L36_INT4_STATUS:
0424     case CS35L36_INT1_RAW_STATUS:
0425     case CS35L36_INT2_RAW_STATUS:
0426     case CS35L36_INT3_RAW_STATUS:
0427     case CS35L36_INT4_RAW_STATUS:
0428     case CS35L36_INT1_MASK:
0429     case CS35L36_INT2_MASK:
0430     case CS35L36_INT3_MASK:
0431     case CS35L36_INT4_MASK:
0432     case CS35L36_INT1_EDGE_LVL_CTRL:
0433     case CS35L36_INT3_EDGE_LVL_CTRL:
0434     case CS35L36_PAC_INT_STATUS:
0435     case CS35L36_PAC_INT_RAW_STATUS:
0436     case CS35L36_PAC_INT_FLUSH_CTRL:
0437         return true;
0438     default:
0439         if (reg >= CS35L36_PAC_PMEM_WORD0 &&
0440             reg <= CS35L36_PAC_PMEM_WORD1023)
0441             return true;
0442         else
0443             return false;
0444     }
0445 }
0446 
0447 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 912,
0448                   TLV_DB_MINMAX_ITEM(-10200, 1200));
0449 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
0450 
0451 static const char * const cs35l36_pcm_sftramp_text[] =  {
0452     "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
0453 
0454 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
0455                 cs35l36_pcm_sftramp_text);
0456 
0457 static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
0458                    struct snd_ctl_elem_value *ucontrol)
0459 {
0460     struct snd_soc_component *component =
0461             snd_soc_kcontrol_component(kcontrol);
0462     struct cs35l36_private *cs35l36 =
0463             snd_soc_component_get_drvdata(component);
0464 
0465     ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
0466 
0467     return 0;
0468 }
0469 
0470 static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
0471                    struct snd_ctl_elem_value *ucontrol)
0472 {
0473     struct snd_soc_component *component =
0474             snd_soc_kcontrol_component(kcontrol);
0475     struct cs35l36_private *cs35l36 =
0476             snd_soc_component_get_drvdata(component);
0477     int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
0478                                0;
0479 
0480     cs35l36->ldm_mode_sel = val;
0481 
0482     regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
0483                CS35L36_NG_AMP_EN_MASK, val);
0484 
0485     return 0;
0486 }
0487 
0488 static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
0489     SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
0490         3, 0x4D0, 0x390, dig_vol_tlv),
0491     SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
0492         amp_gain_tlv),
0493     SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
0494     SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
0495         CS35L36_AMP_ZC_SHIFT, 1, 0),
0496     SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
0497         CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
0498     SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
0499         CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
0500     SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
0501         cs35l36_ldm_sel_put),
0502 };
0503 
0504 static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
0505                   struct snd_kcontrol *kcontrol, int event)
0506 {
0507     struct snd_soc_component *component =
0508             snd_soc_dapm_to_component(w->dapm);
0509     struct cs35l36_private *cs35l36 =
0510             snd_soc_component_get_drvdata(component);
0511     u32 reg;
0512 
0513     switch (event) {
0514     case SND_SOC_DAPM_POST_PMU:
0515         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
0516                    CS35L36_GLOBAL_EN_MASK,
0517                    1 << CS35L36_GLOBAL_EN_SHIFT);
0518 
0519         usleep_range(2000, 2100);
0520 
0521         regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, &reg);
0522 
0523         if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
0524             dev_crit(cs35l36->dev, "PLL Unlocked\n");
0525 
0526         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
0527                    CS35L36_PCM_RX_SEL_MASK,
0528                    CS35L36_PCM_RX_SEL_PCM);
0529         regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
0530                    CS35L36_AMP_MUTE_MASK,
0531                    0 << CS35L36_AMP_MUTE_SHIFT);
0532         break;
0533     case SND_SOC_DAPM_PRE_PMD:
0534         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
0535                    CS35L36_PCM_RX_SEL_MASK,
0536                    CS35L36_PCM_RX_SEL_ZERO);
0537         regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
0538                    CS35L36_AMP_MUTE_MASK,
0539                    1 << CS35L36_AMP_MUTE_SHIFT);
0540         break;
0541     case SND_SOC_DAPM_POST_PMD:
0542         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
0543                    CS35L36_GLOBAL_EN_MASK,
0544                    0 << CS35L36_GLOBAL_EN_SHIFT);
0545 
0546         usleep_range(2000, 2100);
0547         break;
0548     default:
0549         dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
0550         return -EINVAL;
0551     }
0552 
0553     return 0;
0554 }
0555 
0556 static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
0557                    struct snd_kcontrol *kcontrol, int event)
0558 {
0559     struct snd_soc_component *component =
0560             snd_soc_dapm_to_component(w->dapm);
0561     struct cs35l36_private *cs35l36 =
0562             snd_soc_component_get_drvdata(component);
0563 
0564     switch (event) {
0565     case SND_SOC_DAPM_POST_PMU:
0566         if (!cs35l36->pdata.extern_boost)
0567             regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
0568                        CS35L36_BST_EN_MASK,
0569                        CS35L36_BST_EN <<
0570                        CS35L36_BST_EN_SHIFT);
0571         break;
0572     case SND_SOC_DAPM_POST_PMD:
0573         if (!cs35l36->pdata.extern_boost)
0574             regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
0575                        CS35L36_BST_EN_MASK,
0576                        CS35L36_BST_DIS_VP <<
0577                        CS35L36_BST_EN_SHIFT);
0578         break;
0579     default:
0580         dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
0581         return -EINVAL;
0582     }
0583 
0584     return 0;
0585 }
0586 
0587 static const char * const cs35l36_chan_text[] = {
0588     "RX1",
0589     "RX2",
0590 };
0591 
0592 static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
0593                 cs35l36_chan_text);
0594 
0595 static const struct snd_kcontrol_new cs35l36_chan_mux =
0596         SOC_DAPM_ENUM("Input Mux", chansel_enum);
0597 
0598 static const struct snd_kcontrol_new amp_enable_ctrl =
0599         SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
0600                         CS35L36_AMP_MUTE_SHIFT, 1, 1);
0601 
0602 static const struct snd_kcontrol_new boost_ctrl =
0603         SOC_DAPM_SINGLE_VIRT("Switch", 1);
0604 
0605 static const char * const asp_tx_src_text[] = {
0606     "Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
0607 };
0608 
0609 static const unsigned int asp_tx_src_values[] = {
0610     0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
0611 };
0612 
0613 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
0614                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0615                   asp_tx_src_values);
0616 
0617 static const struct snd_kcontrol_new asp_tx1_src =
0618         SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
0619 
0620 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
0621                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0622                   asp_tx_src_values);
0623 
0624 static const struct snd_kcontrol_new asp_tx2_src =
0625         SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
0626 
0627 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
0628                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0629                   asp_tx_src_values);
0630 
0631 static const struct snd_kcontrol_new asp_tx3_src =
0632         SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
0633 
0634 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
0635                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0636                   asp_tx_src_values);
0637 
0638 static const struct snd_kcontrol_new asp_tx4_src =
0639         SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
0640 
0641 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
0642                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0643                   asp_tx_src_values);
0644 
0645 static const struct snd_kcontrol_new asp_tx5_src =
0646         SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
0647 
0648 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
0649                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
0650                   asp_tx_src_values);
0651 
0652 static const struct snd_kcontrol_new asp_tx6_src =
0653         SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
0654 
0655 static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
0656     SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
0657     SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
0658 
0659     SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
0660                    cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
0661                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0662 
0663     SND_SOC_DAPM_OUTPUT("SPK"),
0664     SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &amp_enable_ctrl),
0665     SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
0666     SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
0667                   cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
0668                   SND_SOC_DAPM_POST_PMU),
0669 
0670     SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
0671     SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
0672     SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
0673     SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
0674     SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
0675     SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
0676 
0677     SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
0678     SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
0679     SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
0680     SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
0681     SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
0682     SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
0683 
0684     SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
0685     SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
0686     SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
0687     SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
0688 
0689     SND_SOC_DAPM_INPUT("VP"),
0690     SND_SOC_DAPM_INPUT("VBST"),
0691     SND_SOC_DAPM_INPUT("VSENSE"),
0692 };
0693 
0694 static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
0695     {"VPMON ADC", NULL, "VP"},
0696     {"VBSTMON ADC", NULL, "VBST"},
0697     {"IMON ADC", NULL, "VSENSE"},
0698     {"VMON ADC", NULL, "VSENSE"},
0699 
0700     {"ASPTX1SRC", "IMON", "IMON ADC"},
0701     {"ASPTX1SRC", "VMON", "VMON ADC"},
0702     {"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
0703     {"ASPTX1SRC", "VPMON", "VPMON ADC"},
0704 
0705     {"ASPTX2SRC", "IMON", "IMON ADC"},
0706     {"ASPTX2SRC", "VMON", "VMON ADC"},
0707     {"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
0708     {"ASPTX2SRC", "VPMON", "VPMON ADC"},
0709 
0710     {"ASPTX3SRC", "IMON", "IMON ADC"},
0711     {"ASPTX3SRC", "VMON", "VMON ADC"},
0712     {"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
0713     {"ASPTX3SRC", "VPMON", "VPMON ADC"},
0714 
0715     {"ASPTX4SRC", "IMON", "IMON ADC"},
0716     {"ASPTX4SRC", "VMON", "VMON ADC"},
0717     {"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
0718     {"ASPTX4SRC", "VPMON", "VPMON ADC"},
0719 
0720     {"ASPTX5SRC", "IMON", "IMON ADC"},
0721     {"ASPTX5SRC", "VMON", "VMON ADC"},
0722     {"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
0723     {"ASPTX5SRC", "VPMON", "VPMON ADC"},
0724 
0725     {"ASPTX6SRC", "IMON", "IMON ADC"},
0726     {"ASPTX6SRC", "VMON", "VMON ADC"},
0727     {"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
0728     {"ASPTX6SRC", "VPMON", "VPMON ADC"},
0729 
0730     {"ASPTX1", NULL, "ASPTX1SRC"},
0731     {"ASPTX2", NULL, "ASPTX2SRC"},
0732     {"ASPTX3", NULL, "ASPTX3SRC"},
0733     {"ASPTX4", NULL, "ASPTX4SRC"},
0734     {"ASPTX5", NULL, "ASPTX5SRC"},
0735     {"ASPTX6", NULL, "ASPTX6SRC"},
0736 
0737     {"AMP Capture", NULL, "ASPTX1"},
0738     {"AMP Capture", NULL, "ASPTX2"},
0739     {"AMP Capture", NULL, "ASPTX3"},
0740     {"AMP Capture", NULL, "ASPTX4"},
0741     {"AMP Capture", NULL, "ASPTX5"},
0742     {"AMP Capture", NULL, "ASPTX6"},
0743 
0744     {"AMP Enable", "Switch", "AMP Playback"},
0745     {"SDIN", NULL, "AMP Enable"},
0746     {"Channel Mux", "RX1", "SDIN"},
0747     {"Channel Mux", "RX2", "SDIN"},
0748     {"BOOST Enable", "Switch", "Channel Mux"},
0749     {"CLASS H", NULL, "BOOST Enable"},
0750     {"Main AMP", NULL, "Channel Mux"},
0751     {"Main AMP", NULL, "CLASS H"},
0752     {"SPK", NULL, "Main AMP"},
0753 };
0754 
0755 static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
0756                    unsigned int fmt)
0757 {
0758     struct cs35l36_private *cs35l36 =
0759             snd_soc_component_get_drvdata(component_dai->component);
0760     unsigned int asp_fmt, lrclk_fmt, sclk_fmt, clock_provider, clk_frc;
0761 
0762     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0763     case SND_SOC_DAIFMT_CBP_CFP:
0764         clock_provider = 1;
0765         break;
0766     case SND_SOC_DAIFMT_CBC_CFC:
0767         clock_provider = 0;
0768         break;
0769     default:
0770         return -EINVAL;
0771     }
0772 
0773     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
0774                 CS35L36_SCLK_MSTR_MASK,
0775                 clock_provider << CS35L36_SCLK_MSTR_SHIFT);
0776     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
0777                 CS35L36_LRCLK_MSTR_MASK,
0778                 clock_provider << CS35L36_LRCLK_MSTR_SHIFT);
0779 
0780     switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
0781     case SND_SOC_DAIFMT_CONT:
0782         clk_frc = 1;
0783         break;
0784     case SND_SOC_DAIFMT_GATED:
0785         clk_frc = 0;
0786         break;
0787     default:
0788         return -EINVAL;
0789     }
0790 
0791     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
0792                CS35L36_SCLK_FRC_MASK, clk_frc <<
0793                CS35L36_SCLK_FRC_SHIFT);
0794     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
0795                CS35L36_LRCLK_FRC_MASK, clk_frc <<
0796                CS35L36_LRCLK_FRC_SHIFT);
0797 
0798     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0799     case SND_SOC_DAIFMT_DSP_A:
0800         asp_fmt = 0;
0801         break;
0802     case SND_SOC_DAIFMT_I2S:
0803         asp_fmt = 2;
0804         break;
0805     default:
0806         return -EINVAL;
0807     }
0808 
0809     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0810     case SND_SOC_DAIFMT_NB_IF:
0811         lrclk_fmt = 1;
0812         sclk_fmt = 0;
0813         break;
0814     case SND_SOC_DAIFMT_IB_NF:
0815         lrclk_fmt = 0;
0816         sclk_fmt = 1;
0817         break;
0818     case SND_SOC_DAIFMT_IB_IF:
0819         lrclk_fmt = 1;
0820         sclk_fmt = 1;
0821         break;
0822     case SND_SOC_DAIFMT_NB_NF:
0823         lrclk_fmt = 0;
0824         sclk_fmt = 0;
0825         break;
0826     default:
0827         return -EINVAL;
0828     }
0829 
0830     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
0831                CS35L36_LRCLK_INV_MASK,
0832                lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
0833     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
0834                CS35L36_SCLK_INV_MASK,
0835                sclk_fmt << CS35L36_SCLK_INV_SHIFT);
0836     regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
0837                CS35L36_ASP_FMT_MASK, asp_fmt);
0838 
0839     return 0;
0840 }
0841 
0842 struct cs35l36_global_fs_config {
0843     int rate;
0844     int fs_cfg;
0845 };
0846 
0847 static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
0848     {12000, 0x01},
0849     {24000, 0x02},
0850     {48000, 0x03},
0851     {96000, 0x04},
0852     {192000, 0x05},
0853     {384000, 0x06},
0854     {11025, 0x09},
0855     {22050, 0x0A},
0856     {44100, 0x0B},
0857     {88200, 0x0C},
0858     {176400, 0x0D},
0859     {8000, 0x11},
0860     {16000, 0x12},
0861     {32000, 0x13},
0862 };
0863 
0864 static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
0865                  struct snd_pcm_hw_params *params,
0866                  struct snd_soc_dai *dai)
0867 {
0868     struct cs35l36_private *cs35l36 =
0869             snd_soc_component_get_drvdata(dai->component);
0870     unsigned int asp_width, global_fs = params_rate(params);
0871     int i;
0872 
0873     for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
0874         if (global_fs == cs35l36_fs_rates[i].rate)
0875             regmap_update_bits(cs35l36->regmap,
0876                        CS35L36_GLOBAL_CLK_CTRL,
0877                        CS35L36_GLOBAL_FS_MASK,
0878                        cs35l36_fs_rates[i].fs_cfg <<
0879                        CS35L36_GLOBAL_FS_SHIFT);
0880     }
0881 
0882     switch (params_width(params)) {
0883     case 16:
0884         asp_width = CS35L36_ASP_WIDTH_16;
0885         break;
0886     case 24:
0887         asp_width = CS35L36_ASP_WIDTH_24;
0888         break;
0889     case 32:
0890         asp_width = CS35L36_ASP_WIDTH_32;
0891         break;
0892     default:
0893         return -EINVAL;
0894     }
0895 
0896     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0897         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
0898                    CS35L36_ASP_RX_WIDTH_MASK,
0899                    asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
0900     } else {
0901         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
0902                    CS35L36_ASP_TX_WIDTH_MASK,
0903                    asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
0904     }
0905 
0906     return 0;
0907 }
0908 
0909 static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0910                   unsigned int freq, int dir)
0911 {
0912     struct snd_soc_component *component = dai->component;
0913     struct cs35l36_private *cs35l36 =
0914             snd_soc_component_get_drvdata(component);
0915     int fs1, fs2;
0916 
0917     if (freq > CS35L36_FS_NOM_6MHZ) {
0918         fs1 = CS35L36_FS1_DEFAULT_VAL;
0919         fs2 = CS35L36_FS2_DEFAULT_VAL;
0920     } else {
0921         fs1 = 3 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
0922         fs2 = 5 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
0923     }
0924 
0925     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
0926             CS35L36_TEST_UNLOCK1);
0927     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
0928             CS35L36_TEST_UNLOCK2);
0929 
0930     regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
0931                CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
0932                fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
0933 
0934     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
0935             CS35L36_TEST_LOCK1);
0936     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
0937             CS35L36_TEST_LOCK2);
0938     return 0;
0939 }
0940 
0941 static const struct cs35l36_pll_config *cs35l36_get_clk_config(
0942         struct cs35l36_private *cs35l36, int freq)
0943 {
0944     int i;
0945 
0946     for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
0947         if (cs35l36_pll_sysclk[i].freq == freq)
0948             return &cs35l36_pll_sysclk[i];
0949     }
0950 
0951     return NULL;
0952 }
0953 
0954 static const unsigned int cs35l36_src_rates[] = {
0955     8000, 12000, 11025, 16000, 22050, 24000, 32000,
0956     44100, 48000, 88200, 96000, 176400, 192000, 384000
0957 };
0958 
0959 static const struct snd_pcm_hw_constraint_list cs35l36_constraints = {
0960     .count  = ARRAY_SIZE(cs35l36_src_rates),
0961     .list   = cs35l36_src_rates,
0962 };
0963 
0964 static int cs35l36_pcm_startup(struct snd_pcm_substream *substream,
0965                    struct snd_soc_dai *dai)
0966 {
0967     snd_pcm_hw_constraint_list(substream->runtime, 0,
0968                 SNDRV_PCM_HW_PARAM_RATE, &cs35l36_constraints);
0969 
0970     return 0;
0971 }
0972 
0973 static const struct snd_soc_dai_ops cs35l36_ops = {
0974     .startup = cs35l36_pcm_startup,
0975     .set_fmt = cs35l36_set_dai_fmt,
0976     .hw_params = cs35l36_pcm_hw_params,
0977     .set_sysclk = cs35l36_dai_set_sysclk,
0978 };
0979 
0980 static struct snd_soc_dai_driver cs35l36_dai[] = {
0981     {
0982         .name = "cs35l36-pcm",
0983         .id = 0,
0984         .playback = {
0985             .stream_name = "AMP Playback",
0986             .channels_min = 1,
0987             .channels_max = 8,
0988             .rates = SNDRV_PCM_RATE_KNOT,
0989             .formats = CS35L36_RX_FORMATS,
0990         },
0991         .capture = {
0992             .stream_name = "AMP Capture",
0993             .channels_min = 1,
0994             .channels_max = 8,
0995             .rates = SNDRV_PCM_RATE_KNOT,
0996             .formats = CS35L36_TX_FORMATS,
0997         },
0998         .ops = &cs35l36_ops,
0999         .symmetric_rate = 1,
1000     },
1001 };
1002 
1003 static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
1004                 int clk_id, int source, unsigned int freq,
1005                 int dir)
1006 {
1007     struct cs35l36_private *cs35l36 =
1008             snd_soc_component_get_drvdata(component);
1009     const struct cs35l36_pll_config *clk_cfg;
1010     int prev_clksrc;
1011     bool pdm_switch;
1012 
1013     prev_clksrc = cs35l36->clksrc;
1014 
1015     switch (clk_id) {
1016     case 0:
1017         cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
1018         break;
1019     case 1:
1020         cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
1021         break;
1022     case 2:
1023         cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
1024         break;
1025     case 3:
1026         cs35l36->clksrc = CS35L36_PLLSRC_SELF;
1027         break;
1028     case 4:
1029         cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
1030         break;
1031     default:
1032         return -EINVAL;
1033     }
1034 
1035     clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
1036     if (clk_cfg == NULL) {
1037         dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
1038         return -EINVAL;
1039     }
1040 
1041     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1042                CS35L36_PLL_OPENLOOP_MASK,
1043                1 << CS35L36_PLL_OPENLOOP_SHIFT);
1044     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1045                CS35L36_REFCLK_FREQ_MASK,
1046                clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
1047     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1048                CS35L36_PLL_REFCLK_EN_MASK,
1049                0 << CS35L36_PLL_REFCLK_EN_SHIFT);
1050     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1051                CS35L36_PLL_CLK_SEL_MASK,
1052                cs35l36->clksrc);
1053     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1054                CS35L36_PLL_OPENLOOP_MASK,
1055                0 << CS35L36_PLL_OPENLOOP_SHIFT);
1056     regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1057                CS35L36_PLL_REFCLK_EN_MASK,
1058                1 << CS35L36_PLL_REFCLK_EN_SHIFT);
1059 
1060     if (cs35l36->rev_id == CS35L36_REV_A0) {
1061         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1062                  CS35L36_TEST_UNLOCK1);
1063         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1064                  CS35L36_TEST_UNLOCK2);
1065 
1066         regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
1067         regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
1068 
1069         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1070                    CS35L36_PLL_IGAIN_MASK,
1071                    CS35L36_PLL_IGAIN <<
1072                    CS35L36_PLL_IGAIN_SHIFT);
1073         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1074                    CS35L36_PLL_FFL_IGAIN_MASK,
1075                    clk_cfg->fll_igain);
1076 
1077         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1078                  CS35L36_TEST_LOCK1);
1079         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1080                  CS35L36_TEST_LOCK2);
1081     }
1082 
1083     if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
1084         pdm_switch = cs35l36->ldm_mode_sel &&
1085                  (prev_clksrc != CS35L36_PLLSRC_PDMCLK);
1086 
1087         if (pdm_switch)
1088             regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1089                        CS35L36_NG_DELAY_MASK,
1090                        0 << CS35L36_NG_DELAY_SHIFT);
1091 
1092         regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1093                    CS35L36_PDM_MODE_MASK,
1094                    1 << CS35L36_PDM_MODE_SHIFT);
1095 
1096         if (pdm_switch)
1097             regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1098                        CS35L36_NG_DELAY_MASK,
1099                        3 << CS35L36_NG_DELAY_SHIFT);
1100     } else {
1101         pdm_switch = cs35l36->ldm_mode_sel &&
1102                  (prev_clksrc == CS35L36_PLLSRC_PDMCLK);
1103 
1104         if (pdm_switch)
1105             regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1106                        CS35L36_NG_DELAY_MASK,
1107                        0 << CS35L36_NG_DELAY_SHIFT);
1108 
1109         regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1110                    CS35L36_PDM_MODE_MASK,
1111                    0 << CS35L36_PDM_MODE_SHIFT);
1112 
1113         if (pdm_switch)
1114             regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1115                        CS35L36_NG_DELAY_MASK,
1116                        3 << CS35L36_NG_DELAY_SHIFT);
1117     }
1118 
1119     return 0;
1120 }
1121 
1122 static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
1123 {
1124     regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1125                CS35L36_BSTCVRT_K1_MASK, 0x3C);
1126     regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1127                CS35L36_BSTCVRT_K2_MASK,
1128                0x3C << CS35L36_BSTCVRT_K2_SHIFT);
1129     regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
1130                CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
1131 
1132     switch (inductor) {
1133     case 1000: /* 1 uH */
1134         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1135                    CS35L36_BSTCVRT_SLOPE_MASK,
1136                    0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
1137         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1138                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
1139         break;
1140     case 1200: /* 1.2 uH */
1141         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1142                    CS35L36_BSTCVRT_SLOPE_MASK,
1143                    0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
1144         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1145                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
1146         break;
1147     default:
1148         dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
1149             __func__, inductor);
1150         return -EINVAL;
1151     }
1152 
1153     return 0;
1154 }
1155 
1156 static int cs35l36_component_probe(struct snd_soc_component *component)
1157 {
1158     struct cs35l36_private *cs35l36 =
1159             snd_soc_component_get_drvdata(component);
1160     int ret;
1161 
1162     if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
1163         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
1164                    CS35L36_DCM_AUTO_MASK,
1165                    CS35L36_DCM_AUTO_MASK);
1166 
1167         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1168                  CS35L36_TEST_UNLOCK1);
1169         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1170                  CS35L36_TEST_UNLOCK2);
1171 
1172         regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1173                    CS35L36_BST_MAN_IPKCOMP_MASK,
1174                    0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
1175         regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1176                    CS35L36_BST_MAN_IPKCOMP_EN_MASK,
1177                    CS35L36_BST_MAN_IPKCOMP_EN_MASK);
1178 
1179         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1180                 CS35L36_TEST_LOCK1);
1181         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1182                 CS35L36_TEST_LOCK2);
1183     }
1184 
1185     if (cs35l36->pdata.amp_pcm_inv)
1186         regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
1187                    CS35L36_AMP_PCM_INV_MASK,
1188                    CS35L36_AMP_PCM_INV_MASK);
1189 
1190     if (cs35l36->pdata.multi_amp_mode)
1191         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
1192                    CS35L36_ASP_TX_HIZ_MASK,
1193                    CS35L36_ASP_TX_HIZ_MASK);
1194 
1195     if (cs35l36->pdata.imon_pol_inv)
1196         regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1197                    CS35L36_IMON_POL_MASK, 0);
1198 
1199     if (cs35l36->pdata.vmon_pol_inv)
1200         regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1201                    CS35L36_VMON_POL_MASK, 0);
1202 
1203     if (cs35l36->pdata.bst_vctl)
1204         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1205                    CS35L35_BSTCVRT_CTL_MASK,
1206                    cs35l36->pdata.bst_vctl);
1207 
1208     if (cs35l36->pdata.bst_vctl_sel)
1209         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1210                    CS35L35_BSTCVRT_CTL_SEL_MASK,
1211                    cs35l36->pdata.bst_vctl_sel);
1212 
1213     if (cs35l36->pdata.bst_ipk)
1214         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
1215                    CS35L36_BST_IPK_MASK,
1216                    cs35l36->pdata.bst_ipk);
1217 
1218     if (cs35l36->pdata.boost_ind) {
1219         ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
1220         if (ret < 0) {
1221             dev_err(cs35l36->dev,
1222                 "Boost inductor config failed(%d)\n", ret);
1223             return ret;
1224         }
1225     }
1226 
1227     if (cs35l36->pdata.temp_warn_thld)
1228         regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
1229                    CS35L36_TEMP_THLD_MASK,
1230                    cs35l36->pdata.temp_warn_thld);
1231 
1232     if (cs35l36->pdata.irq_drv_sel)
1233         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1234                    CS35L36_INT_DRV_SEL_MASK,
1235                    cs35l36->pdata.irq_drv_sel <<
1236                    CS35L36_INT_DRV_SEL_SHIFT);
1237 
1238     if (cs35l36->pdata.irq_gpio_sel)
1239         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1240                    CS35L36_INT_GPIO_SEL_MASK,
1241                    cs35l36->pdata.irq_gpio_sel <<
1242                    CS35L36_INT_GPIO_SEL_SHIFT);
1243 
1244     /*
1245      * Rev B0 has 2 versions
1246      * L36 is 10V
1247      * L37 is 12V
1248      * If L36 we need to clamp some values for safety
1249      * after probe has setup dt values. We want to make
1250      * sure we dont miss any values set in probe
1251      */
1252     if (cs35l36->chip_version == CS35L36_10V_L36) {
1253         regmap_update_bits(cs35l36->regmap,
1254                    CS35L36_BSTCVRT_OVERVOLT_CTRL,
1255                    CS35L36_BST_OVP_THLD_MASK,
1256                    CS35L36_BST_OVP_THLD_11V);
1257 
1258         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1259                  CS35L36_TEST_UNLOCK1);
1260         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1261                  CS35L36_TEST_UNLOCK2);
1262 
1263         regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
1264                    CS35L36_BST_OVP_TRIM_MASK,
1265                    CS35L36_BST_OVP_TRIM_11V <<
1266                    CS35L36_BST_OVP_TRIM_SHIFT);
1267         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1268                    CS35L36_BST_CTRL_LIM_MASK,
1269                    1 << CS35L36_BST_CTRL_LIM_SHIFT);
1270         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1271                    CS35L35_BSTCVRT_CTL_MASK,
1272                    CS35L36_BST_CTRL_10V_CLAMP);
1273         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1274                  CS35L36_TEST_LOCK1);
1275         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1276                  CS35L36_TEST_LOCK2);
1277     }
1278 
1279     /*
1280      * RevA and B require the disabling of
1281      * SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
1282      * Just turn it off from default
1283      */
1284     regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
1285                CS35L36_SYNC_GLOBAL_OVR_MASK,
1286                0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
1287 
1288     return 0;
1289 }
1290 
1291 static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
1292     .probe          = &cs35l36_component_probe,
1293     .set_sysclk     = cs35l36_component_set_sysclk,
1294     .dapm_widgets       = cs35l36_dapm_widgets,
1295     .num_dapm_widgets   = ARRAY_SIZE(cs35l36_dapm_widgets),
1296     .dapm_routes        = cs35l36_audio_map,
1297     .num_dapm_routes    = ARRAY_SIZE(cs35l36_audio_map),
1298     .controls       = cs35l36_aud_controls,
1299     .num_controls       = ARRAY_SIZE(cs35l36_aud_controls),
1300     .idle_bias_on       = 1,
1301     .use_pmdown_time    = 1,
1302     .endianness     = 1,
1303 };
1304 
1305 static struct regmap_config cs35l36_regmap = {
1306     .reg_bits = 32,
1307     .val_bits = 32,
1308     .reg_stride = 4,
1309     .max_register = CS35L36_PAC_PMEM_WORD1023,
1310     .reg_defaults = cs35l36_reg,
1311     .num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
1312     .precious_reg = cs35l36_precious_reg,
1313     .volatile_reg = cs35l36_volatile_reg,
1314     .readable_reg = cs35l36_readable_reg,
1315     .cache_type = REGCACHE_RBTREE,
1316 };
1317 
1318 static irqreturn_t cs35l36_irq(int irq, void *data)
1319 {
1320     struct cs35l36_private *cs35l36 = data;
1321     unsigned int status[4];
1322     unsigned int masks[4];
1323     int ret = IRQ_NONE;
1324 
1325     /* ack the irq by reading all status registers */
1326     regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
1327              ARRAY_SIZE(status));
1328 
1329     regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
1330              ARRAY_SIZE(masks));
1331 
1332     /* Check to see if unmasked bits are active */
1333     if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
1334         !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
1335         return IRQ_NONE;
1336     }
1337 
1338     /*
1339      * The following interrupts require a
1340      * protection release cycle to get the
1341      * speaker out of Safe-Mode.
1342      */
1343     if (status[2] & CS35L36_AMP_SHORT_ERR) {
1344         dev_crit(cs35l36->dev, "Amp short error\n");
1345         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1346                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1347         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1348                    CS35L36_AMP_SHORT_ERR_RLS,
1349                    CS35L36_AMP_SHORT_ERR_RLS);
1350         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1351                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1352         regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
1353                    CS35L36_AMP_SHORT_ERR,
1354                    CS35L36_AMP_SHORT_ERR);
1355         ret = IRQ_HANDLED;
1356     }
1357 
1358     if (status[0] & CS35L36_TEMP_WARN) {
1359         dev_crit(cs35l36->dev, "Over temperature warning\n");
1360         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1361                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1362         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1363                    CS35L36_TEMP_WARN_ERR_RLS,
1364                    CS35L36_TEMP_WARN_ERR_RLS);
1365         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1366                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1367         regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1368                    CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
1369         ret = IRQ_HANDLED;
1370     }
1371 
1372     if (status[0] & CS35L36_TEMP_ERR) {
1373         dev_crit(cs35l36->dev, "Over temperature error\n");
1374         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1375                    CS35L36_TEMP_ERR_RLS, 0);
1376         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1377                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1378         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1379                    CS35L36_TEMP_ERR_RLS, 0);
1380         regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1381                    CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
1382         ret = IRQ_HANDLED;
1383     }
1384 
1385     if (status[0] & CS35L36_BST_OVP_ERR) {
1386         dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
1387         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1388                    CS35L36_TEMP_ERR_RLS, 0);
1389         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1390                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1391         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1392                    CS35L36_TEMP_ERR_RLS, 0);
1393         regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1394                    CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
1395         ret = IRQ_HANDLED;
1396     }
1397 
1398     if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
1399         dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
1400         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1401                    CS35L36_BST_UVP_ERR_RLS, 0);
1402         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1403                    CS35L36_BST_UVP_ERR_RLS,
1404                    CS35L36_BST_UVP_ERR_RLS);
1405         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1406                    CS35L36_BST_UVP_ERR_RLS, 0);
1407         regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1408                    CS35L36_BST_DCM_UVP_ERR,
1409                    CS35L36_BST_DCM_UVP_ERR);
1410         ret = IRQ_HANDLED;
1411     }
1412 
1413     if (status[0] & CS35L36_BST_SHORT_ERR) {
1414         dev_crit(cs35l36->dev, "LBST SHORT error!\n");
1415         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1416                    CS35L36_BST_SHORT_ERR_RLS, 0);
1417         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1418                    CS35L36_BST_SHORT_ERR_RLS,
1419                    CS35L36_BST_SHORT_ERR_RLS);
1420         regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1421                    CS35L36_BST_SHORT_ERR_RLS, 0);
1422         regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1423                    CS35L36_BST_SHORT_ERR,
1424                    CS35L36_BST_SHORT_ERR);
1425         ret = IRQ_HANDLED;
1426     }
1427 
1428     return ret;
1429 }
1430 
1431 static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
1432                 struct cs35l36_platform_data *pdata)
1433 {
1434     struct device_node *np = i2c_client->dev.of_node;
1435     struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1436     struct device_node *vpbr_node;
1437     unsigned int val;
1438     int ret;
1439 
1440     if (!np)
1441         return 0;
1442 
1443     ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
1444     if (!ret) {
1445         if (val < 2550 || val > 12000) {
1446             dev_err(&i2c_client->dev,
1447                 "Invalid Boost Voltage %d mV\n", val);
1448             return -EINVAL;
1449         }
1450         pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
1451     } else {
1452         dev_err(&i2c_client->dev,
1453             "Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
1454         return -EINVAL;
1455     }
1456 
1457     ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
1458     if (!ret)
1459         pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
1460 
1461     ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
1462     if (!ret) {
1463         if (val < 1600 || val > 4500) {
1464             dev_err(&i2c_client->dev,
1465                 "Invalid Boost Peak Current %u mA\n", val);
1466             return -EINVAL;
1467         }
1468 
1469         pdata->bst_ipk = (val - 1600) / 50;
1470     } else {
1471         dev_err(&i2c_client->dev,
1472             "Unable to find required parameter 'cirrus,boost-peak-milliamp'");
1473         return -EINVAL;
1474     }
1475 
1476     pdata->multi_amp_mode = of_property_read_bool(np,
1477                     "cirrus,multi-amp-mode");
1478 
1479     pdata->dcm_mode = of_property_read_bool(np,
1480                     "cirrus,dcm-mode-enable");
1481 
1482     pdata->amp_pcm_inv = of_property_read_bool(np,
1483                     "cirrus,amp-pcm-inv");
1484 
1485     pdata->imon_pol_inv = of_property_read_bool(np,
1486                     "cirrus,imon-pol-inv");
1487 
1488     pdata->vmon_pol_inv = of_property_read_bool(np,
1489                     "cirrus,vmon-pol-inv");
1490 
1491     if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
1492         pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
1493 
1494     if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
1495         pdata->boost_ind = val;
1496     } else {
1497         dev_err(&i2c_client->dev, "Inductor not specified.\n");
1498         return -EINVAL;
1499     }
1500 
1501     if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
1502         pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
1503 
1504     if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
1505         pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
1506 
1507     /* VPBR Config */
1508     vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
1509     vpbr_config->is_present = vpbr_node ? true : false;
1510     if (vpbr_config->is_present) {
1511         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
1512                      &val) >= 0)
1513             vpbr_config->vpbr_en = val;
1514         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
1515                      &val) >= 0)
1516             vpbr_config->vpbr_thld = val;
1517         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
1518                      &val) >= 0)
1519             vpbr_config->vpbr_atk_rate = val;
1520         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
1521                      &val) >= 0)
1522             vpbr_config->vpbr_atk_vol = val;
1523         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
1524                      &val) >= 0)
1525             vpbr_config->vpbr_max_attn = val;
1526         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
1527                      &val) >= 0)
1528             vpbr_config->vpbr_wait = val;
1529         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
1530                      &val) >= 0)
1531             vpbr_config->vpbr_rel_rate = val;
1532         if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
1533                      &val) >= 0)
1534             vpbr_config->vpbr_mute_en = val;
1535     }
1536     of_node_put(vpbr_node);
1537 
1538     return 0;
1539 }
1540 
1541 static int cs35l36_pac(struct cs35l36_private *cs35l36)
1542 {
1543     int ret, count;
1544     unsigned int val;
1545 
1546     if (cs35l36->rev_id != CS35L36_REV_B0)
1547         return 0;
1548 
1549     /*
1550      * Magic code for internal PAC
1551      */
1552     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1553              CS35L36_TEST_UNLOCK1);
1554     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1555              CS35L36_TEST_UNLOCK2);
1556 
1557     usleep_range(9500, 10500);
1558 
1559     regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1560              CS35L36_PAC_RESET);
1561     regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1562              CS35L36_PAC_MEM_ACCESS);
1563     regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
1564              CS35L36_B0_PAC_PATCH);
1565 
1566     regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1567              CS35L36_PAC_MEM_ACCESS_CLR);
1568     regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1569              CS35L36_PAC_ENABLE_MASK);
1570 
1571     usleep_range(9500, 10500);
1572 
1573     ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
1574     if (ret < 0) {
1575         dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
1576         return ret;
1577     }
1578 
1579     count = 0;
1580     while (!(val & CS35L36_MCU_CONFIG_CLR)) {
1581         usleep_range(100, 200);
1582         count++;
1583 
1584         ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
1585                   &val);
1586         if (ret < 0) {
1587             dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
1588                 ret);
1589             return ret;
1590         }
1591 
1592         if (count >= 100)
1593             return -EINVAL;
1594     }
1595 
1596     regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
1597              CS35L36_MCU_CONFIG_CLR);
1598     regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
1599                CS35L36_PAC_ENABLE_MASK, 0);
1600 
1601     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1602              CS35L36_TEST_LOCK1);
1603     regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1604              CS35L36_TEST_LOCK2);
1605 
1606     return 0;
1607 }
1608 
1609 static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
1610 {
1611     struct cs35l36_platform_data *pdata = &cs35l36->pdata;
1612     struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1613 
1614     regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
1615                CS35L36_VPBR_EN_MASK,
1616                vpbr_config->vpbr_en <<
1617                CS35L36_VPBR_EN_SHIFT);
1618     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1619                CS35L36_VPBR_THLD_MASK,
1620                vpbr_config->vpbr_thld <<
1621                CS35L36_VPBR_THLD_SHIFT);
1622     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1623                CS35L36_VPBR_MAX_ATTN_MASK,
1624                vpbr_config->vpbr_max_attn <<
1625                CS35L36_VPBR_MAX_ATTN_SHIFT);
1626     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1627                CS35L36_VPBR_ATK_VOL_MASK,
1628                vpbr_config->vpbr_atk_vol <<
1629                CS35L36_VPBR_ATK_VOL_SHIFT);
1630     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1631                CS35L36_VPBR_ATK_RATE_MASK,
1632                vpbr_config->vpbr_atk_rate <<
1633                CS35L36_VPBR_ATK_RATE_SHIFT);
1634     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1635                CS35L36_VPBR_WAIT_MASK,
1636                vpbr_config->vpbr_wait <<
1637                CS35L36_VPBR_WAIT_SHIFT);
1638     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1639                CS35L36_VPBR_REL_RATE_MASK,
1640                vpbr_config->vpbr_rel_rate <<
1641                CS35L36_VPBR_REL_RATE_SHIFT);
1642     regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1643                CS35L36_VPBR_MUTE_EN_MASK,
1644                vpbr_config->vpbr_mute_en <<
1645                CS35L36_VPBR_MUTE_EN_SHIFT);
1646 }
1647 
1648 static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
1649     { CS35L36_TESTKEY_CTRL,     CS35L36_TEST_UNLOCK1 },
1650     { CS35L36_TESTKEY_CTRL,     CS35L36_TEST_UNLOCK2 },
1651     /* Errata Writes */
1652     { CS35L36_OTP_CTRL1,        0x00002060 },
1653     { CS35L36_OTP_CTRL2,        0x00000001 },
1654     { CS35L36_OTP_CTRL1,        0x00002460 },
1655     { CS35L36_OTP_CTRL2,        0x00000001 },
1656     { 0x00002088,           0x012A1838 },
1657     { 0x00003014,           0x0100EE0E },
1658     { 0x00003008,           0x0008184A },
1659     { 0x00007418,           0x509001C8 },
1660     { 0x00007064,           0x0929A800 },
1661     { 0x00002D10,           0x0002C01C },
1662     { 0x0000410C,           0x00000A11 },
1663     { 0x00006E08,           0x8B19140C },
1664     { 0x00006454,           0x0300000A },
1665     { CS35L36_AMP_NG_CTRL,      0x000020EF },
1666     { 0x00007E34,           0x0000000E },
1667     { 0x0000410C,           0x00000A11 },
1668     { 0x00007410,           0x20514B00 },
1669     /* PAC Config */
1670     { CS35L36_CTRL_OVRRIDE,     0x00000000 },
1671     { CS35L36_PAC_INT0_CTRL,    0x00860001 },
1672     { CS35L36_PAC_INT1_CTRL,    0x00860001 },
1673     { CS35L36_PAC_INT2_CTRL,    0x00860001 },
1674     { CS35L36_PAC_INT3_CTRL,    0x00860001 },
1675     { CS35L36_PAC_INT4_CTRL,    0x00860001 },
1676     { CS35L36_PAC_INT5_CTRL,    0x00860001 },
1677     { CS35L36_PAC_INT6_CTRL,    0x00860001 },
1678     { CS35L36_PAC_INT7_CTRL,    0x00860001 },
1679     { CS35L36_PAC_INT_FLUSH_CTRL,   0x000000FF },
1680     { CS35L36_TESTKEY_CTRL,     CS35L36_TEST_LOCK1 },
1681     { CS35L36_TESTKEY_CTRL,     CS35L36_TEST_LOCK2 },
1682 };
1683 
1684 static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
1685     { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
1686     { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
1687     { 0x00007064,       0x0929A800 },
1688     { 0x00007850,       0x00002FA9 },
1689     { 0x00007854,       0x0003F1D5 },
1690     { 0x00007858,       0x0003F5E3 },
1691     { 0x0000785C,       0x00001137 },
1692     { 0x00007860,       0x0001A7A5 },
1693     { 0x00007864,       0x0002F16A },
1694     { 0x00007868,       0x00003E21 },
1695     { 0x00007848,       0x00000001 },
1696     { 0x00003854,       0x05180240 },
1697     { 0x00007418,       0x509001C8 },
1698     { 0x0000394C,       0x028764BD },
1699     { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
1700     { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
1701 };
1702 
1703 static int cs35l36_i2c_probe(struct i2c_client *i2c_client)
1704 {
1705     struct cs35l36_private *cs35l36;
1706     struct device *dev = &i2c_client->dev;
1707     struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
1708     struct irq_data *irq_d;
1709     int ret, irq_pol, chip_irq_pol, i;
1710     u32 reg_id, reg_revid, l37_id_reg;
1711 
1712     cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
1713     if (!cs35l36)
1714         return -ENOMEM;
1715 
1716     cs35l36->dev = dev;
1717 
1718     i2c_set_clientdata(i2c_client, cs35l36);
1719     cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
1720     if (IS_ERR(cs35l36->regmap)) {
1721         ret = PTR_ERR(cs35l36->regmap);
1722         dev_err(dev, "regmap_init() failed: %d\n", ret);
1723         return ret;
1724     }
1725 
1726     cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
1727     for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
1728         cs35l36->supplies[i].supply = cs35l36_supplies[i];
1729 
1730     ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
1731                       cs35l36->supplies);
1732     if (ret != 0) {
1733         dev_err(dev, "Failed to request core supplies: %d\n", ret);
1734         return ret;
1735     }
1736 
1737     if (pdata) {
1738         cs35l36->pdata = *pdata;
1739     } else {
1740         pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
1741                      GFP_KERNEL);
1742         if (!pdata)
1743             return -ENOMEM;
1744 
1745         if (i2c_client->dev.of_node) {
1746             ret = cs35l36_handle_of_data(i2c_client, pdata);
1747             if (ret != 0)
1748                 return ret;
1749 
1750         }
1751 
1752         cs35l36->pdata = *pdata;
1753     }
1754 
1755     ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
1756     if (ret != 0) {
1757         dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1758         return ret;
1759     }
1760 
1761     /* returning NULL can be an option if in stereo mode */
1762     cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1763                               GPIOD_OUT_LOW);
1764     if (IS_ERR(cs35l36->reset_gpio)) {
1765         ret = PTR_ERR(cs35l36->reset_gpio);
1766         cs35l36->reset_gpio = NULL;
1767         if (ret == -EBUSY) {
1768             dev_info(dev, "Reset line busy, assuming shared reset\n");
1769         } else {
1770             dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1771             goto err_disable_regs;
1772         }
1773     }
1774 
1775     if (cs35l36->reset_gpio)
1776         gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
1777 
1778     usleep_range(2000, 2100);
1779 
1780     /* initialize amplifier */
1781     ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, &reg_id);
1782     if (ret < 0) {
1783         dev_err(dev, "Get Device ID failed %d\n", ret);
1784         goto err;
1785     }
1786 
1787     if (reg_id != CS35L36_CHIP_ID) {
1788         dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
1789             CS35L36_CHIP_ID);
1790         ret = -ENODEV;
1791         goto err;
1792     }
1793 
1794     ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, &reg_revid);
1795     if (ret < 0) {
1796         dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
1797         goto err;
1798     }
1799 
1800     cs35l36->rev_id = reg_revid >> 8;
1801 
1802     ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
1803     if (ret < 0) {
1804         dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
1805             ret);
1806         goto err;
1807     }
1808 
1809     if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
1810         cs35l36->chip_version = CS35L36_12V_L37;
1811     else
1812         cs35l36->chip_version = CS35L36_10V_L36;
1813 
1814     switch (cs35l36->rev_id) {
1815     case CS35L36_REV_A0:
1816         ret = regmap_register_patch(cs35l36->regmap,
1817                 cs35l36_reva0_errata_patch,
1818                 ARRAY_SIZE(cs35l36_reva0_errata_patch));
1819         if (ret < 0) {
1820             dev_err(dev, "Failed to apply A0 errata patch %d\n",
1821                 ret);
1822             goto err;
1823         }
1824         break;
1825     case CS35L36_REV_B0:
1826         ret = cs35l36_pac(cs35l36);
1827         if (ret < 0) {
1828             dev_err(dev, "Failed to Trim OTP %d\n", ret);
1829             goto err;
1830         }
1831 
1832         ret = regmap_register_patch(cs35l36->regmap,
1833                 cs35l36_revb0_errata_patch,
1834                 ARRAY_SIZE(cs35l36_revb0_errata_patch));
1835         if (ret < 0) {
1836             dev_err(dev, "Failed to apply B0 errata patch %d\n",
1837                 ret);
1838             goto err;
1839         }
1840         break;
1841     }
1842 
1843     if (pdata->vpbr_config.is_present)
1844         cs35l36_apply_vpbr_config(cs35l36);
1845 
1846     irq_d = irq_get_irq_data(i2c_client->irq);
1847     if (!irq_d) {
1848         dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
1849         ret = -ENODEV;
1850         goto err;
1851     }
1852 
1853     irq_pol = irqd_get_trigger_type(irq_d);
1854 
1855     switch (irq_pol) {
1856     case IRQF_TRIGGER_FALLING:
1857     case IRQF_TRIGGER_LOW:
1858         chip_irq_pol = 0;
1859         break;
1860     case IRQF_TRIGGER_RISING:
1861     case IRQF_TRIGGER_HIGH:
1862         chip_irq_pol = 1;
1863         break;
1864     default:
1865         dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
1866         ret = -EINVAL;
1867         goto err;
1868     }
1869 
1870     regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1871                CS35L36_INT_POL_SEL_MASK,
1872                chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
1873 
1874     ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
1875                     IRQF_ONESHOT | irq_pol, "cs35l36",
1876                     cs35l36);
1877     if (ret != 0) {
1878         dev_err(dev, "Failed to request IRQ: %d\n", ret);
1879         goto err;
1880     }
1881 
1882     regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1883                CS35L36_INT_OUTPUT_EN_MASK, 1);
1884 
1885     /* Set interrupt masks for critical errors */
1886     regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1887              CS35L36_INT1_MASK_DEFAULT);
1888     regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1889              CS35L36_INT3_MASK_DEFAULT);
1890 
1891     dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
1892          cs35l36->chip_version, reg_revid >> 8);
1893 
1894     ret =  devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
1895                            cs35l36_dai,
1896                            ARRAY_SIZE(cs35l36_dai));
1897     if (ret < 0) {
1898         dev_err(dev, "%s: Register component failed %d\n", __func__,
1899             ret);
1900         goto err;
1901     }
1902 
1903     return 0;
1904 
1905 err:
1906     gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1907 
1908 err_disable_regs:
1909     regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1910     return ret;
1911 }
1912 
1913 static int cs35l36_i2c_remove(struct i2c_client *client)
1914 {
1915     struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
1916 
1917     /* Reset interrupt masks for device removal */
1918     regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1919              CS35L36_INT1_MASK_RESET);
1920     regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1921              CS35L36_INT3_MASK_RESET);
1922 
1923     if (cs35l36->reset_gpio)
1924         gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1925 
1926     regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1927 
1928     return 0;
1929 }
1930 static const struct of_device_id cs35l36_of_match[] = {
1931     {.compatible = "cirrus,cs35l36"},
1932     {},
1933 };
1934 MODULE_DEVICE_TABLE(of, cs35l36_of_match);
1935 
1936 static const struct i2c_device_id cs35l36_id[] = {
1937     {"cs35l36", 0},
1938     {}
1939 };
1940 
1941 MODULE_DEVICE_TABLE(i2c, cs35l36_id);
1942 
1943 static struct i2c_driver cs35l36_i2c_driver = {
1944     .driver = {
1945         .name = "cs35l36",
1946         .of_match_table = cs35l36_of_match,
1947     },
1948     .id_table = cs35l36_id,
1949     .probe_new = cs35l36_i2c_probe,
1950     .remove = cs35l36_i2c_remove,
1951 };
1952 module_i2c_driver(cs35l36_i2c_driver);
1953 
1954 MODULE_DESCRIPTION("ASoC CS35L36 driver");
1955 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1956 MODULE_LICENSE("GPL");
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