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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cs35l35.c -- CS35L35 ALSA SoC audio driver
0004  *
0005  * Copyright 2017 Cirrus Logic, Inc.
0006  *
0007  * Author: Brian Austin <brian.austin@cirrus.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/i2c.h>
0016 #include <linux/slab.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <linux/of_device.h>
0021 #include <linux/of_gpio.h>
0022 #include <linux/regmap.h>
0023 #include <sound/core.h>
0024 #include <sound/pcm.h>
0025 #include <sound/pcm_params.h>
0026 #include <sound/soc.h>
0027 #include <sound/soc-dapm.h>
0028 #include <linux/gpio.h>
0029 #include <sound/initval.h>
0030 #include <sound/tlv.h>
0031 #include <sound/cs35l35.h>
0032 #include <linux/of_irq.h>
0033 #include <linux/completion.h>
0034 
0035 #include "cs35l35.h"
0036 #include "cirrus_legacy.h"
0037 
0038 /*
0039  * Some fields take zero as a valid value so use a high bit flag that won't
0040  * get written to the device to mark those.
0041  */
0042 #define CS35L35_VALID_PDATA 0x80000000
0043 
0044 static const struct reg_default cs35l35_reg[] = {
0045     {CS35L35_PWRCTL1,       0x01},
0046     {CS35L35_PWRCTL2,       0x11},
0047     {CS35L35_PWRCTL3,       0x00},
0048     {CS35L35_CLK_CTL1,      0x04},
0049     {CS35L35_CLK_CTL2,      0x12},
0050     {CS35L35_CLK_CTL3,      0xCF},
0051     {CS35L35_SP_FMT_CTL1,       0x20},
0052     {CS35L35_SP_FMT_CTL2,       0x00},
0053     {CS35L35_SP_FMT_CTL3,       0x02},
0054     {CS35L35_MAG_COMP_CTL,      0x00},
0055     {CS35L35_AMP_INP_DRV_CTL,   0x01},
0056     {CS35L35_AMP_DIG_VOL_CTL,   0x12},
0057     {CS35L35_AMP_DIG_VOL,       0x00},
0058     {CS35L35_ADV_DIG_VOL,       0x00},
0059     {CS35L35_PROTECT_CTL,       0x06},
0060     {CS35L35_AMP_GAIN_AUD_CTL,  0x13},
0061     {CS35L35_AMP_GAIN_PDM_CTL,  0x00},
0062     {CS35L35_AMP_GAIN_ADV_CTL,  0x00},
0063     {CS35L35_GPI_CTL,       0x00},
0064     {CS35L35_BST_CVTR_V_CTL,    0x00},
0065     {CS35L35_BST_PEAK_I,        0x07},
0066     {CS35L35_BST_RAMP_CTL,      0x85},
0067     {CS35L35_BST_CONV_COEF_1,   0x24},
0068     {CS35L35_BST_CONV_COEF_2,   0x24},
0069     {CS35L35_BST_CONV_SLOPE_COMP,   0x4E},
0070     {CS35L35_BST_CONV_SW_FREQ,  0x04},
0071     {CS35L35_CLASS_H_CTL,       0x0B},
0072     {CS35L35_CLASS_H_HEADRM_CTL,    0x0B},
0073     {CS35L35_CLASS_H_RELEASE_RATE,  0x08},
0074     {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
0075     {CS35L35_CLASS_H_VP_CTL,    0xC5},
0076     {CS35L35_VPBR_CTL,      0x0A},
0077     {CS35L35_VPBR_VOL_CTL,      0x90},
0078     {CS35L35_VPBR_TIMING_CTL,   0x6A},
0079     {CS35L35_VPBR_MODE_VOL_CTL, 0x00},
0080     {CS35L35_SPKR_MON_CTL,      0xC0},
0081     {CS35L35_IMON_SCALE_CTL,    0x30},
0082     {CS35L35_AUDIN_RXLOC_CTL,   0x00},
0083     {CS35L35_ADVIN_RXLOC_CTL,   0x80},
0084     {CS35L35_VMON_TXLOC_CTL,    0x00},
0085     {CS35L35_IMON_TXLOC_CTL,    0x80},
0086     {CS35L35_VPMON_TXLOC_CTL,   0x04},
0087     {CS35L35_VBSTMON_TXLOC_CTL, 0x84},
0088     {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
0089     {CS35L35_ZERO_FILL_LOC_CTL, 0x00},
0090     {CS35L35_AUDIN_DEPTH_CTL,   0x0F},
0091     {CS35L35_SPKMON_DEPTH_CTL,  0x0F},
0092     {CS35L35_SUPMON_DEPTH_CTL,  0x0F},
0093     {CS35L35_ZEROFILL_DEPTH_CTL,    0x00},
0094     {CS35L35_MULT_DEV_SYNCH1,   0x02},
0095     {CS35L35_MULT_DEV_SYNCH2,   0x80},
0096     {CS35L35_PROT_RELEASE_CTL,  0x00},
0097     {CS35L35_DIAG_MODE_REG_LOCK,    0x00},
0098     {CS35L35_DIAG_MODE_CTL_1,   0x40},
0099     {CS35L35_DIAG_MODE_CTL_2,   0x00},
0100     {CS35L35_INT_MASK_1,        0xFF},
0101     {CS35L35_INT_MASK_2,        0xFF},
0102     {CS35L35_INT_MASK_3,        0xFF},
0103     {CS35L35_INT_MASK_4,        0xFF},
0104 
0105 };
0106 
0107 static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
0108 {
0109     switch (reg) {
0110     case CS35L35_INT_STATUS_1:
0111     case CS35L35_INT_STATUS_2:
0112     case CS35L35_INT_STATUS_3:
0113     case CS35L35_INT_STATUS_4:
0114     case CS35L35_PLL_STATUS:
0115     case CS35L35_OTP_TRIM_STATUS:
0116         return true;
0117     default:
0118         return false;
0119     }
0120 }
0121 
0122 static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
0123 {
0124     switch (reg) {
0125     case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
0126     case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
0127     case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
0128     case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
0129     case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
0130     case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
0131     case CS35L35_CLASS_H_STATUS:
0132     case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
0133     case CS35L35_VPBR_ATTEN_STATUS:
0134     case CS35L35_SPKR_MON_CTL:
0135     case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
0136     case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
0137     case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
0138     case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
0139     case CS35L35_OTP_TRIM_STATUS:
0140         return true;
0141     default:
0142         return false;
0143     }
0144 }
0145 
0146 static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
0147 {
0148     switch (reg) {
0149     case CS35L35_INT_STATUS_1:
0150     case CS35L35_INT_STATUS_2:
0151     case CS35L35_INT_STATUS_3:
0152     case CS35L35_INT_STATUS_4:
0153     case CS35L35_PLL_STATUS:
0154     case CS35L35_OTP_TRIM_STATUS:
0155         return true;
0156     default:
0157         return false;
0158     }
0159 }
0160 
0161 static void cs35l35_reset(struct cs35l35_private *cs35l35)
0162 {
0163     gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
0164     usleep_range(2000, 2100);
0165     gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
0166     usleep_range(1000, 1100);
0167 }
0168 
0169 static int cs35l35_wait_for_pdn(struct cs35l35_private *cs35l35)
0170 {
0171     int ret;
0172 
0173     if (cs35l35->pdata.ext_bst) {
0174         usleep_range(5000, 5500);
0175         return 0;
0176     }
0177 
0178     reinit_completion(&cs35l35->pdn_done);
0179 
0180     ret = wait_for_completion_timeout(&cs35l35->pdn_done,
0181                       msecs_to_jiffies(100));
0182     if (ret == 0) {
0183         dev_err(cs35l35->dev, "PDN_DONE did not complete\n");
0184         return -ETIMEDOUT;
0185     }
0186 
0187     return 0;
0188 }
0189 
0190 static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
0191         struct snd_kcontrol *kcontrol, int event)
0192 {
0193     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0194     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0195     int ret = 0;
0196 
0197     switch (event) {
0198     case SND_SOC_DAPM_PRE_PMU:
0199         regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0200                     CS35L35_MCLK_DIS_MASK,
0201                     0 << CS35L35_MCLK_DIS_SHIFT);
0202         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
0203                     CS35L35_DISCHG_FILT_MASK,
0204                     0 << CS35L35_DISCHG_FILT_SHIFT);
0205         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
0206                     CS35L35_PDN_ALL_MASK, 0);
0207         break;
0208     case SND_SOC_DAPM_POST_PMD:
0209         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
0210                     CS35L35_DISCHG_FILT_MASK,
0211                     1 << CS35L35_DISCHG_FILT_SHIFT);
0212         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
0213                       CS35L35_PDN_ALL_MASK, 1);
0214 
0215         /* Already muted, so disable volume ramp for faster shutdown */
0216         regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
0217                    CS35L35_AMP_DIGSFT_MASK, 0);
0218 
0219         ret = cs35l35_wait_for_pdn(cs35l35);
0220 
0221         regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0222                     CS35L35_MCLK_DIS_MASK,
0223                     1 << CS35L35_MCLK_DIS_SHIFT);
0224 
0225         regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
0226                    CS35L35_AMP_DIGSFT_MASK,
0227                    1 << CS35L35_AMP_DIGSFT_SHIFT);
0228         break;
0229     default:
0230         dev_err(component->dev, "Invalid event = 0x%x\n", event);
0231         ret = -EINVAL;
0232     }
0233     return ret;
0234 }
0235 
0236 static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
0237         struct snd_kcontrol *kcontrol, int event)
0238 {
0239     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0240     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0241     unsigned int reg[4];
0242     int i;
0243 
0244     switch (event) {
0245     case SND_SOC_DAPM_PRE_PMU:
0246         if (cs35l35->pdata.bst_pdn_fet_on)
0247             regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
0248                 CS35L35_PDN_BST_MASK,
0249                 0 << CS35L35_PDN_BST_FETON_SHIFT);
0250         else
0251             regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
0252                 CS35L35_PDN_BST_MASK,
0253                 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
0254         break;
0255     case SND_SOC_DAPM_POST_PMU:
0256         usleep_range(5000, 5100);
0257         /* If in PDM mode we must use VP for Voltage control */
0258         if (cs35l35->pdm_mode)
0259             regmap_update_bits(cs35l35->regmap,
0260                     CS35L35_BST_CVTR_V_CTL,
0261                     CS35L35_BST_CTL_MASK,
0262                     0 << CS35L35_BST_CTL_SHIFT);
0263 
0264         regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
0265             CS35L35_AMP_MUTE_MASK, 0);
0266 
0267         for (i = 0; i < 2; i++)
0268             regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
0269                     &reg, ARRAY_SIZE(reg));
0270 
0271         break;
0272     case SND_SOC_DAPM_PRE_PMD:
0273         regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
0274                 CS35L35_AMP_MUTE_MASK,
0275                 1 << CS35L35_AMP_MUTE_SHIFT);
0276         if (cs35l35->pdata.bst_pdn_fet_on)
0277             regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
0278                 CS35L35_PDN_BST_MASK,
0279                 1 << CS35L35_PDN_BST_FETON_SHIFT);
0280         else
0281             regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
0282                 CS35L35_PDN_BST_MASK,
0283                 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
0284         break;
0285     case SND_SOC_DAPM_POST_PMD:
0286         usleep_range(5000, 5100);
0287         /*
0288          * If PDM mode we should switch back to pdata value
0289          * for Voltage control when we go down
0290          */
0291         if (cs35l35->pdm_mode)
0292             regmap_update_bits(cs35l35->regmap,
0293                     CS35L35_BST_CVTR_V_CTL,
0294                     CS35L35_BST_CTL_MASK,
0295                     cs35l35->pdata.bst_vctl
0296                     << CS35L35_BST_CTL_SHIFT);
0297 
0298         break;
0299     default:
0300         dev_err(component->dev, "Invalid event = 0x%x\n", event);
0301     }
0302     return 0;
0303 }
0304 
0305 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
0306 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
0307 
0308 static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
0309     SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
0310               0, 0x34, 0xE4, dig_vol_tlv),
0311     SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
0312             amp_gain_tlv),
0313     SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
0314             amp_gain_tlv),
0315 };
0316 
0317 static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
0318     SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
0319               0, 0x34, 0xE4, dig_vol_tlv),
0320     SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
0321             amp_gain_tlv),
0322 };
0323 
0324 static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
0325     SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
0326                 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
0327                 SND_SOC_DAPM_POST_PMD),
0328     SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
0329 
0330     SND_SOC_DAPM_OUTPUT("SPK"),
0331 
0332     SND_SOC_DAPM_INPUT("VP"),
0333     SND_SOC_DAPM_INPUT("VBST"),
0334     SND_SOC_DAPM_INPUT("ISENSE"),
0335     SND_SOC_DAPM_INPUT("VSENSE"),
0336 
0337     SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
0338     SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
0339     SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
0340     SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
0341     SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
0342 
0343     SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
0344         cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
0345                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
0346                 SND_SOC_DAPM_PRE_PMD),
0347 };
0348 
0349 static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
0350     {"VPMON ADC", NULL, "VP"},
0351     {"VBSTMON ADC", NULL, "VBST"},
0352     {"IMON ADC", NULL, "ISENSE"},
0353     {"VMON ADC", NULL, "VSENSE"},
0354     {"SDOUT", NULL, "IMON ADC"},
0355     {"SDOUT", NULL, "VMON ADC"},
0356     {"SDOUT", NULL, "VBSTMON ADC"},
0357     {"SDOUT", NULL, "VPMON ADC"},
0358     {"AMP Capture", NULL, "SDOUT"},
0359 
0360     {"SDIN", NULL, "AMP Playback"},
0361     {"CLASS H", NULL, "SDIN"},
0362     {"Main AMP", NULL, "CLASS H"},
0363     {"SPK", NULL, "Main AMP"},
0364 };
0365 
0366 static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0367 {
0368     struct snd_soc_component *component = codec_dai->component;
0369     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0370 
0371     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0372     case SND_SOC_DAIFMT_CBP_CFP:
0373         regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0374                     CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
0375         cs35l35->clock_consumer = false;
0376         break;
0377     case SND_SOC_DAIFMT_CBC_CFC:
0378         regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0379                     CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
0380         cs35l35->clock_consumer = true;
0381         break;
0382     default:
0383         return -EINVAL;
0384     }
0385 
0386     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0387     case SND_SOC_DAIFMT_I2S:
0388         cs35l35->i2s_mode = true;
0389         cs35l35->pdm_mode = false;
0390         break;
0391     case SND_SOC_DAIFMT_PDM:
0392         cs35l35->pdm_mode = true;
0393         cs35l35->i2s_mode = false;
0394         break;
0395     default:
0396         return -EINVAL;
0397     }
0398 
0399     return 0;
0400 }
0401 
0402 struct cs35l35_sysclk_config {
0403     int sysclk;
0404     int srate;
0405     u8 clk_cfg;
0406 };
0407 
0408 static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
0409 
0410     /* SYSCLK, Sample Rate, Serial Port Cfg */
0411     {5644800, 44100, 0x00},
0412     {5644800, 88200, 0x40},
0413     {6144000, 48000, 0x10},
0414     {6144000, 96000, 0x50},
0415     {11289600, 44100, 0x01},
0416     {11289600, 88200, 0x41},
0417     {11289600, 176400, 0x81},
0418     {12000000, 44100, 0x03},
0419     {12000000, 48000, 0x13},
0420     {12000000, 88200, 0x43},
0421     {12000000, 96000, 0x53},
0422     {12000000, 176400, 0x83},
0423     {12000000, 192000, 0x93},
0424     {12288000, 48000, 0x11},
0425     {12288000, 96000, 0x51},
0426     {12288000, 192000, 0x91},
0427     {13000000, 44100, 0x07},
0428     {13000000, 48000, 0x17},
0429     {13000000, 88200, 0x47},
0430     {13000000, 96000, 0x57},
0431     {13000000, 176400, 0x87},
0432     {13000000, 192000, 0x97},
0433     {22579200, 44100, 0x02},
0434     {22579200, 88200, 0x42},
0435     {22579200, 176400, 0x82},
0436     {24000000, 44100, 0x0B},
0437     {24000000, 48000, 0x1B},
0438     {24000000, 88200, 0x4B},
0439     {24000000, 96000, 0x5B},
0440     {24000000, 176400, 0x8B},
0441     {24000000, 192000, 0x9B},
0442     {24576000, 48000, 0x12},
0443     {24576000, 96000, 0x52},
0444     {24576000, 192000, 0x92},
0445     {26000000, 44100, 0x0F},
0446     {26000000, 48000, 0x1F},
0447     {26000000, 88200, 0x4F},
0448     {26000000, 96000, 0x5F},
0449     {26000000, 176400, 0x8F},
0450     {26000000, 192000, 0x9F},
0451 };
0452 
0453 static int cs35l35_get_clk_config(int sysclk, int srate)
0454 {
0455     int i;
0456 
0457     for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
0458         if (cs35l35_clk_ctl[i].sysclk == sysclk &&
0459             cs35l35_clk_ctl[i].srate == srate)
0460             return cs35l35_clk_ctl[i].clk_cfg;
0461     }
0462     return -EINVAL;
0463 }
0464 
0465 static int cs35l35_hw_params(struct snd_pcm_substream *substream,
0466                  struct snd_pcm_hw_params *params,
0467                  struct snd_soc_dai *dai)
0468 {
0469     struct snd_soc_component *component = dai->component;
0470     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0471     struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
0472     int srate = params_rate(params);
0473     int ret = 0;
0474     u8 sp_sclks;
0475     int audin_format;
0476     int errata_chk;
0477 
0478     int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
0479 
0480     if (clk_ctl < 0) {
0481         dev_err(component->dev, "Invalid CLK:Rate %d:%d\n",
0482             cs35l35->sysclk, srate);
0483         return -EINVAL;
0484     }
0485 
0486     ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
0487               CS35L35_CLK_CTL2_MASK, clk_ctl);
0488     if (ret != 0) {
0489         dev_err(component->dev, "Failed to set port config %d\n", ret);
0490         return ret;
0491     }
0492 
0493     /*
0494      * Rev A0 Errata
0495      * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
0496      * the Class H algorithm does not enable weak-drive operation for
0497      * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
0498      */
0499     errata_chk = (clk_ctl & CS35L35_SP_RATE_MASK) >> CS35L35_SP_RATE_SHIFT;
0500 
0501     if (classh->classh_wk_fet_disable == 0x00 &&
0502         (errata_chk == 0x01 || errata_chk == 0x02)) {
0503         ret = regmap_update_bits(cs35l35->regmap,
0504                     CS35L35_CLASS_H_FET_DRIVE_CTL,
0505                     CS35L35_CH_WKFET_DEL_MASK,
0506                     0 << CS35L35_CH_WKFET_DEL_SHIFT);
0507         if (ret != 0) {
0508             dev_err(component->dev, "Failed to set fet config %d\n",
0509                 ret);
0510             return ret;
0511         }
0512     }
0513 
0514     /*
0515      * You can pull more Monitor data from the SDOUT pin than going to SDIN
0516      * Just make sure your SCLK is fast enough to fill the frame
0517      */
0518     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0519         switch (params_width(params)) {
0520         case 8:
0521             audin_format = CS35L35_SDIN_DEPTH_8;
0522             break;
0523         case 16:
0524             audin_format = CS35L35_SDIN_DEPTH_16;
0525             break;
0526         case 24:
0527             audin_format = CS35L35_SDIN_DEPTH_24;
0528             break;
0529         default:
0530             dev_err(component->dev, "Unsupported Width %d\n",
0531                 params_width(params));
0532             return -EINVAL;
0533         }
0534         regmap_update_bits(cs35l35->regmap,
0535                 CS35L35_AUDIN_DEPTH_CTL,
0536                 CS35L35_AUDIN_DEPTH_MASK,
0537                 audin_format <<
0538                 CS35L35_AUDIN_DEPTH_SHIFT);
0539         if (cs35l35->pdata.stereo) {
0540             regmap_update_bits(cs35l35->regmap,
0541                     CS35L35_AUDIN_DEPTH_CTL,
0542                     CS35L35_ADVIN_DEPTH_MASK,
0543                     audin_format <<
0544                     CS35L35_ADVIN_DEPTH_SHIFT);
0545         }
0546     }
0547 
0548     if (cs35l35->i2s_mode) {
0549         /* We have to take the SCLK to derive num sclks
0550          * to configure the CLOCK_CTL3 register correctly
0551          */
0552         if ((cs35l35->sclk / srate) % 4) {
0553             dev_err(component->dev, "Unsupported sclk/fs ratio %d:%d\n",
0554                     cs35l35->sclk, srate);
0555             return -EINVAL;
0556         }
0557         sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
0558 
0559         /* Only certain ratios supported when device is a clock consumer */
0560         if (cs35l35->clock_consumer) {
0561             switch (sp_sclks) {
0562             case CS35L35_SP_SCLKS_32FS:
0563             case CS35L35_SP_SCLKS_48FS:
0564             case CS35L35_SP_SCLKS_64FS:
0565                 break;
0566             default:
0567                 dev_err(component->dev, "ratio not supported\n");
0568                 return -EINVAL;
0569             }
0570         } else {
0571             /* Only certain ratios supported when device is a clock provider */
0572             switch (sp_sclks) {
0573             case CS35L35_SP_SCLKS_32FS:
0574             case CS35L35_SP_SCLKS_64FS:
0575                 break;
0576             default:
0577                 dev_err(component->dev, "ratio not supported\n");
0578                 return -EINVAL;
0579             }
0580         }
0581         ret = regmap_update_bits(cs35l35->regmap,
0582                     CS35L35_CLK_CTL3,
0583                     CS35L35_SP_SCLKS_MASK, sp_sclks <<
0584                     CS35L35_SP_SCLKS_SHIFT);
0585         if (ret != 0) {
0586             dev_err(component->dev, "Failed to set fsclk %d\n", ret);
0587             return ret;
0588         }
0589     }
0590 
0591     return ret;
0592 }
0593 
0594 static const unsigned int cs35l35_src_rates[] = {
0595     44100, 48000, 88200, 96000, 176400, 192000
0596 };
0597 
0598 static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
0599     .count  = ARRAY_SIZE(cs35l35_src_rates),
0600     .list   = cs35l35_src_rates,
0601 };
0602 
0603 static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
0604                    struct snd_soc_dai *dai)
0605 {
0606     struct snd_soc_component *component = dai->component;
0607     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0608 
0609     if (!substream->runtime)
0610         return 0;
0611 
0612     snd_pcm_hw_constraint_list(substream->runtime, 0,
0613                 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
0614 
0615     regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
0616                     CS35L35_PDM_MODE_MASK,
0617                     0 << CS35L35_PDM_MODE_SHIFT);
0618 
0619     return 0;
0620 }
0621 
0622 static const unsigned int cs35l35_pdm_rates[] = {
0623     44100, 48000, 88200, 96000
0624 };
0625 
0626 static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
0627     .count  = ARRAY_SIZE(cs35l35_pdm_rates),
0628     .list   = cs35l35_pdm_rates,
0629 };
0630 
0631 static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
0632                    struct snd_soc_dai *dai)
0633 {
0634     struct snd_soc_component *component = dai->component;
0635     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0636 
0637     if (!substream->runtime)
0638         return 0;
0639 
0640     snd_pcm_hw_constraint_list(substream->runtime, 0,
0641                 SNDRV_PCM_HW_PARAM_RATE,
0642                 &cs35l35_pdm_constraints);
0643 
0644     regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
0645                     CS35L35_PDM_MODE_MASK,
0646                     1 << CS35L35_PDM_MODE_SHIFT);
0647 
0648     return 0;
0649 }
0650 
0651 static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
0652                 int clk_id, unsigned int freq, int dir)
0653 {
0654     struct snd_soc_component *component = dai->component;
0655     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0656 
0657     /* Need the SCLK Frequency regardless of sysclk source for I2S */
0658     cs35l35->sclk = freq;
0659 
0660     return 0;
0661 }
0662 
0663 static const struct snd_soc_dai_ops cs35l35_ops = {
0664     .startup = cs35l35_pcm_startup,
0665     .set_fmt = cs35l35_set_dai_fmt,
0666     .hw_params = cs35l35_hw_params,
0667     .set_sysclk = cs35l35_dai_set_sysclk,
0668 };
0669 
0670 static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
0671     .startup = cs35l35_pdm_startup,
0672     .set_fmt = cs35l35_set_dai_fmt,
0673     .hw_params = cs35l35_hw_params,
0674 };
0675 
0676 static struct snd_soc_dai_driver cs35l35_dai[] = {
0677     {
0678         .name = "cs35l35-pcm",
0679         .id = 0,
0680         .playback = {
0681             .stream_name = "AMP Playback",
0682             .channels_min = 1,
0683             .channels_max = 8,
0684             .rates = SNDRV_PCM_RATE_KNOT,
0685             .formats = CS35L35_FORMATS,
0686         },
0687         .capture = {
0688             .stream_name = "AMP Capture",
0689             .channels_min = 1,
0690             .channels_max = 8,
0691             .rates = SNDRV_PCM_RATE_KNOT,
0692             .formats = CS35L35_FORMATS,
0693         },
0694         .ops = &cs35l35_ops,
0695         .symmetric_rate = 1,
0696     },
0697     {
0698         .name = "cs35l35-pdm",
0699         .id = 1,
0700         .playback = {
0701             .stream_name = "PDM Playback",
0702             .channels_min = 1,
0703             .channels_max = 2,
0704             .rates = SNDRV_PCM_RATE_KNOT,
0705             .formats = CS35L35_FORMATS,
0706         },
0707         .ops = &cs35l35_pdm_ops,
0708     },
0709 };
0710 
0711 static int cs35l35_component_set_sysclk(struct snd_soc_component *component,
0712                 int clk_id, int source, unsigned int freq,
0713                 int dir)
0714 {
0715     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0716     int clksrc;
0717     int ret = 0;
0718 
0719     switch (clk_id) {
0720     case 0:
0721         clksrc = CS35L35_CLK_SOURCE_MCLK;
0722         break;
0723     case 1:
0724         clksrc = CS35L35_CLK_SOURCE_SCLK;
0725         break;
0726     case 2:
0727         clksrc = CS35L35_CLK_SOURCE_PDM;
0728         break;
0729     default:
0730         dev_err(component->dev, "Invalid CLK Source\n");
0731         return -EINVAL;
0732     }
0733 
0734     switch (freq) {
0735     case 5644800:
0736     case 6144000:
0737     case 11289600:
0738     case 12000000:
0739     case 12288000:
0740     case 13000000:
0741     case 22579200:
0742     case 24000000:
0743     case 24576000:
0744     case 26000000:
0745         cs35l35->sysclk = freq;
0746         break;
0747     default:
0748         dev_err(component->dev, "Invalid CLK Frequency Input : %d\n", freq);
0749         return -EINVAL;
0750     }
0751 
0752     ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0753                 CS35L35_CLK_SOURCE_MASK,
0754                 clksrc << CS35L35_CLK_SOURCE_SHIFT);
0755     if (ret != 0) {
0756         dev_err(component->dev, "Failed to set sysclk %d\n", ret);
0757         return ret;
0758     }
0759 
0760     return ret;
0761 }
0762 
0763 static int cs35l35_boost_inductor(struct cs35l35_private *cs35l35,
0764                   int inductor)
0765 {
0766     struct regmap *regmap = cs35l35->regmap;
0767     unsigned int bst_ipk = 0;
0768 
0769     /*
0770      * Digital Boost Converter Configuration for feedback,
0771      * ramping, switching frequency, and estimation block seeding.
0772      */
0773 
0774     regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
0775                CS35L35_BST_CONV_SWFREQ_MASK, 0x00);
0776 
0777     regmap_read(regmap, CS35L35_BST_PEAK_I, &bst_ipk);
0778     bst_ipk &= CS35L35_BST_IPK_MASK;
0779 
0780     switch (inductor) {
0781     case 1000: /* 1 uH */
0782         regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x24);
0783         regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x24);
0784         regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
0785                    CS35L35_BST_CONV_LBST_MASK, 0x00);
0786 
0787         if (bst_ipk < 0x04)
0788             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
0789         else
0790             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x4E);
0791         break;
0792     case 1200: /* 1.2 uH */
0793         regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
0794         regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
0795         regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
0796                    CS35L35_BST_CONV_LBST_MASK, 0x01);
0797 
0798         if (bst_ipk < 0x04)
0799             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
0800         else
0801             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x47);
0802         break;
0803     case 1500: /* 1.5uH */
0804         regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x20);
0805         regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x20);
0806         regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
0807                    CS35L35_BST_CONV_LBST_MASK, 0x02);
0808 
0809         if (bst_ipk < 0x04)
0810             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
0811         else
0812             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x3C);
0813         break;
0814     case 2200: /* 2.2uH */
0815         regmap_write(regmap, CS35L35_BST_CONV_COEF_1, 0x19);
0816         regmap_write(regmap, CS35L35_BST_CONV_COEF_2, 0x25);
0817         regmap_update_bits(regmap, CS35L35_BST_CONV_SW_FREQ,
0818                    CS35L35_BST_CONV_LBST_MASK, 0x03);
0819 
0820         if (bst_ipk < 0x04)
0821             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x1B);
0822         else
0823             regmap_write(regmap, CS35L35_BST_CONV_SLOPE_COMP, 0x23);
0824         break;
0825     default:
0826         dev_err(cs35l35->dev, "Invalid Inductor Value %d uH\n",
0827             inductor);
0828         return -EINVAL;
0829     }
0830     return 0;
0831 }
0832 
0833 static int cs35l35_component_probe(struct snd_soc_component *component)
0834 {
0835     struct cs35l35_private *cs35l35 = snd_soc_component_get_drvdata(component);
0836     struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
0837     struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
0838     int ret;
0839 
0840     /* Set Platform Data */
0841     if (cs35l35->pdata.bst_vctl)
0842         regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
0843                 CS35L35_BST_CTL_MASK,
0844                 cs35l35->pdata.bst_vctl);
0845 
0846     if (cs35l35->pdata.bst_ipk)
0847         regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
0848                 CS35L35_BST_IPK_MASK,
0849                 cs35l35->pdata.bst_ipk <<
0850                 CS35L35_BST_IPK_SHIFT);
0851 
0852     ret = cs35l35_boost_inductor(cs35l35, cs35l35->pdata.boost_ind);
0853     if (ret)
0854         return ret;
0855 
0856     if (cs35l35->pdata.gain_zc)
0857         regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
0858                 CS35L35_AMP_GAIN_ZC_MASK,
0859                 cs35l35->pdata.gain_zc <<
0860                 CS35L35_AMP_GAIN_ZC_SHIFT);
0861 
0862     if (cs35l35->pdata.aud_channel)
0863         regmap_update_bits(cs35l35->regmap,
0864                 CS35L35_AUDIN_RXLOC_CTL,
0865                 CS35L35_AUD_IN_LR_MASK,
0866                 cs35l35->pdata.aud_channel <<
0867                 CS35L35_AUD_IN_LR_SHIFT);
0868 
0869     if (cs35l35->pdata.stereo) {
0870         regmap_update_bits(cs35l35->regmap,
0871                 CS35L35_ADVIN_RXLOC_CTL,
0872                 CS35L35_ADV_IN_LR_MASK,
0873                 cs35l35->pdata.adv_channel <<
0874                 CS35L35_ADV_IN_LR_SHIFT);
0875         if (cs35l35->pdata.shared_bst)
0876             regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
0877                     CS35L35_CH_STEREO_MASK,
0878                     1 << CS35L35_CH_STEREO_SHIFT);
0879         ret = snd_soc_add_component_controls(component, cs35l35_adv_controls,
0880                     ARRAY_SIZE(cs35l35_adv_controls));
0881         if (ret)
0882             return ret;
0883     }
0884 
0885     if (cs35l35->pdata.sp_drv_str)
0886         regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
0887                 CS35L35_SP_DRV_MASK,
0888                 cs35l35->pdata.sp_drv_str <<
0889                 CS35L35_SP_DRV_SHIFT);
0890     if (cs35l35->pdata.sp_drv_unused)
0891         regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
0892                    CS35L35_SP_I2S_DRV_MASK,
0893                    cs35l35->pdata.sp_drv_unused <<
0894                    CS35L35_SP_I2S_DRV_SHIFT);
0895 
0896     if (classh->classh_algo_enable) {
0897         if (classh->classh_bst_override)
0898             regmap_update_bits(cs35l35->regmap,
0899                     CS35L35_CLASS_H_CTL,
0900                     CS35L35_CH_BST_OVR_MASK,
0901                     classh->classh_bst_override <<
0902                     CS35L35_CH_BST_OVR_SHIFT);
0903         if (classh->classh_bst_max_limit)
0904             regmap_update_bits(cs35l35->regmap,
0905                     CS35L35_CLASS_H_CTL,
0906                     CS35L35_CH_BST_LIM_MASK,
0907                     classh->classh_bst_max_limit <<
0908                     CS35L35_CH_BST_LIM_SHIFT);
0909         if (classh->classh_mem_depth)
0910             regmap_update_bits(cs35l35->regmap,
0911                     CS35L35_CLASS_H_CTL,
0912                     CS35L35_CH_MEM_DEPTH_MASK,
0913                     classh->classh_mem_depth <<
0914                     CS35L35_CH_MEM_DEPTH_SHIFT);
0915         if (classh->classh_headroom)
0916             regmap_update_bits(cs35l35->regmap,
0917                     CS35L35_CLASS_H_HEADRM_CTL,
0918                     CS35L35_CH_HDRM_CTL_MASK,
0919                     classh->classh_headroom <<
0920                     CS35L35_CH_HDRM_CTL_SHIFT);
0921         if (classh->classh_release_rate)
0922             regmap_update_bits(cs35l35->regmap,
0923                     CS35L35_CLASS_H_RELEASE_RATE,
0924                     CS35L35_CH_REL_RATE_MASK,
0925                     classh->classh_release_rate <<
0926                     CS35L35_CH_REL_RATE_SHIFT);
0927         if (classh->classh_wk_fet_disable)
0928             regmap_update_bits(cs35l35->regmap,
0929                     CS35L35_CLASS_H_FET_DRIVE_CTL,
0930                     CS35L35_CH_WKFET_DIS_MASK,
0931                     classh->classh_wk_fet_disable <<
0932                     CS35L35_CH_WKFET_DIS_SHIFT);
0933         if (classh->classh_wk_fet_delay)
0934             regmap_update_bits(cs35l35->regmap,
0935                     CS35L35_CLASS_H_FET_DRIVE_CTL,
0936                     CS35L35_CH_WKFET_DEL_MASK,
0937                     classh->classh_wk_fet_delay <<
0938                     CS35L35_CH_WKFET_DEL_SHIFT);
0939         if (classh->classh_wk_fet_thld)
0940             regmap_update_bits(cs35l35->regmap,
0941                     CS35L35_CLASS_H_FET_DRIVE_CTL,
0942                     CS35L35_CH_WKFET_THLD_MASK,
0943                     classh->classh_wk_fet_thld <<
0944                     CS35L35_CH_WKFET_THLD_SHIFT);
0945         if (classh->classh_vpch_auto)
0946             regmap_update_bits(cs35l35->regmap,
0947                     CS35L35_CLASS_H_VP_CTL,
0948                     CS35L35_CH_VP_AUTO_MASK,
0949                     classh->classh_vpch_auto <<
0950                     CS35L35_CH_VP_AUTO_SHIFT);
0951         if (classh->classh_vpch_rate)
0952             regmap_update_bits(cs35l35->regmap,
0953                     CS35L35_CLASS_H_VP_CTL,
0954                     CS35L35_CH_VP_RATE_MASK,
0955                     classh->classh_vpch_rate <<
0956                     CS35L35_CH_VP_RATE_SHIFT);
0957         if (classh->classh_vpch_man)
0958             regmap_update_bits(cs35l35->regmap,
0959                     CS35L35_CLASS_H_VP_CTL,
0960                     CS35L35_CH_VP_MAN_MASK,
0961                     classh->classh_vpch_man <<
0962                     CS35L35_CH_VP_MAN_SHIFT);
0963     }
0964 
0965     if (monitor_config->is_present) {
0966         if (monitor_config->vmon_specs) {
0967             regmap_update_bits(cs35l35->regmap,
0968                     CS35L35_SPKMON_DEPTH_CTL,
0969                     CS35L35_VMON_DEPTH_MASK,
0970                     monitor_config->vmon_dpth <<
0971                     CS35L35_VMON_DEPTH_SHIFT);
0972             regmap_update_bits(cs35l35->regmap,
0973                     CS35L35_VMON_TXLOC_CTL,
0974                     CS35L35_MON_TXLOC_MASK,
0975                     monitor_config->vmon_loc <<
0976                     CS35L35_MON_TXLOC_SHIFT);
0977             regmap_update_bits(cs35l35->regmap,
0978                     CS35L35_VMON_TXLOC_CTL,
0979                     CS35L35_MON_FRM_MASK,
0980                     monitor_config->vmon_frm <<
0981                     CS35L35_MON_FRM_SHIFT);
0982         }
0983         if (monitor_config->imon_specs) {
0984             regmap_update_bits(cs35l35->regmap,
0985                     CS35L35_SPKMON_DEPTH_CTL,
0986                     CS35L35_IMON_DEPTH_MASK,
0987                     monitor_config->imon_dpth <<
0988                     CS35L35_IMON_DEPTH_SHIFT);
0989             regmap_update_bits(cs35l35->regmap,
0990                     CS35L35_IMON_TXLOC_CTL,
0991                     CS35L35_MON_TXLOC_MASK,
0992                     monitor_config->imon_loc <<
0993                     CS35L35_MON_TXLOC_SHIFT);
0994             regmap_update_bits(cs35l35->regmap,
0995                     CS35L35_IMON_TXLOC_CTL,
0996                     CS35L35_MON_FRM_MASK,
0997                     monitor_config->imon_frm <<
0998                     CS35L35_MON_FRM_SHIFT);
0999             regmap_update_bits(cs35l35->regmap,
1000                     CS35L35_IMON_SCALE_CTL,
1001                     CS35L35_IMON_SCALE_MASK,
1002                     monitor_config->imon_scale <<
1003                     CS35L35_IMON_SCALE_SHIFT);
1004         }
1005         if (monitor_config->vpmon_specs) {
1006             regmap_update_bits(cs35l35->regmap,
1007                     CS35L35_SUPMON_DEPTH_CTL,
1008                     CS35L35_VPMON_DEPTH_MASK,
1009                     monitor_config->vpmon_dpth <<
1010                     CS35L35_VPMON_DEPTH_SHIFT);
1011             regmap_update_bits(cs35l35->regmap,
1012                     CS35L35_VPMON_TXLOC_CTL,
1013                     CS35L35_MON_TXLOC_MASK,
1014                     monitor_config->vpmon_loc <<
1015                     CS35L35_MON_TXLOC_SHIFT);
1016             regmap_update_bits(cs35l35->regmap,
1017                     CS35L35_VPMON_TXLOC_CTL,
1018                     CS35L35_MON_FRM_MASK,
1019                     monitor_config->vpmon_frm <<
1020                     CS35L35_MON_FRM_SHIFT);
1021         }
1022         if (monitor_config->vbstmon_specs) {
1023             regmap_update_bits(cs35l35->regmap,
1024                     CS35L35_SUPMON_DEPTH_CTL,
1025                     CS35L35_VBSTMON_DEPTH_MASK,
1026                     monitor_config->vpmon_dpth <<
1027                     CS35L35_VBSTMON_DEPTH_SHIFT);
1028             regmap_update_bits(cs35l35->regmap,
1029                     CS35L35_VBSTMON_TXLOC_CTL,
1030                     CS35L35_MON_TXLOC_MASK,
1031                     monitor_config->vbstmon_loc <<
1032                     CS35L35_MON_TXLOC_SHIFT);
1033             regmap_update_bits(cs35l35->regmap,
1034                     CS35L35_VBSTMON_TXLOC_CTL,
1035                     CS35L35_MON_FRM_MASK,
1036                     monitor_config->vbstmon_frm <<
1037                     CS35L35_MON_FRM_SHIFT);
1038         }
1039         if (monitor_config->vpbrstat_specs) {
1040             regmap_update_bits(cs35l35->regmap,
1041                     CS35L35_SUPMON_DEPTH_CTL,
1042                     CS35L35_VPBRSTAT_DEPTH_MASK,
1043                     monitor_config->vpbrstat_dpth <<
1044                     CS35L35_VPBRSTAT_DEPTH_SHIFT);
1045             regmap_update_bits(cs35l35->regmap,
1046                     CS35L35_VPBR_STATUS_TXLOC_CTL,
1047                     CS35L35_MON_TXLOC_MASK,
1048                     monitor_config->vpbrstat_loc <<
1049                     CS35L35_MON_TXLOC_SHIFT);
1050             regmap_update_bits(cs35l35->regmap,
1051                     CS35L35_VPBR_STATUS_TXLOC_CTL,
1052                     CS35L35_MON_FRM_MASK,
1053                     monitor_config->vpbrstat_frm <<
1054                     CS35L35_MON_FRM_SHIFT);
1055         }
1056         if (monitor_config->zerofill_specs) {
1057             regmap_update_bits(cs35l35->regmap,
1058                     CS35L35_SUPMON_DEPTH_CTL,
1059                     CS35L35_ZEROFILL_DEPTH_MASK,
1060                     monitor_config->zerofill_dpth <<
1061                     CS35L35_ZEROFILL_DEPTH_SHIFT);
1062             regmap_update_bits(cs35l35->regmap,
1063                     CS35L35_ZERO_FILL_LOC_CTL,
1064                     CS35L35_MON_TXLOC_MASK,
1065                     monitor_config->zerofill_loc <<
1066                     CS35L35_MON_TXLOC_SHIFT);
1067             regmap_update_bits(cs35l35->regmap,
1068                     CS35L35_ZERO_FILL_LOC_CTL,
1069                     CS35L35_MON_FRM_MASK,
1070                     monitor_config->zerofill_frm <<
1071                     CS35L35_MON_FRM_SHIFT);
1072         }
1073     }
1074 
1075     return 0;
1076 }
1077 
1078 static const struct snd_soc_component_driver soc_component_dev_cs35l35 = {
1079     .probe          = cs35l35_component_probe,
1080     .set_sysclk     = cs35l35_component_set_sysclk,
1081     .dapm_widgets       = cs35l35_dapm_widgets,
1082     .num_dapm_widgets   = ARRAY_SIZE(cs35l35_dapm_widgets),
1083     .dapm_routes        = cs35l35_audio_map,
1084     .num_dapm_routes    = ARRAY_SIZE(cs35l35_audio_map),
1085     .controls       = cs35l35_aud_controls,
1086     .num_controls       = ARRAY_SIZE(cs35l35_aud_controls),
1087     .idle_bias_on       = 1,
1088     .use_pmdown_time    = 1,
1089     .endianness     = 1,
1090 };
1091 
1092 static struct regmap_config cs35l35_regmap = {
1093     .reg_bits = 8,
1094     .val_bits = 8,
1095 
1096     .max_register = CS35L35_MAX_REGISTER,
1097     .reg_defaults = cs35l35_reg,
1098     .num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
1099     .volatile_reg = cs35l35_volatile_register,
1100     .readable_reg = cs35l35_readable_register,
1101     .precious_reg = cs35l35_precious_register,
1102     .cache_type = REGCACHE_RBTREE,
1103     .use_single_read = true,
1104     .use_single_write = true,
1105 };
1106 
1107 static irqreturn_t cs35l35_irq(int irq, void *data)
1108 {
1109     struct cs35l35_private *cs35l35 = data;
1110     unsigned int sticky1, sticky2, sticky3, sticky4;
1111     unsigned int mask1, mask2, mask3, mask4, current1;
1112 
1113     /* ack the irq by reading all status registers */
1114     regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
1115     regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
1116     regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
1117     regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
1118 
1119     regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
1120     regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
1121     regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
1122     regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
1123 
1124     /* Check to see if unmasked bits are active */
1125     if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
1126             && !(sticky4 & ~mask4))
1127         return IRQ_NONE;
1128 
1129     if (sticky2 & CS35L35_PDN_DONE)
1130         complete(&cs35l35->pdn_done);
1131 
1132     /* read the current values */
1133     regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &current1);
1134 
1135     /* handle the interrupts */
1136     if (sticky1 & CS35L35_CAL_ERR) {
1137         dev_crit(cs35l35->dev, "Calibration Error\n");
1138 
1139         /* error is no longer asserted; safe to reset */
1140         if (!(current1 & CS35L35_CAL_ERR)) {
1141             pr_debug("%s : Cal error release\n", __func__);
1142             regmap_update_bits(cs35l35->regmap,
1143                     CS35L35_PROT_RELEASE_CTL,
1144                     CS35L35_CAL_ERR_RLS, 0);
1145             regmap_update_bits(cs35l35->regmap,
1146                     CS35L35_PROT_RELEASE_CTL,
1147                     CS35L35_CAL_ERR_RLS,
1148                     CS35L35_CAL_ERR_RLS);
1149             regmap_update_bits(cs35l35->regmap,
1150                     CS35L35_PROT_RELEASE_CTL,
1151                     CS35L35_CAL_ERR_RLS, 0);
1152         }
1153     }
1154 
1155     if (sticky1 & CS35L35_AMP_SHORT) {
1156         dev_crit(cs35l35->dev, "AMP Short Error\n");
1157         /* error is no longer asserted; safe to reset */
1158         if (!(current1 & CS35L35_AMP_SHORT)) {
1159             dev_dbg(cs35l35->dev, "Amp short error release\n");
1160             regmap_update_bits(cs35l35->regmap,
1161                     CS35L35_PROT_RELEASE_CTL,
1162                     CS35L35_SHORT_RLS, 0);
1163             regmap_update_bits(cs35l35->regmap,
1164                     CS35L35_PROT_RELEASE_CTL,
1165                     CS35L35_SHORT_RLS,
1166                     CS35L35_SHORT_RLS);
1167             regmap_update_bits(cs35l35->regmap,
1168                     CS35L35_PROT_RELEASE_CTL,
1169                     CS35L35_SHORT_RLS, 0);
1170         }
1171     }
1172 
1173     if (sticky1 & CS35L35_OTW) {
1174         dev_warn(cs35l35->dev, "Over temperature warning\n");
1175 
1176         /* error is no longer asserted; safe to reset */
1177         if (!(current1 & CS35L35_OTW)) {
1178             dev_dbg(cs35l35->dev, "Over temperature warn release\n");
1179             regmap_update_bits(cs35l35->regmap,
1180                     CS35L35_PROT_RELEASE_CTL,
1181                     CS35L35_OTW_RLS, 0);
1182             regmap_update_bits(cs35l35->regmap,
1183                     CS35L35_PROT_RELEASE_CTL,
1184                     CS35L35_OTW_RLS,
1185                     CS35L35_OTW_RLS);
1186             regmap_update_bits(cs35l35->regmap,
1187                     CS35L35_PROT_RELEASE_CTL,
1188                     CS35L35_OTW_RLS, 0);
1189         }
1190     }
1191 
1192     if (sticky1 & CS35L35_OTE) {
1193         dev_crit(cs35l35->dev, "Over temperature error\n");
1194         /* error is no longer asserted; safe to reset */
1195         if (!(current1 & CS35L35_OTE)) {
1196             dev_dbg(cs35l35->dev, "Over temperature error release\n");
1197             regmap_update_bits(cs35l35->regmap,
1198                     CS35L35_PROT_RELEASE_CTL,
1199                     CS35L35_OTE_RLS, 0);
1200             regmap_update_bits(cs35l35->regmap,
1201                     CS35L35_PROT_RELEASE_CTL,
1202                     CS35L35_OTE_RLS,
1203                     CS35L35_OTE_RLS);
1204             regmap_update_bits(cs35l35->regmap,
1205                     CS35L35_PROT_RELEASE_CTL,
1206                     CS35L35_OTE_RLS, 0);
1207         }
1208     }
1209 
1210     if (sticky3 & CS35L35_BST_HIGH) {
1211         dev_crit(cs35l35->dev, "VBST error: powering off!\n");
1212         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1213             CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1214         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1215             CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1216     }
1217 
1218     if (sticky3 & CS35L35_LBST_SHORT) {
1219         dev_crit(cs35l35->dev, "LBST error: powering off!\n");
1220         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1221             CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1222         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1223             CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1224     }
1225 
1226     if (sticky2 & CS35L35_VPBR_ERR)
1227         dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n");
1228 
1229     if (sticky4 & CS35L35_VMON_OVFL)
1230         dev_dbg(cs35l35->dev, "Error: VMON overflow\n");
1231 
1232     if (sticky4 & CS35L35_IMON_OVFL)
1233         dev_dbg(cs35l35->dev, "Error: IMON overflow\n");
1234 
1235     return IRQ_HANDLED;
1236 }
1237 
1238 
1239 static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
1240                 struct cs35l35_platform_data *pdata)
1241 {
1242     struct device_node *np = i2c_client->dev.of_node;
1243     struct device_node *classh, *signal_format;
1244     struct classh_cfg *classh_config = &pdata->classh_algo;
1245     struct monitor_cfg *monitor_config = &pdata->mon_cfg;
1246     unsigned int val32 = 0;
1247     u8 monitor_array[4];
1248     const int imon_array_size = ARRAY_SIZE(monitor_array);
1249     const int mon_array_size = imon_array_size - 1;
1250     int ret = 0;
1251 
1252     if (!np)
1253         return 0;
1254 
1255     pdata->bst_pdn_fet_on = of_property_read_bool(np,
1256                     "cirrus,boost-pdn-fet-on");
1257 
1258     ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
1259     if (ret >= 0) {
1260         if (val32 < 2600 || val32 > 9000) {
1261             dev_err(&i2c_client->dev,
1262                 "Invalid Boost Voltage %d mV\n", val32);
1263             return -EINVAL;
1264         }
1265         pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
1266     }
1267 
1268     ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
1269     if (ret >= 0) {
1270         if (val32 < 1680 || val32 > 4480) {
1271             dev_err(&i2c_client->dev,
1272                 "Invalid Boost Peak Current %u mA\n", val32);
1273             return -EINVAL;
1274         }
1275 
1276         pdata->bst_ipk = ((val32 - 1680) / 110) | CS35L35_VALID_PDATA;
1277     }
1278 
1279     ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val32);
1280     if (ret >= 0) {
1281         pdata->boost_ind = val32;
1282     } else {
1283         dev_err(&i2c_client->dev, "Inductor not specified.\n");
1284         return -EINVAL;
1285     }
1286 
1287     if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
1288         pdata->sp_drv_str = val32;
1289     if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
1290         pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
1291 
1292     pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
1293 
1294     if (pdata->stereo) {
1295         ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
1296         if (ret >= 0)
1297             pdata->aud_channel = val32;
1298 
1299         ret = of_property_read_u32(np, "cirrus,advisory-channel",
1300                        &val32);
1301         if (ret >= 0)
1302             pdata->adv_channel = val32;
1303 
1304         pdata->shared_bst = of_property_read_bool(np,
1305                         "cirrus,shared-boost");
1306     }
1307 
1308     pdata->ext_bst = of_property_read_bool(np, "cirrus,external-boost");
1309 
1310     pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
1311 
1312     classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
1313     classh_config->classh_algo_enable = (classh != NULL);
1314 
1315     if (classh_config->classh_algo_enable) {
1316         classh_config->classh_bst_override =
1317             of_property_read_bool(np, "cirrus,classh-bst-overide");
1318 
1319         ret = of_property_read_u32(classh,
1320                        "cirrus,classh-bst-max-limit",
1321                        &val32);
1322         if (ret >= 0) {
1323             val32 |= CS35L35_VALID_PDATA;
1324             classh_config->classh_bst_max_limit = val32;
1325         }
1326 
1327         ret = of_property_read_u32(classh,
1328                        "cirrus,classh-bst-max-limit",
1329                        &val32);
1330         if (ret >= 0) {
1331             val32 |= CS35L35_VALID_PDATA;
1332             classh_config->classh_bst_max_limit = val32;
1333         }
1334 
1335         ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
1336                        &val32);
1337         if (ret >= 0) {
1338             val32 |= CS35L35_VALID_PDATA;
1339             classh_config->classh_mem_depth = val32;
1340         }
1341 
1342         ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
1343                        &val32);
1344         if (ret >= 0)
1345             classh_config->classh_release_rate = val32;
1346 
1347         ret = of_property_read_u32(classh, "cirrus,classh-headroom",
1348                        &val32);
1349         if (ret >= 0) {
1350             val32 |= CS35L35_VALID_PDATA;
1351             classh_config->classh_headroom = val32;
1352         }
1353 
1354         ret = of_property_read_u32(classh,
1355                        "cirrus,classh-wk-fet-disable",
1356                        &val32);
1357         if (ret >= 0)
1358             classh_config->classh_wk_fet_disable = val32;
1359 
1360         ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
1361                        &val32);
1362         if (ret >= 0) {
1363             val32 |= CS35L35_VALID_PDATA;
1364             classh_config->classh_wk_fet_delay = val32;
1365         }
1366 
1367         ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
1368                        &val32);
1369         if (ret >= 0)
1370             classh_config->classh_wk_fet_thld = val32;
1371 
1372         ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
1373                        &val32);
1374         if (ret >= 0) {
1375             val32 |= CS35L35_VALID_PDATA;
1376             classh_config->classh_vpch_auto = val32;
1377         }
1378 
1379         ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
1380                        &val32);
1381         if (ret >= 0) {
1382             val32 |= CS35L35_VALID_PDATA;
1383             classh_config->classh_vpch_rate = val32;
1384         }
1385 
1386         ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
1387                        &val32);
1388         if (ret >= 0)
1389             classh_config->classh_vpch_man = val32;
1390     }
1391     of_node_put(classh);
1392 
1393     /* frame depth location */
1394     signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
1395     monitor_config->is_present = signal_format ? true : false;
1396     if (monitor_config->is_present) {
1397         ret = of_property_read_u8_array(signal_format, "cirrus,imon",
1398                         monitor_array, imon_array_size);
1399         if (!ret) {
1400             monitor_config->imon_specs = true;
1401             monitor_config->imon_dpth = monitor_array[0];
1402             monitor_config->imon_loc = monitor_array[1];
1403             monitor_config->imon_frm = monitor_array[2];
1404             monitor_config->imon_scale = monitor_array[3];
1405         }
1406         ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
1407                         monitor_array, mon_array_size);
1408         if (!ret) {
1409             monitor_config->vmon_specs = true;
1410             monitor_config->vmon_dpth = monitor_array[0];
1411             monitor_config->vmon_loc = monitor_array[1];
1412             monitor_config->vmon_frm = monitor_array[2];
1413         }
1414         ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
1415                         monitor_array, mon_array_size);
1416         if (!ret) {
1417             monitor_config->vpmon_specs = true;
1418             monitor_config->vpmon_dpth = monitor_array[0];
1419             monitor_config->vpmon_loc = monitor_array[1];
1420             monitor_config->vpmon_frm = monitor_array[2];
1421         }
1422         ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
1423                         monitor_array, mon_array_size);
1424         if (!ret) {
1425             monitor_config->vbstmon_specs = true;
1426             monitor_config->vbstmon_dpth = monitor_array[0];
1427             monitor_config->vbstmon_loc = monitor_array[1];
1428             monitor_config->vbstmon_frm = monitor_array[2];
1429         }
1430         ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
1431                         monitor_array, mon_array_size);
1432         if (!ret) {
1433             monitor_config->vpbrstat_specs = true;
1434             monitor_config->vpbrstat_dpth = monitor_array[0];
1435             monitor_config->vpbrstat_loc = monitor_array[1];
1436             monitor_config->vpbrstat_frm = monitor_array[2];
1437         }
1438         ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
1439                         monitor_array, mon_array_size);
1440         if (!ret) {
1441             monitor_config->zerofill_specs = true;
1442             monitor_config->zerofill_dpth = monitor_array[0];
1443             monitor_config->zerofill_loc = monitor_array[1];
1444             monitor_config->zerofill_frm = monitor_array[2];
1445         }
1446     }
1447     of_node_put(signal_format);
1448 
1449     return 0;
1450 }
1451 
1452 /* Errata Rev A0 */
1453 static const struct reg_sequence cs35l35_errata_patch[] = {
1454 
1455     { 0x7F, 0x99 },
1456     { 0x00, 0x99 },
1457     { 0x52, 0x22 },
1458     { 0x04, 0x14 },
1459     { 0x6D, 0x44 },
1460     { 0x24, 0x10 },
1461     { 0x58, 0xC4 },
1462     { 0x00, 0x98 },
1463     { 0x18, 0x08 },
1464     { 0x00, 0x00 },
1465     { 0x7F, 0x00 },
1466 };
1467 
1468 static int cs35l35_i2c_probe(struct i2c_client *i2c_client)
1469 {
1470     struct cs35l35_private *cs35l35;
1471     struct device *dev = &i2c_client->dev;
1472     struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
1473     int i, devid;
1474     int ret;
1475     unsigned int reg;
1476 
1477     cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
1478     if (!cs35l35)
1479         return -ENOMEM;
1480 
1481     cs35l35->dev = dev;
1482 
1483     i2c_set_clientdata(i2c_client, cs35l35);
1484     cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
1485     if (IS_ERR(cs35l35->regmap)) {
1486         ret = PTR_ERR(cs35l35->regmap);
1487         dev_err(dev, "regmap_init() failed: %d\n", ret);
1488         return ret;
1489     }
1490 
1491     for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
1492         cs35l35->supplies[i].supply = cs35l35_supplies[i];
1493 
1494     cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
1495 
1496     ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
1497                       cs35l35->supplies);
1498     if (ret != 0) {
1499         dev_err(dev, "Failed to request core supplies: %d\n", ret);
1500         return ret;
1501     }
1502 
1503     if (pdata) {
1504         cs35l35->pdata = *pdata;
1505     } else {
1506         pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
1507                      GFP_KERNEL);
1508         if (!pdata)
1509             return -ENOMEM;
1510         if (i2c_client->dev.of_node) {
1511             ret = cs35l35_handle_of_data(i2c_client, pdata);
1512             if (ret != 0)
1513                 return ret;
1514 
1515         }
1516         cs35l35->pdata = *pdata;
1517     }
1518 
1519     ret = regulator_bulk_enable(cs35l35->num_supplies,
1520                     cs35l35->supplies);
1521     if (ret != 0) {
1522         dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1523         return ret;
1524     }
1525 
1526     /* returning NULL can be valid if in stereo mode */
1527     cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1528                               GPIOD_OUT_LOW);
1529     if (IS_ERR(cs35l35->reset_gpio)) {
1530         ret = PTR_ERR(cs35l35->reset_gpio);
1531         cs35l35->reset_gpio = NULL;
1532         if (ret == -EBUSY) {
1533             dev_info(dev,
1534                  "Reset line busy, assuming shared reset\n");
1535         } else {
1536             dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1537             goto err;
1538         }
1539     }
1540 
1541     cs35l35_reset(cs35l35);
1542 
1543     init_completion(&cs35l35->pdn_done);
1544 
1545     ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
1546                     IRQF_ONESHOT | IRQF_TRIGGER_LOW |
1547                     IRQF_SHARED, "cs35l35", cs35l35);
1548     if (ret != 0) {
1549         dev_err(dev, "Failed to request IRQ: %d\n", ret);
1550         goto err;
1551     }
1552     /* initialize codec */
1553     devid = cirrus_read_device_id(cs35l35->regmap, CS35L35_DEVID_AB);
1554     if (devid < 0) {
1555         ret = devid;
1556         dev_err(dev, "Failed to read device ID: %d\n", ret);
1557         goto err;
1558     }
1559 
1560     if (devid != CS35L35_CHIP_ID) {
1561         dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
1562             devid, CS35L35_CHIP_ID);
1563         ret = -ENODEV;
1564         goto err;
1565     }
1566 
1567     ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, &reg);
1568     if (ret < 0) {
1569         dev_err(dev, "Get Revision ID failed: %d\n", ret);
1570         goto err;
1571     }
1572 
1573     ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
1574                     ARRAY_SIZE(cs35l35_errata_patch));
1575     if (ret < 0) {
1576         dev_err(dev, "Failed to apply errata patch: %d\n", ret);
1577         goto err;
1578     }
1579 
1580     dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
1581          devid, reg & 0xFF);
1582 
1583     /* Set the INT Masks for critical errors */
1584     regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
1585                 CS35L35_INT1_CRIT_MASK);
1586     regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
1587                 CS35L35_INT2_CRIT_MASK);
1588     regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
1589                 CS35L35_INT3_CRIT_MASK);
1590     regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
1591                 CS35L35_INT4_CRIT_MASK);
1592 
1593     regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1594             CS35L35_PWR2_PDN_MASK,
1595             CS35L35_PWR2_PDN_MASK);
1596 
1597     if (cs35l35->pdata.bst_pdn_fet_on)
1598         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1599                     CS35L35_PDN_BST_MASK,
1600                     1 << CS35L35_PDN_BST_FETON_SHIFT);
1601     else
1602         regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1603                     CS35L35_PDN_BST_MASK,
1604                     1 << CS35L35_PDN_BST_FETOFF_SHIFT);
1605 
1606     regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
1607             CS35L35_PWR3_PDN_MASK,
1608             CS35L35_PWR3_PDN_MASK);
1609 
1610     regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
1611         CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
1612 
1613     ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l35,
1614                     cs35l35_dai, ARRAY_SIZE(cs35l35_dai));
1615     if (ret < 0) {
1616         dev_err(dev, "Failed to register component: %d\n", ret);
1617         goto err;
1618     }
1619 
1620     return 0;
1621 
1622 err:
1623     regulator_bulk_disable(cs35l35->num_supplies,
1624                    cs35l35->supplies);
1625     gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1626 
1627     return ret;
1628 }
1629 
1630 static int cs35l35_i2c_remove(struct i2c_client *i2c_client)
1631 {
1632     struct cs35l35_private *cs35l35 = i2c_get_clientdata(i2c_client);
1633 
1634     regulator_bulk_disable(cs35l35->num_supplies, cs35l35->supplies);
1635     gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1636 
1637     return 0;
1638 }
1639 
1640 static const struct of_device_id cs35l35_of_match[] = {
1641     {.compatible = "cirrus,cs35l35"},
1642     {},
1643 };
1644 MODULE_DEVICE_TABLE(of, cs35l35_of_match);
1645 
1646 static const struct i2c_device_id cs35l35_id[] = {
1647     {"cs35l35", 0},
1648     {}
1649 };
1650 
1651 MODULE_DEVICE_TABLE(i2c, cs35l35_id);
1652 
1653 static struct i2c_driver cs35l35_i2c_driver = {
1654     .driver = {
1655         .name = "cs35l35",
1656         .of_match_table = cs35l35_of_match,
1657     },
1658     .id_table = cs35l35_id,
1659     .probe_new = cs35l35_i2c_probe,
1660     .remove = cs35l35_i2c_remove,
1661 };
1662 
1663 module_i2c_driver(cs35l35_i2c_driver);
1664 
1665 MODULE_DESCRIPTION("ASoC CS35L35 driver");
1666 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1667 MODULE_LICENSE("GPL");
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