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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cs35l34.c -- CS35l34 ALSA SoC audio driver
0004  *
0005  * Copyright 2016 Cirrus Logic, Inc.
0006  *
0007  * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/i2c.h>
0016 #include <linux/slab.h>
0017 #include <linux/workqueue.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/regulator/machine.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/of_device.h>
0023 #include <linux/of_gpio.h>
0024 #include <linux/of_irq.h>
0025 #include <sound/core.h>
0026 #include <sound/pcm.h>
0027 #include <sound/pcm_params.h>
0028 #include <sound/soc.h>
0029 #include <sound/soc-dapm.h>
0030 #include <linux/gpio.h>
0031 #include <linux/gpio/consumer.h>
0032 #include <sound/initval.h>
0033 #include <sound/tlv.h>
0034 #include <sound/cs35l34.h>
0035 
0036 #include "cs35l34.h"
0037 #include "cirrus_legacy.h"
0038 
0039 #define PDN_DONE_ATTEMPTS 10
0040 #define CS35L34_START_DELAY 50
0041 
0042 struct  cs35l34_private {
0043     struct snd_soc_component *component;
0044     struct cs35l34_platform_data pdata;
0045     struct regmap *regmap;
0046     struct regulator_bulk_data core_supplies[2];
0047     int num_core_supplies;
0048     int mclk_int;
0049     bool tdm_mode;
0050     struct gpio_desc *reset_gpio;   /* Active-low reset GPIO */
0051 };
0052 
0053 static const struct reg_default cs35l34_reg[] = {
0054     {CS35L34_PWRCTL1, 0x01},
0055     {CS35L34_PWRCTL2, 0x19},
0056     {CS35L34_PWRCTL3, 0x01},
0057     {CS35L34_ADSP_CLK_CTL, 0x08},
0058     {CS35L34_MCLK_CTL, 0x11},
0059     {CS35L34_AMP_INP_DRV_CTL, 0x01},
0060     {CS35L34_AMP_DIG_VOL_CTL, 0x12},
0061     {CS35L34_AMP_DIG_VOL, 0x00},
0062     {CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
0063     {CS35L34_PROTECT_CTL, 0x06},
0064     {CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
0065     {CS35L34_BST_CVTR_V_CTL, 0x00},
0066     {CS35L34_BST_PEAK_I, 0x10},
0067     {CS35L34_BST_RAMP_CTL, 0x87},
0068     {CS35L34_BST_CONV_COEF_1, 0x24},
0069     {CS35L34_BST_CONV_COEF_2, 0x24},
0070     {CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
0071     {CS35L34_BST_CONV_SW_FREQ, 0x08},
0072     {CS35L34_CLASS_H_CTL, 0x0D},
0073     {CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
0074     {CS35L34_CLASS_H_RELEASE_RATE, 0x08},
0075     {CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
0076     {CS35L34_CLASS_H_STATUS, 0x05},
0077     {CS35L34_VPBR_CTL, 0x0A},
0078     {CS35L34_VPBR_VOL_CTL, 0x90},
0079     {CS35L34_VPBR_TIMING_CTL, 0x6A},
0080     {CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
0081     {CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
0082     {CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
0083     {CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
0084     {CS35L34_PRED_WAIT_CTL, 0x10},
0085     {CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
0086     {CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
0087     {CS35L34_VPBR_ATTEN_STATUS, 0x00},
0088     {CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
0089     {CS35L34_SPKR_MON_CTL, 0xC6},
0090     {CS35L34_ADSP_I2S_CTL, 0x00},
0091     {CS35L34_ADSP_TDM_CTL, 0x00},
0092     {CS35L34_TDM_TX_CTL_1_VMON, 0x00},
0093     {CS35L34_TDM_TX_CTL_2_IMON, 0x04},
0094     {CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
0095     {CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
0096     {CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
0097     {CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
0098     {CS35L34_TDM_TX_SLOT_EN_1, 0x00},
0099     {CS35L34_TDM_TX_SLOT_EN_2, 0x00},
0100     {CS35L34_TDM_TX_SLOT_EN_3, 0x00},
0101     {CS35L34_TDM_TX_SLOT_EN_4, 0x00},
0102     {CS35L34_TDM_RX_CTL_1_AUDIN, 0x40},
0103     {CS35L34_TDM_RX_CTL_3_ALIVE, 0x04},
0104     {CS35L34_MULT_DEV_SYNCH1, 0x00},
0105     {CS35L34_MULT_DEV_SYNCH2, 0x80},
0106     {CS35L34_PROT_RELEASE_CTL, 0x00},
0107     {CS35L34_DIAG_MODE_REG_LOCK, 0x00},
0108     {CS35L34_DIAG_MODE_CTL_1, 0x00},
0109     {CS35L34_DIAG_MODE_CTL_2, 0x00},
0110     {CS35L34_INT_MASK_1, 0xFF},
0111     {CS35L34_INT_MASK_2, 0xFF},
0112     {CS35L34_INT_MASK_3, 0xFF},
0113     {CS35L34_INT_MASK_4, 0xFF},
0114     {CS35L34_INT_STATUS_1, 0x30},
0115     {CS35L34_INT_STATUS_2, 0x05},
0116     {CS35L34_INT_STATUS_3, 0x00},
0117     {CS35L34_INT_STATUS_4, 0x00},
0118     {CS35L34_OTP_TRIM_STATUS, 0x00},
0119 };
0120 
0121 static bool cs35l34_volatile_register(struct device *dev, unsigned int reg)
0122 {
0123     switch (reg) {
0124     case CS35L34_DEVID_AB:
0125     case CS35L34_DEVID_CD:
0126     case CS35L34_DEVID_E:
0127     case CS35L34_FAB_ID:
0128     case CS35L34_REV_ID:
0129     case CS35L34_INT_STATUS_1:
0130     case CS35L34_INT_STATUS_2:
0131     case CS35L34_INT_STATUS_3:
0132     case CS35L34_INT_STATUS_4:
0133     case CS35L34_CLASS_H_STATUS:
0134     case CS35L34_VPBR_ATTEN_STATUS:
0135     case CS35L34_OTP_TRIM_STATUS:
0136         return true;
0137     default:
0138         return false;
0139     }
0140 }
0141 
0142 static bool cs35l34_readable_register(struct device *dev, unsigned int reg)
0143 {
0144     switch (reg) {
0145     case    CS35L34_DEVID_AB:
0146     case    CS35L34_DEVID_CD:
0147     case    CS35L34_DEVID_E:
0148     case    CS35L34_FAB_ID:
0149     case    CS35L34_REV_ID:
0150     case    CS35L34_PWRCTL1:
0151     case    CS35L34_PWRCTL2:
0152     case    CS35L34_PWRCTL3:
0153     case    CS35L34_ADSP_CLK_CTL:
0154     case    CS35L34_MCLK_CTL:
0155     case    CS35L34_AMP_INP_DRV_CTL:
0156     case    CS35L34_AMP_DIG_VOL_CTL:
0157     case    CS35L34_AMP_DIG_VOL:
0158     case    CS35L34_AMP_ANLG_GAIN_CTL:
0159     case    CS35L34_PROTECT_CTL:
0160     case    CS35L34_AMP_KEEP_ALIVE_CTL:
0161     case    CS35L34_BST_CVTR_V_CTL:
0162     case    CS35L34_BST_PEAK_I:
0163     case    CS35L34_BST_RAMP_CTL:
0164     case    CS35L34_BST_CONV_COEF_1:
0165     case    CS35L34_BST_CONV_COEF_2:
0166     case    CS35L34_BST_CONV_SLOPE_COMP:
0167     case    CS35L34_BST_CONV_SW_FREQ:
0168     case    CS35L34_CLASS_H_CTL:
0169     case    CS35L34_CLASS_H_HEADRM_CTL:
0170     case    CS35L34_CLASS_H_RELEASE_RATE:
0171     case    CS35L34_CLASS_H_FET_DRIVE_CTL:
0172     case    CS35L34_CLASS_H_STATUS:
0173     case    CS35L34_VPBR_CTL:
0174     case    CS35L34_VPBR_VOL_CTL:
0175     case    CS35L34_VPBR_TIMING_CTL:
0176     case    CS35L34_PRED_MAX_ATTEN_SPK_LOAD:
0177     case    CS35L34_PRED_BROWNOUT_THRESH:
0178     case    CS35L34_PRED_BROWNOUT_VOL_CTL:
0179     case    CS35L34_PRED_BROWNOUT_RATE_CTL:
0180     case    CS35L34_PRED_WAIT_CTL:
0181     case    CS35L34_PRED_ZVP_INIT_IMP_CTL:
0182     case    CS35L34_PRED_MAN_SAFE_VPI_CTL:
0183     case    CS35L34_VPBR_ATTEN_STATUS:
0184     case    CS35L34_PRED_BRWNOUT_ATT_STATUS:
0185     case    CS35L34_SPKR_MON_CTL:
0186     case    CS35L34_ADSP_I2S_CTL:
0187     case    CS35L34_ADSP_TDM_CTL:
0188     case    CS35L34_TDM_TX_CTL_1_VMON:
0189     case    CS35L34_TDM_TX_CTL_2_IMON:
0190     case    CS35L34_TDM_TX_CTL_3_VPMON:
0191     case    CS35L34_TDM_TX_CTL_4_VBSTMON:
0192     case    CS35L34_TDM_TX_CTL_5_FLAG1:
0193     case    CS35L34_TDM_TX_CTL_6_FLAG2:
0194     case    CS35L34_TDM_TX_SLOT_EN_1:
0195     case    CS35L34_TDM_TX_SLOT_EN_2:
0196     case    CS35L34_TDM_TX_SLOT_EN_3:
0197     case    CS35L34_TDM_TX_SLOT_EN_4:
0198     case    CS35L34_TDM_RX_CTL_1_AUDIN:
0199     case    CS35L34_TDM_RX_CTL_3_ALIVE:
0200     case    CS35L34_MULT_DEV_SYNCH1:
0201     case    CS35L34_MULT_DEV_SYNCH2:
0202     case    CS35L34_PROT_RELEASE_CTL:
0203     case    CS35L34_DIAG_MODE_REG_LOCK:
0204     case    CS35L34_DIAG_MODE_CTL_1:
0205     case    CS35L34_DIAG_MODE_CTL_2:
0206     case    CS35L34_INT_MASK_1:
0207     case    CS35L34_INT_MASK_2:
0208     case    CS35L34_INT_MASK_3:
0209     case    CS35L34_INT_MASK_4:
0210     case    CS35L34_INT_STATUS_1:
0211     case    CS35L34_INT_STATUS_2:
0212     case    CS35L34_INT_STATUS_3:
0213     case    CS35L34_INT_STATUS_4:
0214     case    CS35L34_OTP_TRIM_STATUS:
0215         return true;
0216     default:
0217         return false;
0218     }
0219 }
0220 
0221 static bool cs35l34_precious_register(struct device *dev, unsigned int reg)
0222 {
0223     switch (reg) {
0224     case CS35L34_INT_STATUS_1:
0225     case CS35L34_INT_STATUS_2:
0226     case CS35L34_INT_STATUS_3:
0227     case CS35L34_INT_STATUS_4:
0228         return true;
0229     default:
0230         return false;
0231     }
0232 }
0233 
0234 static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
0235         struct snd_kcontrol *kcontrol, int event)
0236 {
0237     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0238     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0239     int ret;
0240 
0241     switch (event) {
0242     case SND_SOC_DAPM_PRE_PMU:
0243         if (priv->tdm_mode)
0244             regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
0245                         CS35L34_PDN_TDM, 0x00);
0246 
0247         ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
0248                         CS35L34_PDN_ALL, 0);
0249         if (ret < 0) {
0250             dev_err(component->dev, "Cannot set Power bits %d\n", ret);
0251             return ret;
0252         }
0253         usleep_range(5000, 5100);
0254     break;
0255     case SND_SOC_DAPM_POST_PMD:
0256         if (priv->tdm_mode) {
0257             regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
0258                     CS35L34_PDN_TDM, CS35L34_PDN_TDM);
0259         }
0260         ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
0261                     CS35L34_PDN_ALL, CS35L34_PDN_ALL);
0262     break;
0263     default:
0264         pr_err("Invalid event = 0x%x\n", event);
0265     }
0266     return 0;
0267 }
0268 
0269 static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0270                 unsigned int rx_mask, int slots, int slot_width)
0271 {
0272     struct snd_soc_component *component = dai->component;
0273     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0274     unsigned int reg, bit_pos;
0275     int slot, slot_num;
0276 
0277     if (slot_width != 8)
0278         return -EINVAL;
0279 
0280     priv->tdm_mode = true;
0281     /* scan rx_mask for aud slot */
0282     slot = ffs(rx_mask) - 1;
0283     if (slot >= 0)
0284         snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN,
0285                     CS35L34_X_LOC, slot);
0286 
0287     /* scan tx_mask: vmon(2 slots); imon (2 slots); vpmon (1 slot)
0288      * vbstmon (1 slot)
0289      */
0290     slot = ffs(tx_mask) - 1;
0291     slot_num = 0;
0292 
0293     /* disable vpmon/vbstmon: enable later if set in tx_mask */
0294     snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
0295                 CS35L34_X_STATE | CS35L34_X_LOC,
0296                 CS35L34_X_STATE | CS35L34_X_LOC);
0297     snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON,
0298                 CS35L34_X_STATE | CS35L34_X_LOC,
0299                 CS35L34_X_STATE | CS35L34_X_LOC);
0300 
0301     /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
0302     while (slot >= 0) {
0303         /* configure VMON_TX_LOC */
0304         if (slot_num == 0)
0305             snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON,
0306                     CS35L34_X_STATE | CS35L34_X_LOC, slot);
0307 
0308         /* configure IMON_TX_LOC */
0309         if (slot_num == 4) {
0310             snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON,
0311                     CS35L34_X_STATE | CS35L34_X_LOC, slot);
0312         }
0313         /* configure VPMON_TX_LOC */
0314         if (slot_num == 3) {
0315             snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
0316                     CS35L34_X_STATE | CS35L34_X_LOC, slot);
0317         }
0318         /* configure VBSTMON_TX_LOC */
0319         if (slot_num == 7) {
0320             snd_soc_component_update_bits(component,
0321                 CS35L34_TDM_TX_CTL_4_VBSTMON,
0322                 CS35L34_X_STATE | CS35L34_X_LOC, slot);
0323         }
0324 
0325         /* Enable the relevant tx slot */
0326         reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8);
0327         bit_pos = slot - ((slot / 8) * (8));
0328         snd_soc_component_update_bits(component, reg,
0329             1 << bit_pos, 1 << bit_pos);
0330 
0331         tx_mask &= ~(1 << slot);
0332         slot = ffs(tx_mask) - 1;
0333         slot_num++;
0334     }
0335 
0336     return 0;
0337 }
0338 
0339 static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w,
0340         struct snd_kcontrol *kcontrol, int event)
0341 {
0342     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0343     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0344 
0345     switch (event) {
0346     case SND_SOC_DAPM_POST_PMU:
0347         regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
0348                 CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge);
0349         usleep_range(5000, 5100);
0350         regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
0351                         CS35L34_MUTE, 0);
0352         break;
0353     case SND_SOC_DAPM_POST_PMD:
0354         regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
0355             CS35L34_BST_CVTL_MASK, 0);
0356         regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
0357             CS35L34_MUTE, CS35L34_MUTE);
0358         usleep_range(5000, 5100);
0359         break;
0360     default:
0361         pr_err("Invalid event = 0x%x\n", event);
0362     }
0363     return 0;
0364 }
0365 
0366 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
0367 
0368 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0);
0369 
0370 
0371 static const struct snd_kcontrol_new cs35l34_snd_controls[] = {
0372     SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL,
0373               0, 0x34, 0xE4, dig_vol_tlv),
0374     SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL,
0375               0, 0xF, 0, amp_gain_tlv),
0376 };
0377 
0378 
0379 static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w,
0380         struct snd_kcontrol *kcontrol, int event)
0381 {
0382     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0383     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0384     int ret, i;
0385     unsigned int reg;
0386 
0387     switch (event) {
0388     case SND_SOC_DAPM_PRE_PMD:
0389         ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL,
0390             &reg);
0391         if (ret != 0) {
0392             pr_err("%s regmap read failure %d\n", __func__, ret);
0393             return ret;
0394         }
0395         if (reg & CS35L34_AMP_DIGSFT)
0396             msleep(40);
0397         else
0398             usleep_range(2000, 2100);
0399 
0400         for (i = 0; i < PDN_DONE_ATTEMPTS; i++) {
0401             ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2,
0402                 &reg);
0403             if (ret != 0) {
0404                 pr_err("%s regmap read failure %d\n",
0405                     __func__, ret);
0406                 return ret;
0407             }
0408             if (reg & CS35L34_PDN_DONE)
0409                 break;
0410 
0411             usleep_range(5000, 5100);
0412         }
0413         if (i == PDN_DONE_ATTEMPTS)
0414             pr_err("%s Device did not power down properly\n",
0415                 __func__);
0416         break;
0417     default:
0418         pr_err("Invalid event = 0x%x\n", event);
0419         break;
0420     }
0421     return 0;
0422 }
0423 
0424 static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = {
0425     SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3,
0426                     1, 1, cs35l34_sdin_event,
0427                     SND_SOC_DAPM_PRE_PMU |
0428                     SND_SOC_DAPM_POST_PMD),
0429     SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1),
0430 
0431     SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1,
0432         cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD),
0433 
0434     SND_SOC_DAPM_OUTPUT("SPK"),
0435 
0436     SND_SOC_DAPM_INPUT("VP"),
0437     SND_SOC_DAPM_INPUT("VPST"),
0438     SND_SOC_DAPM_INPUT("ISENSE"),
0439     SND_SOC_DAPM_INPUT("VSENSE"),
0440 
0441     SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1),
0442     SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1),
0443     SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1),
0444     SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1),
0445     SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1),
0446     SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1),
0447 
0448     SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0,
0449         cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU |
0450             SND_SOC_DAPM_POST_PMD),
0451 };
0452 
0453 static const struct snd_soc_dapm_route cs35l34_audio_map[] = {
0454     {"SDIN", NULL, "AMP Playback"},
0455     {"BOOST", NULL, "SDIN"},
0456     {"CLASS H", NULL, "BOOST"},
0457     {"Main AMP", NULL, "CLASS H"},
0458     {"SPK", NULL, "Main AMP"},
0459 
0460     {"VPMON ADC", NULL, "CLASS H"},
0461     {"VBSTMON ADC", NULL, "CLASS H"},
0462     {"SPK", NULL, "VPMON ADC"},
0463     {"SPK", NULL, "VBSTMON ADC"},
0464 
0465     {"IMON ADC", NULL, "ISENSE"},
0466     {"VMON ADC", NULL, "VSENSE"},
0467     {"SDOUT", NULL, "IMON ADC"},
0468     {"SDOUT", NULL, "VMON ADC"},
0469     {"AMP Capture", NULL, "SDOUT"},
0470 
0471     {"SDIN", NULL, "EXTCLK"},
0472     {"SDOUT", NULL, "EXTCLK"},
0473 };
0474 
0475 struct cs35l34_mclk_div {
0476     int mclk;
0477     int srate;
0478     u8 adsp_rate;
0479 };
0480 
0481 static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = {
0482 
0483     /* MCLK, Sample Rate, adsp_rate */
0484 
0485     {5644800, 11025, 0x1},
0486     {5644800, 22050, 0x4},
0487     {5644800, 44100, 0x7},
0488 
0489     {6000000,  8000, 0x0},
0490     {6000000, 11025, 0x1},
0491     {6000000, 12000, 0x2},
0492     {6000000, 16000, 0x3},
0493     {6000000, 22050, 0x4},
0494     {6000000, 24000, 0x5},
0495     {6000000, 32000, 0x6},
0496     {6000000, 44100, 0x7},
0497     {6000000, 48000, 0x8},
0498 
0499     {6144000,  8000, 0x0},
0500     {6144000, 11025, 0x1},
0501     {6144000, 12000, 0x2},
0502     {6144000, 16000, 0x3},
0503     {6144000, 22050, 0x4},
0504     {6144000, 24000, 0x5},
0505     {6144000, 32000, 0x6},
0506     {6144000, 44100, 0x7},
0507     {6144000, 48000, 0x8},
0508 };
0509 
0510 static int cs35l34_get_mclk_coeff(int mclk, int srate)
0511 {
0512     int i;
0513 
0514     for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) {
0515         if (cs35l34_mclk_coeffs[i].mclk == mclk &&
0516             cs35l34_mclk_coeffs[i].srate == srate)
0517             return i;
0518     }
0519     return -EINVAL;
0520 }
0521 
0522 static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0523 {
0524     struct snd_soc_component *component = codec_dai->component;
0525     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0526 
0527     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0528     case SND_SOC_DAIFMT_CBM_CFM:
0529         regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
0530                     0x80, 0x80);
0531         break;
0532     case SND_SOC_DAIFMT_CBS_CFS:
0533         regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
0534                     0x80, 0x00);
0535         break;
0536     default:
0537         return -EINVAL;
0538     }
0539     return 0;
0540 }
0541 
0542 static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream,
0543                  struct snd_pcm_hw_params *params,
0544                  struct snd_soc_dai *dai)
0545 {
0546     struct snd_soc_component *component = dai->component;
0547     struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
0548     int srate = params_rate(params);
0549     int ret;
0550 
0551     int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate);
0552 
0553     if (coeff < 0) {
0554         dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n",
0555             priv->mclk_int, srate);
0556         return coeff;
0557     }
0558 
0559     ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
0560         CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate);
0561     if (ret != 0)
0562         dev_err(component->dev, "Failed to set clock state %d\n", ret);
0563 
0564     return ret;
0565 }
0566 
0567 static const unsigned int cs35l34_src_rates[] = {
0568     8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
0569 };
0570 
0571 
0572 static const struct snd_pcm_hw_constraint_list cs35l34_constraints = {
0573     .count  = ARRAY_SIZE(cs35l34_src_rates),
0574     .list   = cs35l34_src_rates,
0575 };
0576 
0577 static int cs35l34_pcm_startup(struct snd_pcm_substream *substream,
0578                    struct snd_soc_dai *dai)
0579 {
0580 
0581     snd_pcm_hw_constraint_list(substream->runtime, 0,
0582                 SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints);
0583     return 0;
0584 }
0585 
0586 
0587 static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate)
0588 {
0589 
0590     struct snd_soc_component *component = dai->component;
0591 
0592     if (tristate)
0593         snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
0594                     CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT);
0595     else
0596         snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
0597                     CS35L34_PDN_SDOUT, 0);
0598     return 0;
0599 }
0600 
0601 static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai,
0602                 int clk_id, unsigned int freq, int dir)
0603 {
0604     struct snd_soc_component *component = dai->component;
0605     struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
0606     unsigned int value;
0607 
0608     switch (freq) {
0609     case CS35L34_MCLK_5644:
0610         value = CS35L34_MCLK_RATE_5P6448;
0611         cs35l34->mclk_int = freq;
0612     break;
0613     case CS35L34_MCLK_6:
0614         value = CS35L34_MCLK_RATE_6P0000;
0615         cs35l34->mclk_int = freq;
0616     break;
0617     case CS35L34_MCLK_6144:
0618         value = CS35L34_MCLK_RATE_6P1440;
0619         cs35l34->mclk_int = freq;
0620     break;
0621     case CS35L34_MCLK_11289:
0622         value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448;
0623         cs35l34->mclk_int = freq / 2;
0624     break;
0625     case CS35L34_MCLK_12:
0626         value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000;
0627         cs35l34->mclk_int = freq / 2;
0628     break;
0629     case CS35L34_MCLK_12288:
0630         value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440;
0631         cs35l34->mclk_int = freq / 2;
0632     break;
0633     default:
0634         dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq);
0635         cs35l34->mclk_int = 0;
0636         return -EINVAL;
0637     }
0638     regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL,
0639             CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value);
0640     return 0;
0641 }
0642 
0643 static const struct snd_soc_dai_ops cs35l34_ops = {
0644     .startup = cs35l34_pcm_startup,
0645     .set_tristate = cs35l34_set_tristate,
0646     .set_fmt = cs35l34_set_dai_fmt,
0647     .hw_params = cs35l34_pcm_hw_params,
0648     .set_sysclk = cs35l34_dai_set_sysclk,
0649     .set_tdm_slot = cs35l34_set_tdm_slot,
0650 };
0651 
0652 static struct snd_soc_dai_driver cs35l34_dai = {
0653         .name = "cs35l34",
0654         .id = 0,
0655         .playback = {
0656             .stream_name = "AMP Playback",
0657             .channels_min = 1,
0658             .channels_max = 8,
0659             .rates = CS35L34_RATES,
0660             .formats = CS35L34_FORMATS,
0661         },
0662         .capture = {
0663             .stream_name = "AMP Capture",
0664             .channels_min = 1,
0665             .channels_max = 8,
0666             .rates = CS35L34_RATES,
0667             .formats = CS35L34_FORMATS,
0668         },
0669         .ops = &cs35l34_ops,
0670         .symmetric_rate = 1,
0671 };
0672 
0673 static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34,
0674     unsigned int inductor)
0675 {
0676     struct snd_soc_component *component = cs35l34->component;
0677 
0678     switch (inductor) {
0679     case 1000: /* 1 uH */
0680         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24);
0681         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24);
0682         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0683             0x4E);
0684         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0);
0685         break;
0686     case 1200: /* 1.2 uH */
0687         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
0688         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
0689         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0690             0x47);
0691         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1);
0692         break;
0693     case 1500: /* 1.5uH */
0694         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
0695         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
0696         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0697             0x3C);
0698         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2);
0699         break;
0700     case 2200: /* 2.2uH */
0701         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19);
0702         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25);
0703         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0704             0x23);
0705         regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3);
0706         break;
0707     default:
0708         dev_err(component->dev, "%s Invalid Inductor Value %d uH\n",
0709             __func__, inductor);
0710         return -EINVAL;
0711     }
0712     return 0;
0713 }
0714 
0715 static int cs35l34_probe(struct snd_soc_component *component)
0716 {
0717     int ret = 0;
0718     struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
0719 
0720     pm_runtime_get_sync(component->dev);
0721 
0722     /* Set over temperature warning attenuation to 6 dB */
0723     regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
0724          CS35L34_OTW_ATTN_MASK, 0x8);
0725 
0726     /* Set Power control registers 2 and 3 to have everything
0727      * powered down at initialization
0728      */
0729     regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD);
0730     regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F);
0731 
0732     /* Set mute bit at startup */
0733     regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
0734                 CS35L34_MUTE, CS35L34_MUTE);
0735 
0736     /* Set Platform Data */
0737     if (cs35l34->pdata.boost_peak)
0738         regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I,
0739                 CS35L34_BST_PEAK_MASK,
0740                 cs35l34->pdata.boost_peak);
0741 
0742     if (cs35l34->pdata.gain_zc_disable)
0743         regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
0744             CS35L34_GAIN_ZC_MASK, 0);
0745     else
0746         regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
0747             CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK);
0748 
0749     if (cs35l34->pdata.aif_half_drv)
0750         regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL,
0751             CS35L34_ADSP_DRIVE, 0);
0752 
0753     if (cs35l34->pdata.digsft_disable)
0754         regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
0755             CS35L34_AMP_DIGSFT, 0);
0756 
0757     if (cs35l34->pdata.amp_inv)
0758         regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
0759             CS35L34_INV, CS35L34_INV);
0760 
0761     if (cs35l34->pdata.boost_ind)
0762         ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind);
0763 
0764     if (cs35l34->pdata.i2s_sdinloc)
0765         regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL,
0766             CS35L34_I2S_LOC_MASK,
0767             cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT);
0768 
0769     if (cs35l34->pdata.tdm_rising_edge)
0770         regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL,
0771             1, 1);
0772 
0773     pm_runtime_put_sync(component->dev);
0774 
0775     return ret;
0776 }
0777 
0778 
0779 static const struct snd_soc_component_driver soc_component_dev_cs35l34 = {
0780     .probe          = cs35l34_probe,
0781     .dapm_widgets       = cs35l34_dapm_widgets,
0782     .num_dapm_widgets   = ARRAY_SIZE(cs35l34_dapm_widgets),
0783     .dapm_routes        = cs35l34_audio_map,
0784     .num_dapm_routes    = ARRAY_SIZE(cs35l34_audio_map),
0785     .controls       = cs35l34_snd_controls,
0786     .num_controls       = ARRAY_SIZE(cs35l34_snd_controls),
0787     .idle_bias_on       = 1,
0788     .use_pmdown_time    = 1,
0789     .endianness     = 1,
0790 };
0791 
0792 static struct regmap_config cs35l34_regmap = {
0793     .reg_bits = 8,
0794     .val_bits = 8,
0795 
0796     .max_register = CS35L34_MAX_REGISTER,
0797     .reg_defaults = cs35l34_reg,
0798     .num_reg_defaults = ARRAY_SIZE(cs35l34_reg),
0799     .volatile_reg = cs35l34_volatile_register,
0800     .readable_reg = cs35l34_readable_register,
0801     .precious_reg = cs35l34_precious_register,
0802     .cache_type = REGCACHE_RBTREE,
0803 
0804     .use_single_read = true,
0805     .use_single_write = true,
0806 };
0807 
0808 static int cs35l34_handle_of_data(struct i2c_client *i2c_client,
0809                 struct cs35l34_platform_data *pdata)
0810 {
0811     struct device_node *np = i2c_client->dev.of_node;
0812     unsigned int val;
0813 
0814     if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt",
0815         &val) >= 0) {
0816         /* Boost Voltage has a maximum of 8V */
0817         if (val > 8000 || (val < 3300 && val > 0)) {
0818             dev_err(&i2c_client->dev,
0819                 "Invalid Boost Voltage %d mV\n", val);
0820             return -EINVAL;
0821         }
0822         if (val == 0)
0823             pdata->boost_vtge = 0; /* Use VP */
0824         else
0825             pdata->boost_vtge = ((val - 3300)/100) + 1;
0826     } else {
0827         dev_warn(&i2c_client->dev,
0828             "Boost Voltage not specified. Using VP\n");
0829     }
0830 
0831     if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
0832         pdata->boost_ind = val;
0833     } else {
0834         dev_err(&i2c_client->dev, "Inductor not specified.\n");
0835         return -EINVAL;
0836     }
0837 
0838     if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) {
0839         if (val > 3840 || val < 1200) {
0840             dev_err(&i2c_client->dev,
0841                 "Invalid Boost Peak Current %d mA\n", val);
0842             return -EINVAL;
0843         }
0844         pdata->boost_peak = ((val - 1200)/80) + 1;
0845     }
0846 
0847     pdata->aif_half_drv = of_property_read_bool(np,
0848         "cirrus,aif-half-drv");
0849     pdata->digsft_disable = of_property_read_bool(np,
0850         "cirrus,digsft-disable");
0851 
0852     pdata->gain_zc_disable = of_property_read_bool(np,
0853         "cirrus,gain-zc-disable");
0854     pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv");
0855 
0856     if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0)
0857         pdata->i2s_sdinloc = val;
0858     if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0)
0859         pdata->tdm_rising_edge = val;
0860 
0861     return 0;
0862 }
0863 
0864 static irqreturn_t cs35l34_irq_thread(int irq, void *data)
0865 {
0866     struct cs35l34_private *cs35l34 = data;
0867     struct snd_soc_component *component = cs35l34->component;
0868     unsigned int sticky1, sticky2, sticky3, sticky4;
0869     unsigned int mask1, mask2, mask3, mask4, current1;
0870 
0871 
0872     /* ack the irq by reading all status registers */
0873     regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4);
0874     regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3);
0875     regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2);
0876     regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1);
0877 
0878     regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4);
0879     regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3);
0880     regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2);
0881     regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1);
0882 
0883     if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
0884         && !(sticky4 & ~mask4))
0885         return IRQ_NONE;
0886 
0887     regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &current1);
0888 
0889     if (sticky1 & CS35L34_CAL_ERR) {
0890         dev_err(component->dev, "Cal error\n");
0891 
0892         /* error is no longer asserted; safe to reset */
0893         if (!(current1 & CS35L34_CAL_ERR)) {
0894             dev_dbg(component->dev, "Cal error release\n");
0895             regmap_update_bits(cs35l34->regmap,
0896                     CS35L34_PROT_RELEASE_CTL,
0897                     CS35L34_CAL_ERR_RLS, 0);
0898             regmap_update_bits(cs35l34->regmap,
0899                     CS35L34_PROT_RELEASE_CTL,
0900                     CS35L34_CAL_ERR_RLS,
0901                     CS35L34_CAL_ERR_RLS);
0902             regmap_update_bits(cs35l34->regmap,
0903                     CS35L34_PROT_RELEASE_CTL,
0904                     CS35L34_CAL_ERR_RLS, 0);
0905             /* note: amp will re-calibrate on next resume */
0906         }
0907     }
0908 
0909     if (sticky1 & CS35L34_ALIVE_ERR)
0910         dev_err(component->dev, "Alive error\n");
0911 
0912     if (sticky1 & CS35L34_AMP_SHORT) {
0913         dev_crit(component->dev, "Amp short error\n");
0914 
0915         /* error is no longer asserted; safe to reset */
0916         if (!(current1 & CS35L34_AMP_SHORT)) {
0917             dev_dbg(component->dev,
0918                 "Amp short error release\n");
0919             regmap_update_bits(cs35l34->regmap,
0920                     CS35L34_PROT_RELEASE_CTL,
0921                     CS35L34_SHORT_RLS, 0);
0922             regmap_update_bits(cs35l34->regmap,
0923                     CS35L34_PROT_RELEASE_CTL,
0924                     CS35L34_SHORT_RLS,
0925                     CS35L34_SHORT_RLS);
0926             regmap_update_bits(cs35l34->regmap,
0927                     CS35L34_PROT_RELEASE_CTL,
0928                     CS35L34_SHORT_RLS, 0);
0929         }
0930     }
0931 
0932     if (sticky1 & CS35L34_OTW) {
0933         dev_crit(component->dev, "Over temperature warning\n");
0934 
0935         /* error is no longer asserted; safe to reset */
0936         if (!(current1 & CS35L34_OTW)) {
0937             dev_dbg(component->dev,
0938                 "Over temperature warning release\n");
0939             regmap_update_bits(cs35l34->regmap,
0940                     CS35L34_PROT_RELEASE_CTL,
0941                     CS35L34_OTW_RLS, 0);
0942             regmap_update_bits(cs35l34->regmap,
0943                     CS35L34_PROT_RELEASE_CTL,
0944                     CS35L34_OTW_RLS,
0945                     CS35L34_OTW_RLS);
0946             regmap_update_bits(cs35l34->regmap,
0947                     CS35L34_PROT_RELEASE_CTL,
0948                     CS35L34_OTW_RLS, 0);
0949         }
0950     }
0951 
0952     if (sticky1 & CS35L34_OTE) {
0953         dev_crit(component->dev, "Over temperature error\n");
0954 
0955         /* error is no longer asserted; safe to reset */
0956         if (!(current1 & CS35L34_OTE)) {
0957             dev_dbg(component->dev,
0958                 "Over temperature error release\n");
0959             regmap_update_bits(cs35l34->regmap,
0960                     CS35L34_PROT_RELEASE_CTL,
0961                     CS35L34_OTE_RLS, 0);
0962             regmap_update_bits(cs35l34->regmap,
0963                     CS35L34_PROT_RELEASE_CTL,
0964                     CS35L34_OTE_RLS,
0965                     CS35L34_OTE_RLS);
0966             regmap_update_bits(cs35l34->regmap,
0967                     CS35L34_PROT_RELEASE_CTL,
0968                     CS35L34_OTE_RLS, 0);
0969         }
0970     }
0971 
0972     if (sticky3 & CS35L34_BST_HIGH) {
0973         dev_crit(component->dev, "VBST too high error; powering off!\n");
0974         regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
0975                 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
0976         regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
0977                 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
0978     }
0979 
0980     if (sticky3 & CS35L34_LBST_SHORT) {
0981         dev_crit(component->dev, "LBST short error; powering off!\n");
0982         regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
0983                 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
0984         regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
0985                 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
0986     }
0987 
0988     return IRQ_HANDLED;
0989 }
0990 
0991 static const char * const cs35l34_core_supplies[] = {
0992     "VA",
0993     "VP",
0994 };
0995 
0996 static int cs35l34_i2c_probe(struct i2c_client *i2c_client)
0997 {
0998     struct cs35l34_private *cs35l34;
0999     struct cs35l34_platform_data *pdata =
1000         dev_get_platdata(&i2c_client->dev);
1001     int i, devid;
1002     int ret;
1003     unsigned int reg;
1004 
1005     cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
1006     if (!cs35l34)
1007         return -ENOMEM;
1008 
1009     i2c_set_clientdata(i2c_client, cs35l34);
1010     cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
1011     if (IS_ERR(cs35l34->regmap)) {
1012         ret = PTR_ERR(cs35l34->regmap);
1013         dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1014         return ret;
1015     }
1016 
1017     cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies);
1018     for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++)
1019         cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i];
1020 
1021     ret = devm_regulator_bulk_get(&i2c_client->dev,
1022         cs35l34->num_core_supplies,
1023         cs35l34->core_supplies);
1024     if (ret != 0) {
1025         dev_err(&i2c_client->dev,
1026             "Failed to request core supplies %d\n", ret);
1027         return ret;
1028     }
1029 
1030     ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1031                     cs35l34->core_supplies);
1032     if (ret != 0) {
1033         dev_err(&i2c_client->dev,
1034             "Failed to enable core supplies: %d\n", ret);
1035         return ret;
1036     }
1037 
1038     if (pdata) {
1039         cs35l34->pdata = *pdata;
1040     } else {
1041         pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1042                      GFP_KERNEL);
1043         if (!pdata) {
1044             ret = -ENOMEM;
1045             goto err_regulator;
1046         }
1047 
1048         if (i2c_client->dev.of_node) {
1049             ret = cs35l34_handle_of_data(i2c_client, pdata);
1050             if (ret != 0)
1051                 goto err_regulator;
1052 
1053         }
1054         cs35l34->pdata = *pdata;
1055     }
1056 
1057     ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1058             cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1059             "cs35l34", cs35l34);
1060     if (ret != 0)
1061         dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1062 
1063     cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1064                 "reset-gpios", GPIOD_OUT_LOW);
1065     if (IS_ERR(cs35l34->reset_gpio)) {
1066         ret = PTR_ERR(cs35l34->reset_gpio);
1067         goto err_regulator;
1068     }
1069 
1070     gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1071 
1072     msleep(CS35L34_START_DELAY);
1073 
1074     devid = cirrus_read_device_id(cs35l34->regmap, CS35L34_DEVID_AB);
1075     if (devid < 0) {
1076         ret = devid;
1077         dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1078         goto err_reset;
1079     }
1080 
1081     if (devid != CS35L34_CHIP_ID) {
1082         dev_err(&i2c_client->dev,
1083             "CS35l34 Device ID (%X). Expected ID %X\n",
1084             devid, CS35L34_CHIP_ID);
1085         ret = -ENODEV;
1086         goto err_reset;
1087     }
1088 
1089     ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, &reg);
1090     if (ret < 0) {
1091         dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1092         goto err_reset;
1093     }
1094 
1095     dev_info(&i2c_client->dev,
1096          "Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid,
1097         reg & 0xFF);
1098 
1099     /* Unmask critical interrupts */
1100     regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1,
1101                 CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR |
1102                 CS35L34_M_AMP_SHORT | CS35L34_M_OTW |
1103                 CS35L34_M_OTE, 0);
1104     regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3,
1105                 CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0);
1106 
1107     pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1108     pm_runtime_use_autosuspend(&i2c_client->dev);
1109     pm_runtime_set_active(&i2c_client->dev);
1110     pm_runtime_enable(&i2c_client->dev);
1111 
1112     ret = devm_snd_soc_register_component(&i2c_client->dev,
1113             &soc_component_dev_cs35l34, &cs35l34_dai, 1);
1114     if (ret < 0) {
1115         dev_err(&i2c_client->dev,
1116             "%s: Register component failed\n", __func__);
1117         goto err_reset;
1118     }
1119 
1120     return 0;
1121 
1122 err_reset:
1123     gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1124 err_regulator:
1125     regulator_bulk_disable(cs35l34->num_core_supplies,
1126         cs35l34->core_supplies);
1127 
1128     return ret;
1129 }
1130 
1131 static int cs35l34_i2c_remove(struct i2c_client *client)
1132 {
1133     struct cs35l34_private *cs35l34 = i2c_get_clientdata(client);
1134 
1135     gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1136 
1137     pm_runtime_disable(&client->dev);
1138     regulator_bulk_disable(cs35l34->num_core_supplies,
1139         cs35l34->core_supplies);
1140 
1141     return 0;
1142 }
1143 
1144 static int __maybe_unused cs35l34_runtime_resume(struct device *dev)
1145 {
1146     struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1147     int ret;
1148 
1149     ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1150         cs35l34->core_supplies);
1151 
1152     if (ret != 0) {
1153         dev_err(dev, "Failed to enable core supplies: %d\n",
1154             ret);
1155         return ret;
1156     }
1157 
1158     regcache_cache_only(cs35l34->regmap, false);
1159 
1160     gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1161     msleep(CS35L34_START_DELAY);
1162 
1163     ret = regcache_sync(cs35l34->regmap);
1164     if (ret != 0) {
1165         dev_err(dev, "Failed to restore register cache\n");
1166         goto err;
1167     }
1168     return 0;
1169 err:
1170     regcache_cache_only(cs35l34->regmap, true);
1171     regulator_bulk_disable(cs35l34->num_core_supplies,
1172         cs35l34->core_supplies);
1173 
1174     return ret;
1175 }
1176 
1177 static int __maybe_unused cs35l34_runtime_suspend(struct device *dev)
1178 {
1179     struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1180 
1181     regcache_cache_only(cs35l34->regmap, true);
1182     regcache_mark_dirty(cs35l34->regmap);
1183 
1184     gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1185 
1186     regulator_bulk_disable(cs35l34->num_core_supplies,
1187             cs35l34->core_supplies);
1188 
1189     return 0;
1190 }
1191 
1192 static const struct dev_pm_ops cs35l34_pm_ops = {
1193     SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend,
1194                cs35l34_runtime_resume,
1195                NULL)
1196 };
1197 
1198 static const struct of_device_id cs35l34_of_match[] = {
1199     {.compatible = "cirrus,cs35l34"},
1200     {},
1201 };
1202 MODULE_DEVICE_TABLE(of, cs35l34_of_match);
1203 
1204 static const struct i2c_device_id cs35l34_id[] = {
1205     {"cs35l34", 0},
1206     {}
1207 };
1208 MODULE_DEVICE_TABLE(i2c, cs35l34_id);
1209 
1210 static struct i2c_driver cs35l34_i2c_driver = {
1211     .driver = {
1212         .name = "cs35l34",
1213         .pm = &cs35l34_pm_ops,
1214         .of_match_table = cs35l34_of_match,
1215 
1216         },
1217     .id_table = cs35l34_id,
1218     .probe_new = cs35l34_i2c_probe,
1219     .remove = cs35l34_i2c_remove,
1220 
1221 };
1222 
1223 static int __init cs35l34_modinit(void)
1224 {
1225     int ret;
1226 
1227     ret = i2c_add_driver(&cs35l34_i2c_driver);
1228     if (ret != 0) {
1229         pr_err("Failed to register CS35l34 I2C driver: %d\n", ret);
1230         return ret;
1231     }
1232     return 0;
1233 }
1234 module_init(cs35l34_modinit);
1235 
1236 static void __exit cs35l34_exit(void)
1237 {
1238     i2c_del_driver(&cs35l34_i2c_driver);
1239 }
1240 module_exit(cs35l34_exit);
1241 
1242 MODULE_DESCRIPTION("ASoC CS35l34 driver");
1243 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
1244 MODULE_LICENSE("GPL");
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