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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cs35l33.c -- CS35L33 ALSA SoC audio driver
0004  *
0005  * Copyright 2016 Cirrus Logic, Inc.
0006  *
0007  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
0008  */
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/i2c.h>
0015 #include <linux/slab.h>
0016 #include <linux/workqueue.h>
0017 #include <linux/platform_device.h>
0018 #include <sound/core.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022 #include <sound/soc-dapm.h>
0023 #include <sound/initval.h>
0024 #include <sound/tlv.h>
0025 #include <linux/gpio.h>
0026 #include <linux/gpio/consumer.h>
0027 #include <sound/cs35l33.h>
0028 #include <linux/pm_runtime.h>
0029 #include <linux/regulator/consumer.h>
0030 #include <linux/regulator/machine.h>
0031 #include <linux/of_gpio.h>
0032 #include <linux/of.h>
0033 #include <linux/of_device.h>
0034 #include <linux/of_irq.h>
0035 
0036 #include "cs35l33.h"
0037 #include "cirrus_legacy.h"
0038 
0039 #define CS35L33_BOOT_DELAY  50
0040 
0041 struct cs35l33_private {
0042     struct snd_soc_component *component;
0043     struct cs35l33_pdata pdata;
0044     struct regmap *regmap;
0045     struct gpio_desc *reset_gpio;
0046     bool amp_cal;
0047     int mclk_int;
0048     struct regulator_bulk_data core_supplies[2];
0049     int num_core_supplies;
0050     bool is_tdm_mode;
0051     bool enable_soft_ramp;
0052 };
0053 
0054 static const struct reg_default cs35l33_reg[] = {
0055     {CS35L33_PWRCTL1, 0x85},
0056     {CS35L33_PWRCTL2, 0xFE},
0057     {CS35L33_CLK_CTL, 0x0C},
0058     {CS35L33_BST_PEAK_CTL, 0x90},
0059     {CS35L33_PROTECT_CTL, 0x55},
0060     {CS35L33_BST_CTL1, 0x00},
0061     {CS35L33_BST_CTL2, 0x01},
0062     {CS35L33_ADSP_CTL, 0x00},
0063     {CS35L33_ADC_CTL, 0xC8},
0064     {CS35L33_DAC_CTL, 0x14},
0065     {CS35L33_DIG_VOL_CTL, 0x00},
0066     {CS35L33_CLASSD_CTL, 0x04},
0067     {CS35L33_AMP_CTL, 0x90},
0068     {CS35L33_INT_MASK_1, 0xFF},
0069     {CS35L33_INT_MASK_2, 0xFF},
0070     {CS35L33_DIAG_LOCK, 0x00},
0071     {CS35L33_DIAG_CTRL_1, 0x40},
0072     {CS35L33_DIAG_CTRL_2, 0x00},
0073     {CS35L33_HG_MEMLDO_CTL, 0x62},
0074     {CS35L33_HG_REL_RATE, 0x03},
0075     {CS35L33_LDO_DEL, 0x12},
0076     {CS35L33_HG_HEAD, 0x0A},
0077     {CS35L33_HG_EN, 0x05},
0078     {CS35L33_TX_VMON, 0x00},
0079     {CS35L33_TX_IMON, 0x03},
0080     {CS35L33_TX_VPMON, 0x02},
0081     {CS35L33_TX_VBSTMON, 0x05},
0082     {CS35L33_TX_FLAG, 0x06},
0083     {CS35L33_TX_EN1, 0x00},
0084     {CS35L33_TX_EN2, 0x00},
0085     {CS35L33_TX_EN3, 0x00},
0086     {CS35L33_TX_EN4, 0x00},
0087     {CS35L33_RX_AUD, 0x40},
0088     {CS35L33_RX_SPLY, 0x03},
0089     {CS35L33_RX_ALIVE, 0x04},
0090     {CS35L33_BST_CTL4, 0x63},
0091 };
0092 
0093 static const struct reg_sequence cs35l33_patch[] = {
0094     { 0x00,  0x99, 0 },
0095     { 0x59,  0x02, 0 },
0096     { 0x52,  0x30, 0 },
0097     { 0x39,  0x45, 0 },
0098     { 0x57,  0x30, 0 },
0099     { 0x2C,  0x68, 0 },
0100     { 0x00,  0x00, 0 },
0101 };
0102 
0103 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
0104 {
0105     switch (reg) {
0106     case CS35L33_DEVID_AB:
0107     case CS35L33_DEVID_CD:
0108     case CS35L33_DEVID_E:
0109     case CS35L33_REV_ID:
0110     case CS35L33_INT_STATUS_1:
0111     case CS35L33_INT_STATUS_2:
0112     case CS35L33_HG_STATUS:
0113         return true;
0114     default:
0115         return false;
0116     }
0117 }
0118 
0119 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
0120 {
0121     switch (reg) {
0122     /* these are read only registers */
0123     case CS35L33_DEVID_AB:
0124     case CS35L33_DEVID_CD:
0125     case CS35L33_DEVID_E:
0126     case CS35L33_REV_ID:
0127     case CS35L33_INT_STATUS_1:
0128     case CS35L33_INT_STATUS_2:
0129     case CS35L33_HG_STATUS:
0130         return false;
0131     default:
0132         return true;
0133     }
0134 }
0135 
0136 static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
0137 {
0138     switch (reg) {
0139     case CS35L33_DEVID_AB:
0140     case CS35L33_DEVID_CD:
0141     case CS35L33_DEVID_E:
0142     case CS35L33_REV_ID:
0143     case CS35L33_PWRCTL1:
0144     case CS35L33_PWRCTL2:
0145     case CS35L33_CLK_CTL:
0146     case CS35L33_BST_PEAK_CTL:
0147     case CS35L33_PROTECT_CTL:
0148     case CS35L33_BST_CTL1:
0149     case CS35L33_BST_CTL2:
0150     case CS35L33_ADSP_CTL:
0151     case CS35L33_ADC_CTL:
0152     case CS35L33_DAC_CTL:
0153     case CS35L33_DIG_VOL_CTL:
0154     case CS35L33_CLASSD_CTL:
0155     case CS35L33_AMP_CTL:
0156     case CS35L33_INT_MASK_1:
0157     case CS35L33_INT_MASK_2:
0158     case CS35L33_INT_STATUS_1:
0159     case CS35L33_INT_STATUS_2:
0160     case CS35L33_DIAG_LOCK:
0161     case CS35L33_DIAG_CTRL_1:
0162     case CS35L33_DIAG_CTRL_2:
0163     case CS35L33_HG_MEMLDO_CTL:
0164     case CS35L33_HG_REL_RATE:
0165     case CS35L33_LDO_DEL:
0166     case CS35L33_HG_HEAD:
0167     case CS35L33_HG_EN:
0168     case CS35L33_TX_VMON:
0169     case CS35L33_TX_IMON:
0170     case CS35L33_TX_VPMON:
0171     case CS35L33_TX_VBSTMON:
0172     case CS35L33_TX_FLAG:
0173     case CS35L33_TX_EN1:
0174     case CS35L33_TX_EN2:
0175     case CS35L33_TX_EN3:
0176     case CS35L33_TX_EN4:
0177     case CS35L33_RX_AUD:
0178     case CS35L33_RX_SPLY:
0179     case CS35L33_RX_ALIVE:
0180     case CS35L33_BST_CTL4:
0181         return true;
0182     default:
0183         return false;
0184     }
0185 }
0186 
0187 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
0188 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
0189 
0190 static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
0191 
0192     SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
0193                4, 0x09, 0, classd_ctl_tlv),
0194     SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
0195             0, 0x34, 0xE4, dac_tlv),
0196 };
0197 
0198 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
0199     struct snd_kcontrol *kcontrol, int event)
0200 {
0201     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0202     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0203 
0204     switch (event) {
0205     case SND_SOC_DAPM_POST_PMU:
0206         if (!priv->amp_cal) {
0207             usleep_range(8000, 9000);
0208             priv->amp_cal = true;
0209             regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
0210                     CS35L33_AMP_CAL, 0);
0211             dev_dbg(component->dev, "Amp calibration done\n");
0212         }
0213         dev_dbg(component->dev, "Amp turned on\n");
0214         break;
0215     case SND_SOC_DAPM_POST_PMD:
0216         dev_dbg(component->dev, "Amp turned off\n");
0217         break;
0218     default:
0219         dev_err(component->dev, "Invalid event = 0x%x\n", event);
0220         break;
0221     }
0222 
0223     return 0;
0224 }
0225 
0226 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
0227     struct snd_kcontrol *kcontrol, int event)
0228 {
0229     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0230     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0231     unsigned int val;
0232 
0233     switch (event) {
0234     case SND_SOC_DAPM_PRE_PMU:
0235         regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
0236                     CS35L33_PDN_BST, 0);
0237         val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
0238         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
0239                     CS35L33_PDN_TDM, val);
0240         dev_dbg(component->dev, "BST turned on\n");
0241         break;
0242     case SND_SOC_DAPM_POST_PMU:
0243         dev_dbg(component->dev, "SDIN turned on\n");
0244         if (!priv->amp_cal) {
0245             regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
0246                     CS35L33_AMP_CAL, CS35L33_AMP_CAL);
0247             dev_dbg(component->dev, "Amp calibration started\n");
0248             usleep_range(10000, 11000);
0249         }
0250         break;
0251     case SND_SOC_DAPM_POST_PMD:
0252         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
0253                     CS35L33_PDN_TDM, CS35L33_PDN_TDM);
0254         usleep_range(4000, 4100);
0255         regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
0256                     CS35L33_PDN_BST, CS35L33_PDN_BST);
0257         dev_dbg(component->dev, "BST and SDIN turned off\n");
0258         break;
0259     default:
0260         dev_err(component->dev, "Invalid event = 0x%x\n", event);
0261 
0262     }
0263 
0264     return 0;
0265 }
0266 
0267 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
0268     struct snd_kcontrol *kcontrol, int event)
0269 {
0270     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0271     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0272     unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
0273     unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
0274     unsigned int val, val2;
0275 
0276     switch (event) {
0277     case SND_SOC_DAPM_PRE_PMU:
0278         if (priv->is_tdm_mode) {
0279             /* set sdout_3st_i2s and reset pdn_tdm */
0280             val = CS35L33_SDOUT_3ST_I2S;
0281             /* reset sdout_3st_tdm */
0282             val2 = 0;
0283         } else {
0284             /* reset sdout_3st_i2s and set pdn_tdm */
0285             val = CS35L33_PDN_TDM;
0286             /* set sdout_3st_tdm */
0287             val2 = CS35L33_SDOUT_3ST_TDM;
0288         }
0289         dev_dbg(component->dev, "SDOUT turned on\n");
0290         break;
0291     case SND_SOC_DAPM_PRE_PMD:
0292         val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
0293         val2 = CS35L33_SDOUT_3ST_TDM;
0294         dev_dbg(component->dev, "SDOUT turned off\n");
0295         break;
0296     default:
0297         dev_err(component->dev, "Invalid event = 0x%x\n", event);
0298         return 0;
0299     }
0300 
0301     regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
0302         mask, val);
0303     regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0304         mask2, val2);
0305 
0306     return 0;
0307 }
0308 
0309 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
0310 
0311     SND_SOC_DAPM_OUTPUT("SPK"),
0312     SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
0313         cs35l33_spkrdrv_event,
0314         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0315     SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
0316         2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
0317         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0318 
0319     SND_SOC_DAPM_INPUT("MON"),
0320 
0321     SND_SOC_DAPM_ADC("VMON", NULL,
0322         CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
0323     SND_SOC_DAPM_ADC("IMON", NULL,
0324         CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
0325     SND_SOC_DAPM_ADC("VPMON", NULL,
0326         CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
0327     SND_SOC_DAPM_ADC("VBSTMON", NULL,
0328         CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
0329 
0330     SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
0331         cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
0332         SND_SOC_DAPM_PRE_PMD),
0333 };
0334 
0335 static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
0336     {"SDIN", NULL, "CS35L33 Playback"},
0337     {"SPKDRV", NULL, "SDIN"},
0338     {"SPK", NULL, "SPKDRV"},
0339 
0340     {"VMON", NULL, "MON"},
0341     {"IMON", NULL, "MON"},
0342 
0343     {"SDOUT", NULL, "VMON"},
0344     {"SDOUT", NULL, "IMON"},
0345     {"CS35L33 Capture", NULL, "SDOUT"},
0346 };
0347 
0348 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
0349     {"SPKDRV", NULL, "VPMON"},
0350     {"VPMON", NULL, "CS35L33 Playback"},
0351 };
0352 
0353 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
0354     {"SDOUT", NULL, "VPMON"},
0355     {"VPMON", NULL, "MON"},
0356     {"SDOUT", NULL, "VBSTMON"},
0357     {"VBSTMON", NULL, "MON"},
0358 };
0359 
0360 static int cs35l33_set_bias_level(struct snd_soc_component *component,
0361                   enum snd_soc_bias_level level)
0362 {
0363     unsigned int val;
0364     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0365 
0366     switch (level) {
0367     case SND_SOC_BIAS_ON:
0368         break;
0369     case SND_SOC_BIAS_PREPARE:
0370         regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
0371                     CS35L33_PDN_ALL, 0);
0372         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0373                     CS35L33_MCLKDIS, 0);
0374         break;
0375     case SND_SOC_BIAS_STANDBY:
0376         regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
0377                     CS35L33_PDN_ALL, CS35L33_PDN_ALL);
0378         regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
0379         usleep_range(1000, 1100);
0380         if (val & CS35L33_PDN_DONE)
0381             regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0382                         CS35L33_MCLKDIS, CS35L33_MCLKDIS);
0383         break;
0384     case SND_SOC_BIAS_OFF:
0385         break;
0386     default:
0387         return -EINVAL;
0388     }
0389 
0390     return 0;
0391 }
0392 
0393 struct cs35l33_mclk_div {
0394     int mclk;
0395     int srate;
0396     u8 adsp_rate;
0397     u8 int_fs_ratio;
0398 };
0399 
0400 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
0401     /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
0402     {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
0403     {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
0404     {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
0405 
0406     {6000000,  8000, 0x1, 0},
0407     {6000000, 11025, 0x2, 0},
0408     {6000000, 11029, 0x3, 0},
0409     {6000000, 12000, 0x4, 0},
0410     {6000000, 16000, 0x5, 0},
0411     {6000000, 22050, 0x6, 0},
0412     {6000000, 22059, 0x7, 0},
0413     {6000000, 24000, 0x8, 0},
0414     {6000000, 32000, 0x9, 0},
0415     {6000000, 44100, 0xA, 0},
0416     {6000000, 44118, 0xB, 0},
0417     {6000000, 48000, 0xC, 0},
0418 
0419     {6144000,  8000, 0x1, CS35L33_INT_FS_RATE},
0420     {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
0421     {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
0422     {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
0423     {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
0424     {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
0425 };
0426 
0427 static int cs35l33_get_mclk_coeff(int mclk, int srate)
0428 {
0429     int i;
0430 
0431     for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
0432         if (cs35l33_mclk_coeffs[i].mclk == mclk &&
0433             cs35l33_mclk_coeffs[i].srate == srate)
0434             return i;
0435     }
0436     return -EINVAL;
0437 }
0438 
0439 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0440 {
0441     struct snd_soc_component *component = codec_dai->component;
0442     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0443 
0444     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0445     case SND_SOC_DAIFMT_CBM_CFM:
0446         regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
0447             CS35L33_MS_MASK, CS35L33_MS_MASK);
0448         dev_dbg(component->dev, "Audio port in master mode\n");
0449         break;
0450     case SND_SOC_DAIFMT_CBS_CFS:
0451         regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
0452             CS35L33_MS_MASK, 0);
0453         dev_dbg(component->dev, "Audio port in slave mode\n");
0454         break;
0455     default:
0456         return -EINVAL;
0457     }
0458 
0459     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0460     case SND_SOC_DAIFMT_DSP_A:
0461         /*
0462          * tdm mode in cs35l33 resembles dsp-a mode very
0463          * closely, it is dsp-a with fsync shifted left by half bclk
0464          */
0465         priv->is_tdm_mode = true;
0466         dev_dbg(component->dev, "Audio port in TDM mode\n");
0467         break;
0468     case SND_SOC_DAIFMT_I2S:
0469         priv->is_tdm_mode = false;
0470         dev_dbg(component->dev, "Audio port in I2S mode\n");
0471         break;
0472     default:
0473         return -EINVAL;
0474     }
0475 
0476     return 0;
0477 }
0478 
0479 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
0480                  struct snd_pcm_hw_params *params,
0481                  struct snd_soc_dai *dai)
0482 {
0483     struct snd_soc_component *component = dai->component;
0484     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0485     int sample_size = params_width(params);
0486     int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
0487 
0488     if (coeff < 0)
0489         return coeff;
0490 
0491     regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0492         CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
0493         cs35l33_mclk_coeffs[coeff].int_fs_ratio
0494         | cs35l33_mclk_coeffs[coeff].adsp_rate);
0495 
0496     if (priv->is_tdm_mode) {
0497         sample_size = (sample_size / 8) - 1;
0498         if (sample_size > 2)
0499             sample_size = 2;
0500         regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
0501             CS35L33_AUDIN_RX_DEPTH,
0502             sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
0503     }
0504 
0505     dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
0506         params_rate(params), params_width(params));
0507 
0508     return 0;
0509 }
0510 
0511 static const unsigned int cs35l33_src_rates[] = {
0512     8000, 11025, 11029, 12000, 16000, 22050,
0513     22059, 24000, 32000, 44100, 44118, 48000
0514 };
0515 
0516 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
0517     .count  = ARRAY_SIZE(cs35l33_src_rates),
0518     .list   = cs35l33_src_rates,
0519 };
0520 
0521 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
0522                    struct snd_soc_dai *dai)
0523 {
0524     snd_pcm_hw_constraint_list(substream->runtime, 0,
0525                     SNDRV_PCM_HW_PARAM_RATE,
0526                     &cs35l33_constraints);
0527     return 0;
0528 }
0529 
0530 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
0531 {
0532     struct snd_soc_component *component = dai->component;
0533     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0534 
0535     if (tristate) {
0536         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
0537             CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
0538         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0539             CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
0540     } else {
0541         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
0542             CS35L33_SDOUT_3ST_I2S, 0);
0543         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
0544             CS35L33_SDOUT_3ST_TDM, 0);
0545     }
0546 
0547     return 0;
0548 }
0549 
0550 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0551                 unsigned int rx_mask, int slots, int slot_width)
0552 {
0553     struct snd_soc_component *component = dai->component;
0554     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0555     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0556     unsigned int reg, bit_pos, i;
0557     int slot, slot_num;
0558 
0559     if (slot_width != 8)
0560         return -EINVAL;
0561 
0562     /* scan rx_mask for aud slot */
0563     slot = ffs(rx_mask) - 1;
0564     if (slot >= 0) {
0565         regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
0566             CS35L33_X_LOC, slot);
0567         dev_dbg(component->dev, "Audio starts from slots %d", slot);
0568     }
0569 
0570     /*
0571      * scan tx_mask: vmon(2 slots); imon (2 slots);
0572      * vpmon (1 slot) vbstmon (1 slot)
0573      */
0574     slot = ffs(tx_mask) - 1;
0575     slot_num = 0;
0576 
0577     for (i = 0; i < 2 ; i++) {
0578         /* disable vpmon/vbstmon: enable later if set in tx_mask */
0579         regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
0580             CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
0581             | CS35L33_X_LOC);
0582     }
0583 
0584     /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
0585     snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
0586         ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
0587 
0588     while (slot >= 0) {
0589         /* configure VMON_TX_LOC */
0590         if (slot_num == 0) {
0591             regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
0592                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
0593             dev_dbg(component->dev, "VMON enabled in slots %d-%d",
0594                 slot, slot + 1);
0595         }
0596 
0597         /* configure IMON_TX_LOC */
0598         if (slot_num == 3) {
0599             regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
0600                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
0601             dev_dbg(component->dev, "IMON enabled in slots %d-%d",
0602                 slot, slot + 1);
0603         }
0604 
0605         /* configure VPMON_TX_LOC */
0606         if (slot_num == 4) {
0607             regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
0608                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
0609             snd_soc_dapm_add_routes(dapm,
0610                 &cs35l33_vp_vbst_mon_route[0], 2);
0611             dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
0612         }
0613 
0614         /* configure VBSTMON_TX_LOC */
0615         if (slot_num == 5) {
0616             regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
0617                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
0618             snd_soc_dapm_add_routes(dapm,
0619                 &cs35l33_vp_vbst_mon_route[2], 2);
0620             dev_dbg(component->dev,
0621                 "VBSTMON enabled in slots %d", slot);
0622         }
0623 
0624         /* Enable the relevant tx slot */
0625         reg = CS35L33_TX_EN4 - (slot/8);
0626         bit_pos = slot - ((slot / 8) * (8));
0627         regmap_update_bits(priv->regmap, reg,
0628             1 << bit_pos, 1 << bit_pos);
0629 
0630         tx_mask &= ~(1 << slot);
0631         slot = ffs(tx_mask) - 1;
0632         slot_num++;
0633     }
0634 
0635     return 0;
0636 }
0637 
0638 static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
0639         int clk_id, int source, unsigned int freq, int dir)
0640 {
0641     struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
0642 
0643     switch (freq) {
0644     case CS35L33_MCLK_5644:
0645     case CS35L33_MCLK_6:
0646     case CS35L33_MCLK_6144:
0647         regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
0648             CS35L33_MCLKDIV2, 0);
0649         cs35l33->mclk_int = freq;
0650         break;
0651     case CS35L33_MCLK_11289:
0652     case CS35L33_MCLK_12:
0653     case CS35L33_MCLK_12288:
0654         regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
0655             CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
0656         cs35l33->mclk_int = freq/2;
0657         break;
0658     default:
0659         cs35l33->mclk_int = 0;
0660         return -EINVAL;
0661     }
0662 
0663     dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
0664         freq, cs35l33->mclk_int);
0665 
0666     return 0;
0667 }
0668 
0669 static const struct snd_soc_dai_ops cs35l33_ops = {
0670     .startup = cs35l33_pcm_startup,
0671     .set_tristate = cs35l33_set_tristate,
0672     .set_fmt = cs35l33_set_dai_fmt,
0673     .hw_params = cs35l33_pcm_hw_params,
0674     .set_tdm_slot = cs35l33_set_tdm_slot,
0675 };
0676 
0677 static struct snd_soc_dai_driver cs35l33_dai = {
0678         .name = "cs35l33-dai",
0679         .id = 0,
0680         .playback = {
0681             .stream_name = "CS35L33 Playback",
0682             .channels_min = 1,
0683             .channels_max = 1,
0684             .rates = CS35L33_RATES,
0685             .formats = CS35L33_FORMATS,
0686         },
0687         .capture = {
0688             .stream_name = "CS35L33 Capture",
0689             .channels_min = 2,
0690             .channels_max = 2,
0691             .rates = CS35L33_RATES,
0692             .formats = CS35L33_FORMATS,
0693         },
0694         .ops = &cs35l33_ops,
0695         .symmetric_rate = 1,
0696 };
0697 
0698 static int cs35l33_set_hg_data(struct snd_soc_component *component,
0699                    struct cs35l33_pdata *pdata)
0700 {
0701     struct cs35l33_hg *hg_config = &pdata->hg_config;
0702     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0703     struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
0704 
0705     if (hg_config->enable_hg_algo) {
0706         regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
0707             CS35L33_MEM_DEPTH_MASK,
0708             hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
0709         regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
0710             hg_config->release_rate);
0711         regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
0712             CS35L33_HD_RM_MASK,
0713             hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
0714         regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
0715             CS35L33_LDO_THLD_MASK,
0716             hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
0717         regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
0718             CS35L33_LDO_DISABLE_MASK,
0719             hg_config->ldo_path_disable <<
0720                 CS35L33_LDO_DISABLE_SHIFT);
0721         regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
0722             CS35L33_LDO_ENTRY_DELAY_MASK,
0723             hg_config->ldo_entry_delay <<
0724                 CS35L33_LDO_ENTRY_DELAY_SHIFT);
0725         if (hg_config->vp_hg_auto) {
0726             regmap_update_bits(priv->regmap, CS35L33_HG_EN,
0727                 CS35L33_VP_HG_AUTO_MASK,
0728                 CS35L33_VP_HG_AUTO_MASK);
0729             snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
0730                 ARRAY_SIZE(cs35l33_vphg_auto_route));
0731         }
0732         regmap_update_bits(priv->regmap, CS35L33_HG_EN,
0733             CS35L33_VP_HG_MASK,
0734             hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
0735         regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
0736             CS35L33_VP_HG_RATE_MASK,
0737             hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
0738         regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
0739             CS35L33_VP_HG_VA_MASK,
0740             hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
0741         regmap_update_bits(priv->regmap, CS35L33_HG_EN,
0742             CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
0743     }
0744     return 0;
0745 }
0746 
0747 static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
0748 {
0749     struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
0750     int ret = 0, steps = 0;
0751 
0752     /* Boost current in uA */
0753     if (bst > 3600000 || bst < 1850000) {
0754         dev_err(component->dev, "Invalid boost current %d\n", bst);
0755         ret = -EINVAL;
0756         goto err;
0757     }
0758 
0759     if (bst % 15625) {
0760         dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
0761             bst);
0762         ret = -EINVAL;
0763         goto err;
0764     }
0765 
0766     while (bst > 1850000) {
0767         bst -= 15625;
0768         steps++;
0769     }
0770 
0771     regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
0772         steps+0x70);
0773 
0774 err:
0775     return ret;
0776 }
0777 
0778 static int cs35l33_probe(struct snd_soc_component *component)
0779 {
0780     struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
0781 
0782     cs35l33->component = component;
0783     pm_runtime_get_sync(component->dev);
0784 
0785     regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
0786         CS35L33_ALIVE_WD_DIS, 0x8);
0787     regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
0788                 CS35L33_ALIVE_WD_DIS2,
0789                 CS35L33_ALIVE_WD_DIS2);
0790 
0791     /* Set Platform Data */
0792     regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
0793         CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
0794     regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
0795         CS35L33_AMP_DRV_SEL_MASK,
0796         cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
0797 
0798     if (cs35l33->pdata.boost_ipk)
0799         cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
0800 
0801     if (cs35l33->enable_soft_ramp) {
0802         snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
0803             CS35L33_DIGSFT, CS35L33_DIGSFT);
0804         snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
0805             CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
0806     } else {
0807         snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
0808             CS35L33_DIGSFT, 0);
0809     }
0810 
0811     /* update IMON scaling rate if different from default of 0x8 */
0812     if (cs35l33->pdata.imon_adc_scale != 0x8)
0813         snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
0814             CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
0815 
0816     cs35l33_set_hg_data(component, &(cs35l33->pdata));
0817 
0818     /*
0819      * unmask important interrupts that causes the chip to enter
0820      * speaker safe mode and hence deserves user attention
0821      */
0822     regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
0823         CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
0824         CS35L33_M_CAL_ERR, 0);
0825 
0826     pm_runtime_put_sync(component->dev);
0827 
0828     return 0;
0829 }
0830 
0831 static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
0832     .probe          = cs35l33_probe,
0833     .set_bias_level     = cs35l33_set_bias_level,
0834     .set_sysclk     = cs35l33_component_set_sysclk,
0835     .controls       = cs35l33_snd_controls,
0836     .num_controls       = ARRAY_SIZE(cs35l33_snd_controls),
0837     .dapm_widgets       = cs35l33_dapm_widgets,
0838     .num_dapm_widgets   = ARRAY_SIZE(cs35l33_dapm_widgets),
0839     .dapm_routes        = cs35l33_audio_map,
0840     .num_dapm_routes    = ARRAY_SIZE(cs35l33_audio_map),
0841     .use_pmdown_time    = 1,
0842     .endianness     = 1,
0843 };
0844 
0845 static const struct regmap_config cs35l33_regmap = {
0846     .reg_bits = 8,
0847     .val_bits = 8,
0848 
0849     .max_register = CS35L33_MAX_REGISTER,
0850     .reg_defaults = cs35l33_reg,
0851     .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
0852     .volatile_reg = cs35l33_volatile_register,
0853     .readable_reg = cs35l33_readable_register,
0854     .writeable_reg = cs35l33_writeable_register,
0855     .cache_type = REGCACHE_RBTREE,
0856     .use_single_read = true,
0857     .use_single_write = true,
0858 };
0859 
0860 static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
0861 {
0862     struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
0863     int ret;
0864 
0865     dev_dbg(dev, "%s\n", __func__);
0866 
0867     gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
0868 
0869     ret = regulator_bulk_enable(cs35l33->num_core_supplies,
0870         cs35l33->core_supplies);
0871     if (ret != 0) {
0872         dev_err(dev, "Failed to enable core supplies: %d\n", ret);
0873         return ret;
0874     }
0875 
0876     regcache_cache_only(cs35l33->regmap, false);
0877 
0878     gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
0879 
0880     msleep(CS35L33_BOOT_DELAY);
0881 
0882     ret = regcache_sync(cs35l33->regmap);
0883     if (ret != 0) {
0884         dev_err(dev, "Failed to restore register cache\n");
0885         goto err;
0886     }
0887 
0888     return 0;
0889 
0890 err:
0891     regcache_cache_only(cs35l33->regmap, true);
0892     regulator_bulk_disable(cs35l33->num_core_supplies,
0893         cs35l33->core_supplies);
0894 
0895     return ret;
0896 }
0897 
0898 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
0899 {
0900     struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
0901 
0902     dev_dbg(dev, "%s\n", __func__);
0903 
0904     /* redo the calibration in next power up */
0905     cs35l33->amp_cal = false;
0906 
0907     regcache_cache_only(cs35l33->regmap, true);
0908     regcache_mark_dirty(cs35l33->regmap);
0909     regulator_bulk_disable(cs35l33->num_core_supplies,
0910         cs35l33->core_supplies);
0911 
0912     return 0;
0913 }
0914 
0915 static const struct dev_pm_ops cs35l33_pm_ops = {
0916     SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
0917                cs35l33_runtime_resume,
0918                NULL)
0919 };
0920 
0921 static int cs35l33_get_hg_data(const struct device_node *np,
0922                    struct cs35l33_pdata *pdata)
0923 {
0924     struct device_node *hg;
0925     struct cs35l33_hg *hg_config = &pdata->hg_config;
0926     u32 val32;
0927 
0928     hg = of_get_child_by_name(np, "cirrus,hg-algo");
0929     hg_config->enable_hg_algo = hg ? true : false;
0930 
0931     if (hg_config->enable_hg_algo) {
0932         if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
0933             hg_config->mem_depth = val32;
0934         if (of_property_read_u32(hg, "cirrus,release-rate",
0935                 &val32) >= 0)
0936             hg_config->release_rate = val32;
0937         if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
0938             hg_config->ldo_thld = val32;
0939         if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
0940                 &val32) >= 0)
0941             hg_config->ldo_path_disable = val32;
0942         if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
0943                 &val32) >= 0)
0944             hg_config->ldo_entry_delay = val32;
0945 
0946         hg_config->vp_hg_auto = of_property_read_bool(hg,
0947             "cirrus,vp-hg-auto");
0948 
0949         if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
0950             hg_config->vp_hg = val32;
0951         if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
0952             hg_config->vp_hg_rate = val32;
0953         if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
0954             hg_config->vp_hg_va = val32;
0955     }
0956 
0957     of_node_put(hg);
0958 
0959     return 0;
0960 }
0961 
0962 static irqreturn_t cs35l33_irq_thread(int irq, void *data)
0963 {
0964     struct cs35l33_private *cs35l33 = data;
0965     struct snd_soc_component *component = cs35l33->component;
0966     unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
0967 
0968     regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
0969         &sticky_val2);
0970     regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
0971         &sticky_val1);
0972     regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
0973     regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
0974 
0975     /* Check to see if the unmasked bits are active,
0976      *  if not then exit.
0977      */
0978     if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
0979         return IRQ_NONE;
0980 
0981     regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
0982         &current_val);
0983 
0984     /* handle the interrupts */
0985 
0986     if (sticky_val1 & CS35L33_AMP_SHORT) {
0987         dev_crit(component->dev, "Amp short error\n");
0988         if (!(current_val & CS35L33_AMP_SHORT)) {
0989             dev_dbg(component->dev,
0990                 "Amp short error release\n");
0991             regmap_update_bits(cs35l33->regmap,
0992                 CS35L33_AMP_CTL,
0993                 CS35L33_AMP_SHORT_RLS, 0);
0994             regmap_update_bits(cs35l33->regmap,
0995                 CS35L33_AMP_CTL,
0996                 CS35L33_AMP_SHORT_RLS,
0997                 CS35L33_AMP_SHORT_RLS);
0998             regmap_update_bits(cs35l33->regmap,
0999                 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
1000                 0);
1001         }
1002     }
1003 
1004     if (sticky_val1 & CS35L33_CAL_ERR) {
1005         dev_err(component->dev, "Cal error\n");
1006 
1007         /* redo the calibration in next power up */
1008         cs35l33->amp_cal = false;
1009 
1010         if (!(current_val & CS35L33_CAL_ERR)) {
1011             dev_dbg(component->dev, "Cal error release\n");
1012             regmap_update_bits(cs35l33->regmap,
1013                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1014                 0);
1015             regmap_update_bits(cs35l33->regmap,
1016                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1017                 CS35L33_CAL_ERR_RLS);
1018             regmap_update_bits(cs35l33->regmap,
1019                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1020                 0);
1021         }
1022     }
1023 
1024     if (sticky_val1 & CS35L33_OTE) {
1025         dev_crit(component->dev, "Over temperature error\n");
1026         if (!(current_val & CS35L33_OTE)) {
1027             dev_dbg(component->dev,
1028                 "Over temperature error release\n");
1029             regmap_update_bits(cs35l33->regmap,
1030                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1031             regmap_update_bits(cs35l33->regmap,
1032                 CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1033                 CS35L33_OTE_RLS);
1034             regmap_update_bits(cs35l33->regmap,
1035                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1036         }
1037     }
1038 
1039     if (sticky_val1 & CS35L33_OTW) {
1040         dev_err(component->dev, "Over temperature warning\n");
1041         if (!(current_val & CS35L33_OTW)) {
1042             dev_dbg(component->dev,
1043                 "Over temperature warning release\n");
1044             regmap_update_bits(cs35l33->regmap,
1045                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1046             regmap_update_bits(cs35l33->regmap,
1047                 CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1048                 CS35L33_OTW_RLS);
1049             regmap_update_bits(cs35l33->regmap,
1050                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1051         }
1052     }
1053     if (CS35L33_ALIVE_ERR & sticky_val1)
1054         dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
1055 
1056     if (CS35L33_MCLK_ERR & sticky_val1)
1057         dev_err(component->dev, "ERROR: MCLK Interrupt\n");
1058 
1059     if (CS35L33_VMON_OVFL & sticky_val2)
1060         dev_err(component->dev,
1061             "ERROR: VMON Overflow Interrupt\n");
1062 
1063     if (CS35L33_IMON_OVFL & sticky_val2)
1064         dev_err(component->dev,
1065             "ERROR: IMON Overflow Interrupt\n");
1066 
1067     if (CS35L33_VPMON_OVFL & sticky_val2)
1068         dev_err(component->dev,
1069             "ERROR: VPMON Overflow Interrupt\n");
1070 
1071     return IRQ_HANDLED;
1072 }
1073 
1074 static const char * const cs35l33_core_supplies[] = {
1075     "VA",
1076     "VP",
1077 };
1078 
1079 static int cs35l33_of_get_pdata(struct device *dev,
1080                 struct cs35l33_private *cs35l33)
1081 {
1082     struct device_node *np = dev->of_node;
1083     struct cs35l33_pdata *pdata = &cs35l33->pdata;
1084     u32 val32;
1085 
1086     if (!np)
1087         return 0;
1088 
1089     if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1090         pdata->boost_ctl = val32;
1091         pdata->amp_drv_sel = 1;
1092     }
1093 
1094     if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1095         pdata->ramp_rate = val32;
1096         cs35l33->enable_soft_ramp = true;
1097     }
1098 
1099     if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1100         pdata->boost_ipk = val32;
1101 
1102     if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1103         if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1104             pdata->imon_adc_scale = val32;
1105         else
1106             /* use default value */
1107             pdata->imon_adc_scale = 0x8;
1108     } else {
1109         /* use default value */
1110         pdata->imon_adc_scale = 0x8;
1111     }
1112 
1113     cs35l33_get_hg_data(np, pdata);
1114 
1115     return 0;
1116 }
1117 
1118 static int cs35l33_i2c_probe(struct i2c_client *i2c_client)
1119 {
1120     struct cs35l33_private *cs35l33;
1121     struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1122     int ret, devid, i;
1123     unsigned int reg;
1124 
1125     cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1126                    GFP_KERNEL);
1127     if (!cs35l33)
1128         return -ENOMEM;
1129 
1130     i2c_set_clientdata(i2c_client, cs35l33);
1131     cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1132     if (IS_ERR(cs35l33->regmap)) {
1133         ret = PTR_ERR(cs35l33->regmap);
1134         dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1135         return ret;
1136     }
1137 
1138     regcache_cache_only(cs35l33->regmap, true);
1139 
1140     for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1141         cs35l33->core_supplies[i].supply
1142             = cs35l33_core_supplies[i];
1143     cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1144 
1145     ret = devm_regulator_bulk_get(&i2c_client->dev,
1146             cs35l33->num_core_supplies,
1147             cs35l33->core_supplies);
1148     if (ret != 0) {
1149         dev_err(&i2c_client->dev,
1150             "Failed to request core supplies: %d\n",
1151             ret);
1152         return ret;
1153     }
1154 
1155     if (pdata) {
1156         cs35l33->pdata = *pdata;
1157     } else {
1158         cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1159         pdata = &cs35l33->pdata;
1160     }
1161 
1162     ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1163             cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1164             "cs35l33", cs35l33);
1165     if (ret != 0)
1166         dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1167 
1168     /* We could issue !RST or skip it based on AMP topology */
1169     cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1170             "reset-gpios", GPIOD_OUT_HIGH);
1171     if (IS_ERR(cs35l33->reset_gpio)) {
1172         dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1173             __func__);
1174         return PTR_ERR(cs35l33->reset_gpio);
1175     }
1176 
1177     ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1178                     cs35l33->core_supplies);
1179     if (ret != 0) {
1180         dev_err(&i2c_client->dev,
1181             "Failed to enable core supplies: %d\n",
1182             ret);
1183         return ret;
1184     }
1185 
1186     gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1187 
1188     msleep(CS35L33_BOOT_DELAY);
1189     regcache_cache_only(cs35l33->regmap, false);
1190 
1191     /* initialize codec */
1192     devid = cirrus_read_device_id(cs35l33->regmap, CS35L33_DEVID_AB);
1193     if (devid < 0) {
1194         ret = devid;
1195         dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1196         goto err_enable;
1197     }
1198 
1199     if (devid != CS35L33_CHIP_ID) {
1200         dev_err(&i2c_client->dev,
1201             "CS35L33 Device ID (%X). Expected ID %X\n",
1202             devid, CS35L33_CHIP_ID);
1203         ret = -EINVAL;
1204         goto err_enable;
1205     }
1206 
1207     ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1208     if (ret < 0) {
1209         dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1210         goto err_enable;
1211     }
1212 
1213     dev_info(&i2c_client->dev,
1214          "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
1215 
1216     ret = regmap_register_patch(cs35l33->regmap,
1217             cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1218     if (ret < 0) {
1219         dev_err(&i2c_client->dev,
1220             "Error in applying regmap patch: %d\n", ret);
1221         goto err_enable;
1222     }
1223 
1224     /* disable mclk and tdm */
1225     regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1226         CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1227         CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1228 
1229     pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1230     pm_runtime_use_autosuspend(&i2c_client->dev);
1231     pm_runtime_set_active(&i2c_client->dev);
1232     pm_runtime_enable(&i2c_client->dev);
1233 
1234     ret = devm_snd_soc_register_component(&i2c_client->dev,
1235             &soc_component_dev_cs35l33, &cs35l33_dai, 1);
1236     if (ret < 0) {
1237         dev_err(&i2c_client->dev, "%s: Register component failed\n",
1238             __func__);
1239         goto err_enable;
1240     }
1241 
1242     return 0;
1243 
1244 err_enable:
1245     gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1246 
1247     regulator_bulk_disable(cs35l33->num_core_supplies,
1248                    cs35l33->core_supplies);
1249 
1250     return ret;
1251 }
1252 
1253 static int cs35l33_i2c_remove(struct i2c_client *client)
1254 {
1255     struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1256 
1257     gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1258 
1259     pm_runtime_disable(&client->dev);
1260     regulator_bulk_disable(cs35l33->num_core_supplies,
1261         cs35l33->core_supplies);
1262 
1263     return 0;
1264 }
1265 
1266 static const struct of_device_id cs35l33_of_match[] = {
1267     { .compatible = "cirrus,cs35l33", },
1268     {},
1269 };
1270 MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1271 
1272 static const struct i2c_device_id cs35l33_id[] = {
1273     {"cs35l33", 0},
1274     {}
1275 };
1276 
1277 MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1278 
1279 static struct i2c_driver cs35l33_i2c_driver = {
1280     .driver = {
1281         .name = "cs35l33",
1282         .pm = &cs35l33_pm_ops,
1283         .of_match_table = cs35l33_of_match,
1284 
1285         },
1286     .id_table = cs35l33_id,
1287     .probe_new = cs35l33_i2c_probe,
1288     .remove = cs35l33_i2c_remove,
1289 
1290 };
1291 module_i2c_driver(cs35l33_i2c_driver);
1292 
1293 MODULE_DESCRIPTION("ASoC CS35L33 driver");
1294 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1295 MODULE_LICENSE("GPL");
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