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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
0004 //
0005 // Copyright (C) 2009 Renesas Solutions Corp.
0006 // Kuninori Morimoto <morimoto.kuninori@renesas.com>
0007 //
0008 // Based on wm8731.c by Richard Purdie
0009 // Based on ak4535.c by Richard Purdie
0010 // Based on wm8753.c by Liam Girdwood
0011 
0012 /* ** CAUTION **
0013  *
0014  * This is very simple driver.
0015  * It can use headphone output / stereo input only
0016  *
0017  * AK4642 is tested.
0018  * AK4643 is tested.
0019  * AK4648 is tested.
0020  */
0021 
0022 #include <linux/clk.h>
0023 #include <linux/clk-provider.h>
0024 #include <linux/delay.h>
0025 #include <linux/i2c.h>
0026 #include <linux/slab.h>
0027 #include <linux/of_device.h>
0028 #include <linux/module.h>
0029 #include <linux/regmap.h>
0030 #include <sound/soc.h>
0031 #include <sound/initval.h>
0032 #include <sound/tlv.h>
0033 
0034 #define PW_MGMT1    0x00
0035 #define PW_MGMT2    0x01
0036 #define SG_SL1      0x02
0037 #define SG_SL2      0x03
0038 #define MD_CTL1     0x04
0039 #define MD_CTL2     0x05
0040 #define TIMER       0x06
0041 #define ALC_CTL1    0x07
0042 #define ALC_CTL2    0x08
0043 #define L_IVC       0x09
0044 #define L_DVC       0x0a
0045 #define ALC_CTL3    0x0b
0046 #define R_IVC       0x0c
0047 #define R_DVC       0x0d
0048 #define MD_CTL3     0x0e
0049 #define MD_CTL4     0x0f
0050 #define PW_MGMT3    0x10
0051 #define DF_S        0x11
0052 #define FIL3_0      0x12
0053 #define FIL3_1      0x13
0054 #define FIL3_2      0x14
0055 #define FIL3_3      0x15
0056 #define EQ_0        0x16
0057 #define EQ_1        0x17
0058 #define EQ_2        0x18
0059 #define EQ_3        0x19
0060 #define EQ_4        0x1a
0061 #define EQ_5        0x1b
0062 #define FIL1_0      0x1c
0063 #define FIL1_1      0x1d
0064 #define FIL1_2      0x1e
0065 #define FIL1_3      0x1f    /* The maximum valid register for ak4642 */
0066 #define PW_MGMT4    0x20
0067 #define MD_CTL5     0x21
0068 #define LO_MS       0x22
0069 #define HP_MS       0x23
0070 #define SPK_MS      0x24    /* The maximum valid register for ak4643 */
0071 #define EQ_FBEQAB   0x25
0072 #define EQ_FBEQCD   0x26
0073 #define EQ_FBEQE    0x27    /* The maximum valid register for ak4648 */
0074 
0075 /* PW_MGMT1*/
0076 #define PMVCM       (1 << 6) /* VCOM Power Management */
0077 #define PMMIN       (1 << 5) /* MIN Input Power Management */
0078 #define PMDAC       (1 << 2) /* DAC Power Management */
0079 #define PMADL       (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
0080 
0081 /* PW_MGMT2 */
0082 #define HPMTN       (1 << 6)
0083 #define PMHPL       (1 << 5)
0084 #define PMHPR       (1 << 4)
0085 #define MS      (1 << 3) /* master/slave select */
0086 #define MCKO        (1 << 1)
0087 #define PMPLL       (1 << 0)
0088 
0089 #define PMHP_MASK   (PMHPL | PMHPR)
0090 #define PMHP        PMHP_MASK
0091 
0092 /* PW_MGMT3 */
0093 #define PMADR       (1 << 0) /* MIC L / ADC R Power Management */
0094 
0095 /* SG_SL1 */
0096 #define MINS        (1 << 6) /* Switch from MIN to Speaker */
0097 #define DACL        (1 << 4) /* Switch from DAC to Stereo or Receiver */
0098 #define PMMP        (1 << 2) /* MPWR pin Power Management */
0099 #define MGAIN0      (1 << 0) /* MIC amp gain*/
0100 
0101 /* SG_SL2 */
0102 #define LOPS        (1 << 6) /* Stero Line-out Power Save Mode */
0103 
0104 /* TIMER */
0105 #define ZTM(param)  ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
0106 #define WTM(param)  (((param & 0x4) << 4) | ((param & 0x3) << 2))
0107 
0108 /* ALC_CTL1 */
0109 #define ALC     (1 << 5) /* ALC Enable */
0110 #define LMTH0       (1 << 0) /* ALC Limiter / Recovery Level */
0111 
0112 /* MD_CTL1 */
0113 #define PLL3        (1 << 7)
0114 #define PLL2        (1 << 6)
0115 #define PLL1        (1 << 5)
0116 #define PLL0        (1 << 4)
0117 #define PLL_MASK    (PLL3 | PLL2 | PLL1 | PLL0)
0118 
0119 #define BCKO_MASK   (1 << 3)
0120 #define BCKO_64     BCKO_MASK
0121 
0122 #define DIF_MASK    (3 << 0)
0123 #define DSP     (0 << 0)
0124 #define RIGHT_J     (1 << 0)
0125 #define LEFT_J      (2 << 0)
0126 #define I2S     (3 << 0)
0127 
0128 /* MD_CTL2 */
0129 #define FSs(val)    (((val & 0x7) << 0) | ((val & 0x8) << 2))
0130 #define PSs(val)    ((val & 0x3) << 6)
0131 
0132 /* MD_CTL3 */
0133 #define BST1        (1 << 3)
0134 
0135 /* MD_CTL4 */
0136 #define DACH        (1 << 0)
0137 
0138 struct ak4642_drvdata {
0139     const struct regmap_config *regmap_config;
0140     int extended_frequencies;
0141 };
0142 
0143 struct ak4642_priv {
0144     const struct ak4642_drvdata *drvdata;
0145     struct clk *mcko;
0146 };
0147 
0148 /*
0149  * Playback Volume (table 39)
0150  *
0151  * max : 0x00 : +12.0 dB
0152  *       ( 0.5 dB step )
0153  * min : 0xFE : -115.0 dB
0154  * mute: 0xFF
0155  */
0156 static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
0157 
0158 static const struct snd_kcontrol_new ak4642_snd_controls[] = {
0159 
0160     SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
0161              0, 0xFF, 1, out_tlv),
0162     SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
0163     SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
0164 };
0165 
0166 static const struct snd_kcontrol_new ak4642_headphone_control =
0167     SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
0168 
0169 static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
0170     SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
0171 };
0172 
0173 /* event handlers */
0174 static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
0175                  struct snd_kcontrol *kcontrol, int event)
0176 {
0177     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0178 
0179     switch (event) {
0180     case SND_SOC_DAPM_PRE_PMD:
0181     case SND_SOC_DAPM_PRE_PMU:
0182         /* Power save mode ON */
0183         snd_soc_component_update_bits(component, SG_SL2, LOPS, LOPS);
0184         break;
0185     case SND_SOC_DAPM_POST_PMU:
0186     case SND_SOC_DAPM_POST_PMD:
0187         /* Power save mode OFF */
0188         msleep(300);
0189         snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);
0190         break;
0191     }
0192 
0193     return 0;
0194 }
0195 
0196 static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
0197 
0198     /* Outputs */
0199     SND_SOC_DAPM_OUTPUT("HPOUTL"),
0200     SND_SOC_DAPM_OUTPUT("HPOUTR"),
0201     SND_SOC_DAPM_OUTPUT("LINEOUT"),
0202 
0203     SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
0204     SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
0205     SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
0206                 &ak4642_headphone_control),
0207 
0208     SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
0209 
0210     SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
0211                &ak4642_lout_mixer_controls[0],
0212                ARRAY_SIZE(ak4642_lout_mixer_controls),
0213                ak4642_lout_event,
0214                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0215                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0216 
0217     /* DAC */
0218     SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
0219 };
0220 
0221 static const struct snd_soc_dapm_route ak4642_intercon[] = {
0222 
0223     /* Outputs */
0224     {"HPOUTL", NULL, "HPL Out"},
0225     {"HPOUTR", NULL, "HPR Out"},
0226     {"LINEOUT", NULL, "LINEOUT Mixer"},
0227 
0228     {"HPL Out", NULL, "Headphone Enable"},
0229     {"HPR Out", NULL, "Headphone Enable"},
0230 
0231     {"Headphone Enable", "Switch", "DACH"},
0232 
0233     {"DACH", NULL, "DAC"},
0234 
0235     {"LINEOUT Mixer", "DACL", "DAC"},
0236 
0237     { "DAC", NULL, "Playback" },
0238 };
0239 
0240 /*
0241  * ak4642 register cache
0242  */
0243 static const struct reg_default ak4643_reg[] = {
0244     {  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
0245     {  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
0246     {  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
0247     { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
0248     { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
0249     { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
0250     { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
0251     { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
0252     { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
0253     { 36, 0x00 },
0254 };
0255 
0256 /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
0257    and ak4643. So we reuse the ak4643 reg_default for ak4642.
0258    The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
0259    so define NUM_AK4642_REG_DEFAULTS for ak4642.
0260 */
0261 #define ak4642_reg ak4643_reg
0262 #define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
0263 
0264 static const struct reg_default ak4648_reg[] = {
0265     {  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
0266     {  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
0267     {  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
0268     { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
0269     { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
0270     { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
0271     { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
0272     { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
0273     { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
0274     { 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
0275 };
0276 
0277 static int ak4642_dai_startup(struct snd_pcm_substream *substream,
0278                   struct snd_soc_dai *dai)
0279 {
0280     int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0281     struct snd_soc_component *component = dai->component;
0282 
0283     if (is_play) {
0284         /*
0285          * start headphone output
0286          *
0287          * PLL, Master Mode
0288          * Audio I/F Format :MSB justified (ADC & DAC)
0289          * Bass Boost Level : Middle
0290          *
0291          * This operation came from example code of
0292          * "ASAHI KASEI AK4642" (japanese) manual p97.
0293          */
0294         snd_soc_component_write(component, L_IVC, 0x91); /* volume */
0295         snd_soc_component_write(component, R_IVC, 0x91); /* volume */
0296     } else {
0297         /*
0298          * start stereo input
0299          *
0300          * PLL Master Mode
0301          * Audio I/F Format:MSB justified (ADC & DAC)
0302          * Pre MIC AMP:+20dB
0303          * MIC Power On
0304          * ALC setting:Refer to Table 35
0305          * ALC bit=“1”
0306          *
0307          * This operation came from example code of
0308          * "ASAHI KASEI AK4642" (japanese) manual p94.
0309          */
0310         snd_soc_component_update_bits(component, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
0311         snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));
0312         snd_soc_component_write(component, ALC_CTL1, ALC | LMTH0);
0313         snd_soc_component_update_bits(component, PW_MGMT1, PMADL, PMADL);
0314         snd_soc_component_update_bits(component, PW_MGMT3, PMADR, PMADR);
0315     }
0316 
0317     return 0;
0318 }
0319 
0320 static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
0321                    struct snd_soc_dai *dai)
0322 {
0323     int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0324     struct snd_soc_component *component = dai->component;
0325 
0326     if (is_play) {
0327     } else {
0328         /* stop stereo input */
0329         snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);
0330         snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);
0331         snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);
0332     }
0333 }
0334 
0335 static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
0336     int clk_id, unsigned int freq, int dir)
0337 {
0338     struct snd_soc_component *component = codec_dai->component;
0339     struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
0340     u8 pll;
0341     int extended_freq = 0;
0342 
0343     switch (freq) {
0344     case 11289600:
0345         pll = PLL2;
0346         break;
0347     case 12288000:
0348         pll = PLL2 | PLL0;
0349         break;
0350     case 12000000:
0351         pll = PLL2 | PLL1;
0352         break;
0353     case 24000000:
0354         pll = PLL2 | PLL1 | PLL0;
0355         break;
0356     case 13500000:
0357         pll = PLL3 | PLL2;
0358         break;
0359     case 27000000:
0360         pll = PLL3 | PLL2 | PLL0;
0361         break;
0362     case 19200000:
0363         pll = PLL3;
0364         extended_freq = 1;
0365         break;
0366     case 13000000:
0367         pll = PLL3 | PLL2 | PLL1;
0368         extended_freq = 1;
0369         break;
0370     case 26000000:
0371         pll = PLL3 | PLL2 | PLL1 | PLL0;
0372         extended_freq = 1;
0373         break;
0374     default:
0375         return -EINVAL;
0376     }
0377 
0378     if (extended_freq && !priv->drvdata->extended_frequencies)
0379         return -EINVAL;
0380 
0381     snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
0382 
0383     return 0;
0384 }
0385 
0386 static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0387 {
0388     struct snd_soc_component *component = dai->component;
0389     u8 data;
0390     u8 bcko;
0391 
0392     data = MCKO | PMPLL; /* use MCKO */
0393     bcko = 0;
0394 
0395     /* set clocking for audio interface */
0396     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0397     case SND_SOC_DAIFMT_CBP_CFP:
0398         data |= MS;
0399         bcko = BCKO_64;
0400         break;
0401     case SND_SOC_DAIFMT_CBC_CFC:
0402         break;
0403     default:
0404         return -EINVAL;
0405     }
0406     snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data);
0407     snd_soc_component_update_bits(component, MD_CTL1, BCKO_MASK, bcko);
0408 
0409     /* format type */
0410     data = 0;
0411     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0412     case SND_SOC_DAIFMT_LEFT_J:
0413         data = LEFT_J;
0414         break;
0415     case SND_SOC_DAIFMT_I2S:
0416         data = I2S;
0417         break;
0418     /* FIXME
0419      * Please add RIGHT_J / DSP support here
0420      */
0421     default:
0422         return -EINVAL;
0423     }
0424     snd_soc_component_update_bits(component, MD_CTL1, DIF_MASK, data);
0425 
0426     return 0;
0427 }
0428 
0429 static int ak4642_set_mcko(struct snd_soc_component *component,
0430                u32 frequency)
0431 {
0432     static const u32 fs_list[] = {
0433         [0] = 8000,
0434         [1] = 12000,
0435         [2] = 16000,
0436         [3] = 24000,
0437         [4] = 7350,
0438         [5] = 11025,
0439         [6] = 14700,
0440         [7] = 22050,
0441         [10] = 32000,
0442         [11] = 48000,
0443         [14] = 29400,
0444         [15] = 44100,
0445     };
0446     static const u32 ps_list[] = {
0447         [0] = 256,
0448         [1] = 128,
0449         [2] = 64,
0450         [3] = 32
0451     };
0452     int ps, fs;
0453 
0454     for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
0455         for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
0456             if (frequency == ps_list[ps] * fs_list[fs]) {
0457                 snd_soc_component_write(component, MD_CTL2,
0458                           PSs(ps) | FSs(fs));
0459                 return 0;
0460             }
0461         }
0462     }
0463 
0464     return 0;
0465 }
0466 
0467 static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
0468                 struct snd_pcm_hw_params *params,
0469                 struct snd_soc_dai *dai)
0470 {
0471     struct snd_soc_component *component = dai->component;
0472     struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
0473     u32 rate = clk_get_rate(priv->mcko);
0474 
0475     if (!rate)
0476         rate = params_rate(params) * 256;
0477 
0478     return ak4642_set_mcko(component, rate);
0479 }
0480 
0481 static int ak4642_set_bias_level(struct snd_soc_component *component,
0482                  enum snd_soc_bias_level level)
0483 {
0484     switch (level) {
0485     case SND_SOC_BIAS_OFF:
0486         snd_soc_component_write(component, PW_MGMT1, 0x00);
0487         break;
0488     default:
0489         snd_soc_component_update_bits(component, PW_MGMT1, PMVCM, PMVCM);
0490         break;
0491     }
0492 
0493     return 0;
0494 }
0495 
0496 static const struct snd_soc_dai_ops ak4642_dai_ops = {
0497     .startup    = ak4642_dai_startup,
0498     .shutdown   = ak4642_dai_shutdown,
0499     .set_sysclk = ak4642_dai_set_sysclk,
0500     .set_fmt    = ak4642_dai_set_fmt,
0501     .hw_params  = ak4642_dai_hw_params,
0502 };
0503 
0504 static struct snd_soc_dai_driver ak4642_dai = {
0505     .name = "ak4642-hifi",
0506     .playback = {
0507         .stream_name = "Playback",
0508         .channels_min = 2,
0509         .channels_max = 2,
0510         .rates = SNDRV_PCM_RATE_8000_48000,
0511         .formats = SNDRV_PCM_FMTBIT_S16_LE },
0512     .capture = {
0513         .stream_name = "Capture",
0514         .channels_min = 2,
0515         .channels_max = 2,
0516         .rates = SNDRV_PCM_RATE_8000_48000,
0517         .formats = SNDRV_PCM_FMTBIT_S16_LE },
0518     .ops = &ak4642_dai_ops,
0519     .symmetric_rate = 1,
0520 };
0521 
0522 static int ak4642_suspend(struct snd_soc_component *component)
0523 {
0524     struct regmap *regmap = dev_get_regmap(component->dev, NULL);
0525 
0526     regcache_cache_only(regmap, true);
0527     regcache_mark_dirty(regmap);
0528     return 0;
0529 }
0530 
0531 static int ak4642_resume(struct snd_soc_component *component)
0532 {
0533     struct regmap *regmap = dev_get_regmap(component->dev, NULL);
0534 
0535     regcache_cache_only(regmap, false);
0536     regcache_sync(regmap);
0537     return 0;
0538 }
0539 static int ak4642_probe(struct snd_soc_component *component)
0540 {
0541     struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
0542 
0543     if (priv->mcko)
0544         ak4642_set_mcko(component, clk_get_rate(priv->mcko));
0545 
0546     return 0;
0547 }
0548 
0549 static const struct snd_soc_component_driver soc_component_dev_ak4642 = {
0550     .probe          = ak4642_probe,
0551     .suspend        = ak4642_suspend,
0552     .resume         = ak4642_resume,
0553     .set_bias_level     = ak4642_set_bias_level,
0554     .controls       = ak4642_snd_controls,
0555     .num_controls       = ARRAY_SIZE(ak4642_snd_controls),
0556     .dapm_widgets       = ak4642_dapm_widgets,
0557     .num_dapm_widgets   = ARRAY_SIZE(ak4642_dapm_widgets),
0558     .dapm_routes        = ak4642_intercon,
0559     .num_dapm_routes    = ARRAY_SIZE(ak4642_intercon),
0560     .idle_bias_on       = 1,
0561     .endianness     = 1,
0562 };
0563 
0564 static const struct regmap_config ak4642_regmap = {
0565     .reg_bits       = 8,
0566     .val_bits       = 8,
0567     .max_register       = FIL1_3,
0568     .reg_defaults       = ak4642_reg,
0569     .num_reg_defaults   = NUM_AK4642_REG_DEFAULTS,
0570     .cache_type     = REGCACHE_RBTREE,
0571 };
0572 
0573 static const struct regmap_config ak4643_regmap = {
0574     .reg_bits       = 8,
0575     .val_bits       = 8,
0576     .max_register       = SPK_MS,
0577     .reg_defaults       = ak4643_reg,
0578     .num_reg_defaults   = ARRAY_SIZE(ak4643_reg),
0579     .cache_type     = REGCACHE_RBTREE,
0580 };
0581 
0582 static const struct regmap_config ak4648_regmap = {
0583     .reg_bits       = 8,
0584     .val_bits       = 8,
0585     .max_register       = EQ_FBEQE,
0586     .reg_defaults       = ak4648_reg,
0587     .num_reg_defaults   = ARRAY_SIZE(ak4648_reg),
0588     .cache_type     = REGCACHE_RBTREE,
0589 };
0590 
0591 static const struct ak4642_drvdata ak4642_drvdata = {
0592     .regmap_config = &ak4642_regmap,
0593 };
0594 
0595 static const struct ak4642_drvdata ak4643_drvdata = {
0596     .regmap_config = &ak4643_regmap,
0597 };
0598 
0599 static const struct ak4642_drvdata ak4648_drvdata = {
0600     .regmap_config = &ak4648_regmap,
0601     .extended_frequencies = 1,
0602 };
0603 
0604 #ifdef CONFIG_COMMON_CLK
0605 static struct clk *ak4642_of_parse_mcko(struct device *dev)
0606 {
0607     struct device_node *np = dev->of_node;
0608     struct clk *clk;
0609     const char *clk_name = np->name;
0610     const char *parent_clk_name = NULL;
0611     u32 rate;
0612 
0613     if (of_property_read_u32(np, "clock-frequency", &rate))
0614         return NULL;
0615 
0616     if (of_property_read_bool(np, "clocks"))
0617         parent_clk_name = of_clk_get_parent_name(np, 0);
0618 
0619     of_property_read_string(np, "clock-output-names", &clk_name);
0620 
0621     clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
0622     if (!IS_ERR(clk))
0623         of_clk_add_provider(np, of_clk_src_simple_get, clk);
0624 
0625     return clk;
0626 }
0627 #else
0628 #define ak4642_of_parse_mcko(d) 0
0629 #endif
0630 
0631 static const struct of_device_id ak4642_of_match[];
0632 static const struct i2c_device_id ak4642_i2c_id[];
0633 static int ak4642_i2c_probe(struct i2c_client *i2c)
0634 {
0635     struct device *dev = &i2c->dev;
0636     struct device_node *np = dev->of_node;
0637     const struct ak4642_drvdata *drvdata = NULL;
0638     struct regmap *regmap;
0639     struct ak4642_priv *priv;
0640     struct clk *mcko = NULL;
0641 
0642     if (np) {
0643         const struct of_device_id *of_id;
0644 
0645         mcko = ak4642_of_parse_mcko(dev);
0646         if (IS_ERR(mcko))
0647             mcko = NULL;
0648 
0649         of_id = of_match_device(ak4642_of_match, dev);
0650         if (of_id)
0651             drvdata = of_id->data;
0652     } else {
0653         const struct i2c_device_id *id =
0654             i2c_match_id(ak4642_i2c_id, i2c);
0655         drvdata = (const struct ak4642_drvdata *)id->driver_data;
0656     }
0657 
0658     if (!drvdata) {
0659         dev_err(dev, "Unknown device type\n");
0660         return -EINVAL;
0661     }
0662 
0663     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0664     if (!priv)
0665         return -ENOMEM;
0666 
0667     priv->drvdata = drvdata;
0668     priv->mcko = mcko;
0669 
0670     i2c_set_clientdata(i2c, priv);
0671 
0672     regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
0673     if (IS_ERR(regmap))
0674         return PTR_ERR(regmap);
0675 
0676     return devm_snd_soc_register_component(dev,
0677                 &soc_component_dev_ak4642, &ak4642_dai, 1);
0678 }
0679 
0680 static const struct of_device_id ak4642_of_match[] = {
0681     { .compatible = "asahi-kasei,ak4642",   .data = &ak4642_drvdata},
0682     { .compatible = "asahi-kasei,ak4643",   .data = &ak4643_drvdata},
0683     { .compatible = "asahi-kasei,ak4648",   .data = &ak4648_drvdata},
0684     {},
0685 };
0686 MODULE_DEVICE_TABLE(of, ak4642_of_match);
0687 
0688 static const struct i2c_device_id ak4642_i2c_id[] = {
0689     { "ak4642", (kernel_ulong_t)&ak4642_drvdata },
0690     { "ak4643", (kernel_ulong_t)&ak4643_drvdata },
0691     { "ak4648", (kernel_ulong_t)&ak4648_drvdata },
0692     { }
0693 };
0694 MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
0695 
0696 static struct i2c_driver ak4642_i2c_driver = {
0697     .driver = {
0698         .name = "ak4642-codec",
0699         .of_match_table = ak4642_of_match,
0700     },
0701     .probe_new  = ak4642_i2c_probe,
0702     .id_table   = ak4642_i2c_id,
0703 };
0704 
0705 module_i2c_driver(ak4642_i2c_driver);
0706 
0707 MODULE_DESCRIPTION("Soc AK4642 driver");
0708 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
0709 MODULE_LICENSE("GPL v2");
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