soc/codecs/ak4458.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Audio driver for AK4458
0004  *
0005  * Copyright (C) 2016 Asahi Kasei Microdevices Corporation
0006  * Copyright 2018 NXP
0007  */
0008
0009 #ifndef _AK4458_H
0010 #define _AK4458_H
0011
0012 #include <linux/regmap.h>
0013
0014 /* Settings */
0015
0016 #define AK4458_00_CONTROL1          0x00
0017 #define AK4458_01_CONTROL2          0x01
0018 #define AK4458_02_CONTROL3          0x02
0019 #define AK4458_03_LCHATT            0x03
0020 #define AK4458_04_RCHATT            0x04
0021 #define AK4458_05_CONTROL4          0x05
0022 #define AK4458_06_DSD1              0x06
0023 #define AK4458_07_CONTROL5          0x07
0024 #define AK4458_08_SOUND_CONTROL         0x08
0025 #define AK4458_09_DSD2              0x09
0026 #define AK4458_0A_CONTROL6          0x0A
0027 #define AK4458_0B_CONTROL7          0x0B
0028 #define AK4458_0C_CONTROL8          0x0C
0029 #define AK4458_0D_CONTROL9          0x0D
0030 #define AK4458_0E_CONTROL10         0x0E
0031 #define AK4458_0F_L2CHATT           0x0F
0032 #define AK4458_10_R2CHATT           0x10
0033 #define AK4458_11_L3CHATT           0x11
0034 #define AK4458_12_R3CHATT           0x12
0035 #define AK4458_13_L4CHATT           0x13
0036 #define AK4458_14_R4CHATT           0x14
0037
0038 /* Bitfield Definitions */
0039
0040 /* AK4458_00_CONTROL1 (0x00) Fields
0041  * Addr Register Name  D7     D6    D5    D4    D3    D2    D1    D0
0042  * 00H  Control 1      ACKS   0     0     0     DIF2  DIF1  DIF0  RSTN
0043  */
0044
0045 /* Digital Filter (SD, SLOW, SSLOW) */
0046 #define AK4458_SD_MASK      GENMASK(5, 5)
0047 #define AK4458_SLOW_MASK    GENMASK(0, 0)
0048 #define AK4458_SSLOW_MASK   GENMASK(0, 0)
0049
0050 /* DIF2 1 0
0051  *  x   1 0 MSB justified  Figure 3 (default)
0052  *  x   1 1 I2S Compliment  Figure 4
0053  */
0054 #define AK4458_DIF_SHIFT    1
0055 #define AK4458_DIF_MASK     GENMASK(3, 1)
0056
0057 #define AK4458_DIF_16BIT_LSB    (0 << 1)
0058 #define AK4458_DIF_24BIT_I2S    (3 << 1)
0059 #define AK4458_DIF_32BIT_LSB    (5 << 1)
0060 #define AK4458_DIF_32BIT_MSB    (6 << 1)
0061 #define AK4458_DIF_32BIT_I2S    (7 << 1)
0062
0063 /* AK4458_00_CONTROL1 (0x00) D0 bit */
0064 #define AK4458_RSTN_MASK    GENMASK(0, 0)
0065 #define AK4458_RSTN     (0x1 << 0)
0066
0067 /* AK4458_0A_CONTROL6 Mode bits */
0068 #define AK4458_MODE_SHIFT   6
0069 #define AK4458_MODE_MASK    GENMASK(7, 6)
0070 #define AK4458_MODE_NORMAL  (0 << AK4458_MODE_SHIFT)
0071 #define AK4458_MODE_TDM128  (1 << AK4458_MODE_SHIFT)
0072 #define AK4458_MODE_TDM256  (2 << AK4458_MODE_SHIFT)
0073 #define AK4458_MODE_TDM512  (3 << AK4458_MODE_SHIFT)
0074
0075 /* DAC Digital attenuator transition time setting
0076  * Table 19
0077  * Mode ATS1    ATS2    ATT speed
0078  * 0    0   0   4080/fs
0079  * 1    0   1   2040/fs
0080  * 2    1   0   510/fs
0081  * 3    1   1   255/fs
0082  * */
0083 #define AK4458_ATS_SHIFT    6
0084 #define AK4458_ATS_MASK     GENMASK(7, 6)
0085 #define AK4458_DCHAIN_MASK  (0x1 << 1)
0086
0087 #define AK4458_DSDSEL_MASK      (0x1 << 0)
0088 #define AK4458_DP_MASK          (0x1 << 7)
0089
0090 #endif