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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 
0003 /*
0004  * Based on code by Hu Jin
0005  * Copyright (C) 2014 Asahi Kasei Microdevices Corporation
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/i2c.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <sound/soc.h>
0016 #include <sound/tlv.h>
0017 
0018 /* Registers and fields */
0019 #define AK4375_00_POWER_MANAGEMENT1     0x00
0020 #define PMPLL                   BIT(0)  /* 0: PLL off, 1: PLL on */
0021 #define AK4375_01_POWER_MANAGEMENT2     0x01
0022 #define PMCP1                   BIT(0)  /* Charge Pump 1: LDO1 and DAC */
0023 #define PMCP2                   BIT(1)  /* Charge Pump 2: Class-G HP Amp */
0024 #define PMLDO1P                 BIT(4)
0025 #define PMLDO1N                 BIT(5)
0026 #define PMLDO                   (PMLDO1P | PMLDO1N)
0027 #define AK4375_02_POWER_MANAGEMENT3     0x02
0028 #define AK4375_03_POWER_MANAGEMENT4     0x03
0029 #define AK4375_04_OUTPUT_MODE_SETTING       0x04
0030 #define AK4375_05_CLOCK_MODE_SELECT     0x05
0031 #define FS_MASK                 GENMASK(4, 0)
0032 #define FS_8KHZ                 0x00
0033 #define FS_11_025KHZ                0x01
0034 #define FS_16KHZ                0x04
0035 #define FS_22_05KHZ             0x05
0036 #define FS_32KHZ                0x08
0037 #define FS_44_1KHZ              0x09
0038 #define FS_48KHZ                0x0a
0039 #define FS_88_2KHZ              0x0d
0040 #define FS_96KHZ                0x0e
0041 #define FS_176_4KHZ             0x11
0042 #define FS_192KHZ               0x12
0043 #define CM_MASK                 GENMASK(6, 5)   /* For SRC Bypass mode */
0044 #define CM_0                    (0x0 << 5)
0045 #define CM_1                    (0x1 << 5)
0046 #define CM_2                    (0x2 << 5)
0047 #define CM_3                    (0x3 << 5)
0048 #define AK4375_06_DIGITAL_FILTER_SELECT     0x06
0049 #define DADFSEL                 BIT(5)  /* 0: in SRC Bypass mode, 1: in SRC mode */
0050 #define DASL                    BIT(6)
0051 #define DASD                    BIT(7)
0052 #define AK4375_07_DAC_MONO_MIXING       0x07
0053 #define DACMUTE_MASK                (GENMASK(5, 4) | GENMASK(1, 0)) /* Clear to mute */
0054 #define AK4375_08_JITTER_CLEANER_SETTING1   0x08
0055 #define AK4375_09_JITTER_CLEANER_SETTING2   0x09
0056 #define AK4375_0A_JITTER_CLEANER_SETTING3   0x0a
0057 #define SELDAIN                 BIT(1)  /* 0: SRC Bypass mode, 1: SRC mode */
0058 #define XCKSEL                  BIT(6)  /* 0: PLL0, 1: MCKI */
0059 #define XCKCPSEL                BIT(7)  /* Should be equal to SELDAIN and XCKSEL */
0060 #define AK4375_0B_LCH_OUTPUT_VOLUME     0x0b
0061 #define AK4375_0C_RCH_OUTPUT_VOLUME     0x0c
0062 #define AK4375_0D_HP_VOLUME_CONTROL     0x0d
0063 #define AK4375_0E_PLL_CLK_SOURCE_SELECT     0x0e
0064 #define PLS                 BIT(0)  /* 0: MCKI, 1: BCLK */
0065 #define AK4375_0F_PLL_REF_CLK_DIVIDER1      0x0f    /* Reference clock divider [15:8] bits */
0066 #define AK4375_10_PLL_REF_CLK_DIVIDER2      0x10    /* Reference clock divider [7:0] bis */
0067 #define AK4375_11_PLL_FB_CLK_DIVIDER1       0x11    /* Feedback clock divider [15:8] bits */
0068 #define AK4375_12_PLL_FB_CLK_DIVIDER2       0x12    /* Feedback clock divider [7:0] bits */
0069 #define AK4375_13_SRC_CLK_SOURCE        0x13    /* SRC Bypass: SRCCKS=XCKSEL=SELDAIN=0 */
0070 #define SRCCKS                  BIT(0)  /* SRC Clock source 0: MCKI, 1: PLL0 */
0071 #define DIV                 BIT(4)
0072 #define AK4375_14_DAC_CLK_DIVIDER       0x14
0073 #define AK4375_15_AUDIO_IF_FORMAT       0x15
0074 #define DEVICEID_MASK               GENMASK(7, 5)
0075 #define AK4375_24_MODE_CONTROL          0x24
0076 
0077 #define AK4375_PLL_FREQ_OUT_112896000       112896000   /* 44.1 kHz base rate */
0078 #define AK4375_PLL_FREQ_OUT_122880000       122880000   /* 32 and 48 kHz base rates */
0079 
0080 #define DEVICEID_AK4375             0x00
0081 #define DEVICEID_AK4375A            0x01
0082 #define DEVICEID_AK4376A            0x02
0083 #define DEVICEID_AK4377             0x03
0084 #define DEVICEID_AK4331             0x07
0085 
0086 static const char * const supply_names[] = {
0087     "avdd", "tvdd"
0088 };
0089 
0090 struct ak4375_drvdata {
0091     struct snd_soc_dai_driver *dai_drv;
0092     const struct snd_soc_component_driver *comp_drv;
0093 };
0094 
0095 struct ak4375_priv {
0096     struct device *dev;
0097     struct regmap *regmap;
0098     struct gpio_desc *pdn_gpiod;
0099     struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
0100     unsigned int rate;
0101     unsigned int pld;
0102     u8 mute_save;
0103 };
0104 
0105 static const struct reg_default ak4375_reg_defaults[] = {
0106     { 0x00, 0x00 }, { 0x01, 0x00 }, { 0x02, 0x00 },
0107     { 0x03, 0x00 }, { 0x04, 0x00 }, { 0x05, 0x00 },
0108     { 0x06, 0x00 }, { 0x07, 0x00 }, { 0x08, 0x00 },
0109     { 0x09, 0x00 }, { 0x0a, 0x00 }, { 0x0b, 0x19 },
0110     { 0x0c, 0x19 }, { 0x0d, 0x75 }, { 0x0e, 0x01 },
0111     { 0x0f, 0x00 }, { 0x10, 0x00 }, { 0x11, 0x00 },
0112     { 0x12, 0x00 }, { 0x13, 0x00 }, { 0x14, 0x00 },
0113     { 0x15, 0x00 }, { 0x24, 0x00 },
0114 };
0115 
0116 /*
0117  * Output Digital volume control:
0118  * from -12.5 to 3 dB in 0.5 dB steps (mute instead of -12.5 dB)
0119  */
0120 static DECLARE_TLV_DB_SCALE(dac_tlv, -1250, 50, 0);
0121 
0122 /*
0123  * HP-Amp Analog volume control:
0124  * from -4.2 to 6 dB in 2 dB steps (mute instead of -4.2 dB)
0125  */
0126 static DECLARE_TLV_DB_SCALE(hpg_tlv, -4200, 20, 0);
0127 
0128 static const char * const ak4375_ovolcn_select_texts[]  = { "Dependent", "Independent" };
0129 static const char * const ak4375_mdac_select_texts[]    = { "x1", "x1/2" };
0130 static const char * const ak4375_cpmode_select_texts[]  = {
0131     "Automatic Switching",
0132     "+-VDD Operation",
0133     "+-1/2VDD Operation"
0134 };
0135 
0136 /*
0137  * DASD, DASL bits Digital Filter Setting
0138  * 0, 0 : Sharp Roll-Off Filter
0139  * 0, 1 : Slow Roll-Off Filter
0140  * 1, 0 : Short delay Sharp Roll-Off Filter
0141  * 1, 1 : Short delay Slow Roll-Off Filter
0142  */
0143 static const char * const ak4375_digfil_select_texts[] = {
0144     "Sharp Roll-Off Filter",
0145     "Slow Roll-Off Filter",
0146     "Short delay Sharp Roll-Off Filter",
0147     "Short delay Slow Roll-Off Filter",
0148 };
0149 
0150 static const struct soc_enum ak4375_ovolcn_enum =
0151     SOC_ENUM_SINGLE(AK4375_0B_LCH_OUTPUT_VOLUME, 7,
0152             ARRAY_SIZE(ak4375_ovolcn_select_texts), ak4375_ovolcn_select_texts);
0153 static const struct soc_enum ak4375_mdacl_enum =
0154     SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 2,
0155             ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
0156 static const struct soc_enum ak4375_mdacr_enum =
0157     SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 6,
0158             ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
0159 static const struct soc_enum ak4375_cpmode_enum =
0160     SOC_ENUM_SINGLE(AK4375_03_POWER_MANAGEMENT4, 2,
0161             ARRAY_SIZE(ak4375_cpmode_select_texts), ak4375_cpmode_select_texts);
0162 static const struct soc_enum ak4375_digfil_enum =
0163     SOC_ENUM_SINGLE(AK4375_06_DIGITAL_FILTER_SELECT, 6,
0164             ARRAY_SIZE(ak4375_digfil_select_texts), ak4375_digfil_select_texts);
0165 
0166 static const struct snd_kcontrol_new ak4375_snd_controls[] = {
0167     SOC_DOUBLE_R_TLV("Digital Output Volume", AK4375_0B_LCH_OUTPUT_VOLUME,
0168              AK4375_0C_RCH_OUTPUT_VOLUME, 0, 0x1f, 0, dac_tlv),
0169     SOC_SINGLE_TLV("HP-Amp Analog Volume",
0170                AK4375_0D_HP_VOLUME_CONTROL, 0, 0x1f, 0, hpg_tlv),
0171 
0172     SOC_DOUBLE("DAC Signal Invert Switch", AK4375_07_DAC_MONO_MIXING, 3, 7, 1, 0),
0173 
0174     SOC_ENUM("Digital Volume Control", ak4375_ovolcn_enum),
0175     SOC_ENUM("DACL Signal Level", ak4375_mdacl_enum),
0176     SOC_ENUM("DACR Signal Level", ak4375_mdacr_enum),
0177     SOC_ENUM("Charge Pump Mode", ak4375_cpmode_enum),
0178     SOC_ENUM("DAC Digital Filter Mode", ak4375_digfil_enum),
0179 };
0180 
0181 static const struct snd_kcontrol_new ak4375_hpl_mixer_controls[] = {
0182     SOC_DAPM_SINGLE("LDACL Switch", AK4375_07_DAC_MONO_MIXING, 0, 1, 0),
0183     SOC_DAPM_SINGLE("RDACL Switch", AK4375_07_DAC_MONO_MIXING, 1, 1, 0),
0184 };
0185 
0186 static const struct snd_kcontrol_new ak4375_hpr_mixer_controls[] = {
0187     SOC_DAPM_SINGLE("LDACR Switch", AK4375_07_DAC_MONO_MIXING, 4, 1, 0),
0188     SOC_DAPM_SINGLE("RDACR Switch", AK4375_07_DAC_MONO_MIXING, 5, 1, 0),
0189 };
0190 
0191 static int ak4375_dac_event(struct snd_soc_dapm_widget *w,
0192                 struct snd_kcontrol *kcontrol, int event)
0193 {
0194     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0195 
0196     switch (event) {
0197     case SND_SOC_DAPM_PRE_PMU:
0198         snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, PMPLL);
0199         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, PMCP1);
0200         usleep_range(6500, 7000);
0201         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, PMLDO);
0202         usleep_range(1000, 2000);
0203         break;
0204     case SND_SOC_DAPM_POST_PMU:
0205         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, PMCP2);
0206         usleep_range(4500, 5000);
0207         break;
0208     case SND_SOC_DAPM_PRE_PMD:
0209         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, 0x0);
0210         break;
0211     case SND_SOC_DAPM_POST_PMD:
0212         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, 0x0);
0213         snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, 0x0);
0214         snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, 0x0);
0215         break;
0216     }
0217 
0218     return 0;
0219 }
0220 
0221 static const struct snd_soc_dapm_widget ak4375_dapm_widgets[] = {
0222     SND_SOC_DAPM_DAC_E("DAC", NULL, AK4375_02_POWER_MANAGEMENT3, 0, 0, ak4375_dac_event,
0223                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0224                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0225 
0226     SND_SOC_DAPM_AIF_IN("SDTI", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
0227 
0228     SND_SOC_DAPM_OUTPUT("HPL"),
0229     SND_SOC_DAPM_OUTPUT("HPR"),
0230 
0231     SND_SOC_DAPM_MIXER("HPR Mixer", AK4375_03_POWER_MANAGEMENT4, 1, 0,
0232                &ak4375_hpr_mixer_controls[0], ARRAY_SIZE(ak4375_hpr_mixer_controls)),
0233     SND_SOC_DAPM_MIXER("HPL Mixer", AK4375_03_POWER_MANAGEMENT4, 0, 0,
0234                &ak4375_hpl_mixer_controls[0], ARRAY_SIZE(ak4375_hpl_mixer_controls)),
0235 };
0236 
0237 static const struct snd_soc_dapm_route ak4375_intercon[] = {
0238     { "DAC",    NULL,       "SDTI" },
0239 
0240     { "HPL Mixer",  "LDACL Switch", "DAC" },
0241     { "HPL Mixer",  "RDACL Switch", "DAC" },
0242     { "HPR Mixer",  "LDACR Switch", "DAC" },
0243     { "HPR Mixer",  "RDACR Switch", "DAC" },
0244 
0245     { "HPL",    NULL,       "HPL Mixer" },
0246     { "HPR",    NULL,       "HPR Mixer" },
0247 };
0248 
0249 static int ak4375_hw_params(struct snd_pcm_substream *substream,
0250                 struct snd_pcm_hw_params *params,
0251                 struct snd_soc_dai *dai)
0252 {
0253     struct snd_soc_component *component = dai->component;
0254     struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
0255     unsigned int freq_in, freq_out;
0256 
0257     ak4375->rate = params_rate(params);
0258 
0259     if (ak4375->rate <= 96000)
0260         ak4375->pld = 0;
0261     else
0262         ak4375->pld = 1;
0263 
0264     freq_in = 32 * ak4375->rate / (ak4375->pld + 1);
0265 
0266     if ((ak4375->rate % 8000) == 0)
0267         freq_out = AK4375_PLL_FREQ_OUT_122880000;
0268     else
0269         freq_out = AK4375_PLL_FREQ_OUT_112896000;
0270 
0271     return snd_soc_dai_set_pll(dai, 0, 0, freq_in, freq_out);
0272 }
0273 
0274 static int ak4375_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
0275                   unsigned int freq_in, unsigned int freq_out)
0276 {
0277     struct snd_soc_component *component = dai->component;
0278     struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
0279     unsigned int mclk, plm, mdiv, div;
0280     u8 cms, fs, cm;
0281 
0282     cms = snd_soc_component_read(component, AK4375_05_CLOCK_MODE_SELECT);
0283     fs = cms & ~FS_MASK;
0284     cm = cms & ~CM_MASK;
0285 
0286     switch (ak4375->rate) {
0287     case 8000:
0288         fs |= FS_8KHZ;
0289         break;
0290     case 11025:
0291         fs |= FS_11_025KHZ;
0292         break;
0293     case 16000:
0294         fs |= FS_16KHZ;
0295         break;
0296     case 22050:
0297         fs |= FS_22_05KHZ;
0298         break;
0299     case 32000:
0300         fs |= FS_32KHZ;
0301         break;
0302     case 44100:
0303         fs |= FS_44_1KHZ;
0304         break;
0305     case 48000:
0306         fs |= FS_48KHZ;
0307         break;
0308     case 88200:
0309         fs |= FS_88_2KHZ;
0310         break;
0311     case 96000:
0312         fs |= FS_96KHZ;
0313         break;
0314     case 176400:
0315         fs |= FS_176_4KHZ;
0316         break;
0317     case 192000:
0318         fs |= FS_192KHZ;
0319         break;
0320     default:
0321         return -EINVAL;
0322     }
0323 
0324     if (ak4375->rate <= 24000) {
0325         cm |= CM_1;
0326         mclk = 512 * ak4375->rate;
0327         mdiv = freq_out / mclk - 1;
0328         div = 0;
0329     } else if (ak4375->rate <= 96000) {
0330         cm |= CM_0;
0331         mclk = 256 * ak4375->rate;
0332         mdiv = freq_out / mclk - 1;
0333         div = 0;
0334     } else {
0335         cm |= CM_3;
0336         mclk = 128 * ak4375->rate;
0337         mdiv = 4;
0338         div = 1;
0339     }
0340 
0341     /* Writing both fields in one go seems to make playback choppy on start */
0342     snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, FS_MASK, fs);
0343     snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, CM_MASK, cm);
0344 
0345     snd_soc_component_write(component, AK4375_0F_PLL_REF_CLK_DIVIDER1,
0346                 (ak4375->pld & 0xff00) >> 8);
0347     snd_soc_component_write(component, AK4375_10_PLL_REF_CLK_DIVIDER2,
0348                 ak4375->pld & 0x00ff);
0349 
0350     plm = freq_out / freq_in - 1;
0351     snd_soc_component_write(component, AK4375_11_PLL_FB_CLK_DIVIDER1, (plm & 0xff00) >> 8);
0352     snd_soc_component_write(component, AK4375_12_PLL_FB_CLK_DIVIDER2, plm & 0x00ff);
0353 
0354     snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, DIV, div);
0355 
0356     /* SRCCKS bit: force to 1 for SRC PLL source clock */
0357     snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, SRCCKS, SRCCKS);
0358 
0359     snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv);
0360 
0361     dev_dbg(ak4375->dev, "rate=%d mclk=%d f_in=%d f_out=%d PLD=%d PLM=%d MDIV=%d DIV=%d\n",
0362         ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div);
0363 
0364     return 0;
0365 }
0366 
0367 static int ak4375_mute(struct snd_soc_dai *dai, int mute, int direction)
0368 {
0369     struct snd_soc_component *component = dai->component;
0370     struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
0371     u8 val = snd_soc_component_read(component, AK4375_07_DAC_MONO_MIXING);
0372 
0373     dev_dbg(ak4375->dev, "mute=%d val=%d\n", mute, val);
0374 
0375     if (mute) {
0376         ak4375->mute_save = val & DACMUTE_MASK;
0377         val &= ~DACMUTE_MASK;
0378     } else {
0379         val |= ak4375->mute_save;
0380     }
0381 
0382     snd_soc_component_write(component, AK4375_07_DAC_MONO_MIXING, val);
0383 
0384     return 0;
0385 }
0386 
0387 #define AK4375_RATES    (SNDRV_PCM_RATE_8000_48000 |\
0388              SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\
0389              SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
0390 
0391 #define AK4375_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE |\
0392              SNDRV_PCM_FMTBIT_S24_LE |\
0393              SNDRV_PCM_FMTBIT_S32_LE)
0394 
0395 static const struct snd_soc_dai_ops ak4375_dai_ops = {
0396     .hw_params  = ak4375_hw_params,
0397     .mute_stream    = ak4375_mute,
0398     .set_pll    = ak4375_dai_set_pll,
0399 };
0400 
0401 static struct snd_soc_dai_driver ak4375_dai = {
0402     .name = "ak4375-hifi",
0403     .playback = {
0404         .stream_name    = "HiFi Playback",
0405         .channels_min   = 1,
0406         .channels_max   = 2,
0407         .rates      = AK4375_RATES,
0408         .rate_min   = 8000,
0409         .rate_max   = 192000,
0410         .formats    = AK4375_FORMATS,
0411     },
0412     .ops = &ak4375_dai_ops,
0413 };
0414 
0415 static void ak4375_power_off(struct ak4375_priv *ak4375)
0416 {
0417     gpiod_set_value_cansleep(ak4375->pdn_gpiod, 0);
0418     usleep_range(1000, 2000);
0419 
0420     regulator_bulk_disable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
0421 }
0422 
0423 static int ak4375_power_on(struct ak4375_priv *ak4375)
0424 {
0425     int ret;
0426 
0427     ret = regulator_bulk_enable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
0428     if (ret < 0) {
0429         dev_err(ak4375->dev, "Failed to enable regulators: %d\n", ret);
0430         return ret;
0431     }
0432 
0433     usleep_range(3000, 4000);
0434 
0435     gpiod_set_value_cansleep(ak4375->pdn_gpiod, 1);
0436     usleep_range(1000, 2000);
0437 
0438     return 0;
0439 }
0440 
0441 static int __maybe_unused ak4375_runtime_suspend(struct device *dev)
0442 {
0443     struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
0444 
0445     regcache_cache_only(ak4375->regmap, true);
0446     ak4375_power_off(ak4375);
0447 
0448     return 0;
0449 }
0450 
0451 static int __maybe_unused ak4375_runtime_resume(struct device *dev)
0452 {
0453     struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
0454     int ret;
0455 
0456     ret = ak4375_power_on(ak4375);
0457     if (ret < 0)
0458         return ret;
0459 
0460     regcache_cache_only(ak4375->regmap, false);
0461     regcache_mark_dirty(ak4375->regmap);
0462 
0463     return regcache_sync(ak4375->regmap);
0464 }
0465 
0466 static const struct snd_soc_component_driver soc_codec_dev_ak4375 = {
0467     .controls       = ak4375_snd_controls,
0468     .num_controls       = ARRAY_SIZE(ak4375_snd_controls),
0469     .dapm_widgets       = ak4375_dapm_widgets,
0470     .num_dapm_widgets   = ARRAY_SIZE(ak4375_dapm_widgets),
0471     .dapm_routes        = ak4375_intercon,
0472     .num_dapm_routes    = ARRAY_SIZE(ak4375_intercon),
0473     .idle_bias_on       = 1,
0474     .use_pmdown_time    = 1,
0475     .endianness     = 1,
0476 };
0477 
0478 static const struct regmap_config ak4375_regmap = {
0479     .reg_bits       = 8,
0480     .val_bits       = 8,
0481     .max_register       = AK4375_24_MODE_CONTROL,
0482     .reg_defaults       = ak4375_reg_defaults,
0483     .num_reg_defaults   = ARRAY_SIZE(ak4375_reg_defaults),
0484     .cache_type     = REGCACHE_RBTREE,
0485 };
0486 
0487 static const struct ak4375_drvdata ak4375_drvdata = {
0488     .dai_drv = &ak4375_dai,
0489     .comp_drv = &soc_codec_dev_ak4375,
0490 };
0491 
0492 static const struct dev_pm_ops ak4375_pm = {
0493     SET_RUNTIME_PM_OPS(ak4375_runtime_suspend, ak4375_runtime_resume, NULL)
0494     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0495                 pm_runtime_force_resume)
0496 };
0497 
0498 static int ak4375_i2c_probe(struct i2c_client *i2c)
0499 {
0500     struct ak4375_priv *ak4375;
0501     const struct ak4375_drvdata *drvdata;
0502     unsigned int deviceid;
0503     int ret, i;
0504 
0505     ak4375 = devm_kzalloc(&i2c->dev, sizeof(*ak4375), GFP_KERNEL);
0506     if (!ak4375)
0507         return -ENOMEM;
0508 
0509     ak4375->regmap = devm_regmap_init_i2c(i2c, &ak4375_regmap);
0510     if (IS_ERR(ak4375->regmap))
0511         return PTR_ERR(ak4375->regmap);
0512 
0513     i2c_set_clientdata(i2c, ak4375);
0514     ak4375->dev = &i2c->dev;
0515 
0516     drvdata = of_device_get_match_data(&i2c->dev);
0517 
0518     for (i = 0; i < ARRAY_SIZE(supply_names); i++)
0519         ak4375->supplies[i].supply = supply_names[i];
0520 
0521     ret = devm_regulator_bulk_get(ak4375->dev, ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
0522     if (ret < 0) {
0523         dev_err(ak4375->dev, "Failed to get regulators: %d\n", ret);
0524         return ret;
0525     }
0526 
0527     ak4375->pdn_gpiod = devm_gpiod_get_optional(ak4375->dev, "pdn", GPIOD_OUT_LOW);
0528     if (IS_ERR(ak4375->pdn_gpiod))
0529         return dev_err_probe(ak4375->dev, PTR_ERR(ak4375->pdn_gpiod),
0530                      "failed to get pdn\n");
0531 
0532     ret = ak4375_power_on(ak4375);
0533     if (ret < 0)
0534         return ret;
0535 
0536     /* Don't read deviceid from cache */
0537     regcache_cache_bypass(ak4375->regmap, true);
0538 
0539     ret = regmap_read(ak4375->regmap, AK4375_15_AUDIO_IF_FORMAT, &deviceid);
0540     if (ret < 0) {
0541         dev_err(ak4375->dev, "unable to read DEVICEID!\n");
0542         return ret;
0543     }
0544 
0545     regcache_cache_bypass(ak4375->regmap, false);
0546 
0547     deviceid = (deviceid & DEVICEID_MASK) >> 5;
0548 
0549     switch (deviceid) {
0550     case DEVICEID_AK4331:
0551         dev_err(ak4375->dev, "found untested AK4331\n");
0552         return -EINVAL;
0553     case DEVICEID_AK4375:
0554         dev_dbg(ak4375->dev, "found AK4375\n");
0555         break;
0556     case DEVICEID_AK4375A:
0557         dev_dbg(ak4375->dev, "found AK4375A\n");
0558         break;
0559     case DEVICEID_AK4376A:
0560         dev_err(ak4375->dev, "found unsupported AK4376/A!\n");
0561         return -EINVAL;
0562     case DEVICEID_AK4377:
0563         dev_err(ak4375->dev, "found unsupported AK4377!\n");
0564         return -EINVAL;
0565     default:
0566         dev_err(ak4375->dev, "unrecognized DEVICEID!\n");
0567         return -EINVAL;
0568     }
0569 
0570     pm_runtime_set_active(ak4375->dev);
0571     pm_runtime_enable(ak4375->dev);
0572 
0573     ret = devm_snd_soc_register_component(ak4375->dev, drvdata->comp_drv,
0574                           drvdata->dai_drv, 1);
0575     if (ret < 0) {
0576         dev_err(ak4375->dev, "Failed to register CODEC: %d\n", ret);
0577         return ret;
0578     }
0579 
0580     return 0;
0581 }
0582 
0583 static int ak4375_i2c_remove(struct i2c_client *i2c)
0584 {
0585     pm_runtime_disable(&i2c->dev);
0586 
0587     return 0;
0588 }
0589 
0590 static const struct of_device_id ak4375_of_match[] = {
0591     { .compatible = "asahi-kasei,ak4375", .data = &ak4375_drvdata },
0592     { },
0593 };
0594 MODULE_DEVICE_TABLE(of, ak4375_of_match);
0595 
0596 static struct i2c_driver ak4375_i2c_driver = {
0597     .driver = {
0598         .name = "ak4375",
0599         .pm = &ak4375_pm,
0600         .of_match_table = ak4375_of_match,
0601     },
0602     .probe_new = ak4375_i2c_probe,
0603     .remove = ak4375_i2c_remove,
0604 };
0605 module_i2c_driver(ak4375_i2c_driver);
0606 
0607 MODULE_AUTHOR("Vincent Knecht <vincent.knecht@mailoo.org>");
0608 MODULE_DESCRIPTION("ASoC AK4375 DAC driver");
0609 MODULE_LICENSE("GPL");
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