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0010 #include <linux/module.h>
0011 #include <linux/kernel.h>
0012 #include <linux/regmap.h>
0013 #include <linux/slab.h>
0014
0015 #include <sound/pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/soc.h>
0018 #include <sound/tlv.h>
0019
0020 #include "adav80x.h"
0021
0022 #define ADAV80X_PLAYBACK_CTRL 0x04
0023 #define ADAV80X_AUX_IN_CTRL 0x05
0024 #define ADAV80X_REC_CTRL 0x06
0025 #define ADAV80X_AUX_OUT_CTRL 0x07
0026 #define ADAV80X_DPATH_CTRL1 0x62
0027 #define ADAV80X_DPATH_CTRL2 0x63
0028 #define ADAV80X_DAC_CTRL1 0x64
0029 #define ADAV80X_DAC_CTRL2 0x65
0030 #define ADAV80X_DAC_CTRL3 0x66
0031 #define ADAV80X_DAC_L_VOL 0x68
0032 #define ADAV80X_DAC_R_VOL 0x69
0033 #define ADAV80X_PGA_L_VOL 0x6c
0034 #define ADAV80X_PGA_R_VOL 0x6d
0035 #define ADAV80X_ADC_CTRL1 0x6e
0036 #define ADAV80X_ADC_CTRL2 0x6f
0037 #define ADAV80X_ADC_L_VOL 0x70
0038 #define ADAV80X_ADC_R_VOL 0x71
0039 #define ADAV80X_PLL_CTRL1 0x74
0040 #define ADAV80X_PLL_CTRL2 0x75
0041 #define ADAV80X_ICLK_CTRL1 0x76
0042 #define ADAV80X_ICLK_CTRL2 0x77
0043 #define ADAV80X_PLL_CLK_SRC 0x78
0044 #define ADAV80X_PLL_OUTE 0x7a
0045
0046 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
0047 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
0048 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
0049
0050 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5)
0051 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2)
0052 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src)
0053 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3)
0054
0055 #define ADAV80X_PLL_CTRL1_PLLDIV 0x10
0056 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
0057 #define ADAV80X_PLL_CTRL1_XTLPD 0x02
0058
0059 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
0060
0061 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
0062 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
0063 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
0064
0065 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
0066 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
0067 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
0068
0069 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80
0070 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00
0071 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80
0072
0073 #define ADAV80X_DAC_CTRL1_PD 0x80
0074
0075 #define ADAV80X_DAC_CTRL2_DIV1 0x00
0076 #define ADAV80X_DAC_CTRL2_DIV1_5 0x10
0077 #define ADAV80X_DAC_CTRL2_DIV2 0x20
0078 #define ADAV80X_DAC_CTRL2_DIV3 0x30
0079 #define ADAV80X_DAC_CTRL2_DIV_MASK 0x30
0080
0081 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00
0082 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40
0083 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80
0084 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0
0085
0086 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00
0087 #define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01
0088 #define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02
0089 #define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03
0090 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01
0091
0092 #define ADAV80X_CAPTURE_MODE_MASTER 0x20
0093 #define ADAV80X_CAPTURE_WORD_LEN24 0x00
0094 #define ADAV80X_CAPTURE_WORD_LEN20 0x04
0095 #define ADAV80X_CAPTRUE_WORD_LEN18 0x08
0096 #define ADAV80X_CAPTURE_WORD_LEN16 0x0c
0097 #define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c
0098
0099 #define ADAV80X_CAPTURE_MODE_LEFT_J 0x00
0100 #define ADAV80X_CAPTURE_MODE_I2S 0x01
0101 #define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03
0102 #define ADAV80X_CAPTURE_MODE_MASK 0x03
0103
0104 #define ADAV80X_PLAYBACK_MODE_MASTER 0x10
0105 #define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00
0106 #define ADAV80X_PLAYBACK_MODE_I2S 0x01
0107 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04
0108 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05
0109 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06
0110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07
0111 #define ADAV80X_PLAYBACK_MODE_MASK 0x07
0112
0113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
0114
0115 static const struct reg_default adav80x_reg_defaults[] = {
0116 { ADAV80X_PLAYBACK_CTRL, 0x01 },
0117 { ADAV80X_AUX_IN_CTRL, 0x01 },
0118 { ADAV80X_REC_CTRL, 0x02 },
0119 { ADAV80X_AUX_OUT_CTRL, 0x01 },
0120 { ADAV80X_DPATH_CTRL1, 0xc0 },
0121 { ADAV80X_DPATH_CTRL2, 0x11 },
0122 { ADAV80X_DAC_CTRL1, 0x00 },
0123 { ADAV80X_DAC_CTRL2, 0x00 },
0124 { ADAV80X_DAC_CTRL3, 0x00 },
0125 { ADAV80X_DAC_L_VOL, 0xff },
0126 { ADAV80X_DAC_R_VOL, 0xff },
0127 { ADAV80X_PGA_L_VOL, 0x00 },
0128 { ADAV80X_PGA_R_VOL, 0x00 },
0129 { ADAV80X_ADC_CTRL1, 0x00 },
0130 { ADAV80X_ADC_CTRL2, 0x00 },
0131 { ADAV80X_ADC_L_VOL, 0xff },
0132 { ADAV80X_ADC_R_VOL, 0xff },
0133 { ADAV80X_PLL_CTRL1, 0x00 },
0134 { ADAV80X_PLL_CTRL2, 0x00 },
0135 { ADAV80X_ICLK_CTRL1, 0x00 },
0136 { ADAV80X_ICLK_CTRL2, 0x00 },
0137 { ADAV80X_PLL_CLK_SRC, 0x00 },
0138 { ADAV80X_PLL_OUTE, 0x00 },
0139 };
0140
0141 struct adav80x {
0142 struct regmap *regmap;
0143
0144 enum adav80x_clk_src clk_src;
0145 unsigned int sysclk;
0146 enum adav80x_pll_src pll_src;
0147
0148 unsigned int dai_fmt[2];
0149 unsigned int rate;
0150 bool deemph;
0151 bool sysclk_pd[3];
0152 };
0153
0154 static const char *adav80x_mux_text[] = {
0155 "ADC",
0156 "Playback",
0157 "Aux Playback",
0158 };
0159
0160 static const unsigned int adav80x_mux_values[] = {
0161 0, 2, 3,
0162 };
0163
0164 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \
0165 SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \
0166 ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \
0167 adav80x_mux_values)
0168
0169 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0);
0170 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
0171 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
0172
0173 static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
0174 SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
0175 static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
0176 SOC_DAPM_ENUM("Route", adav80x_capture_enum);
0177 static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
0178 SOC_DAPM_ENUM("Route", adav80x_dac_enum);
0179
0180 #define ADAV80X_MUX(name, ctrl) \
0181 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
0182
0183 static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
0184 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
0185 SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1),
0186
0187 SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0),
0188 SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0),
0189
0190 SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
0191 SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
0192
0193 SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0),
0194 SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0),
0195
0196 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
0197 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
0198 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
0199
0200 SND_SOC_DAPM_INPUT("VINR"),
0201 SND_SOC_DAPM_INPUT("VINL"),
0202 SND_SOC_DAPM_OUTPUT("VOUTR"),
0203 SND_SOC_DAPM_OUTPUT("VOUTL"),
0204
0205 SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
0206 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
0207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
0208 SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0),
0209 };
0210
0211 static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source,
0212 struct snd_soc_dapm_widget *sink)
0213 {
0214 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0215 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0216 const char *clk;
0217
0218 switch (adav80x->clk_src) {
0219 case ADAV80X_CLK_PLL1:
0220 clk = "PLL1";
0221 break;
0222 case ADAV80X_CLK_PLL2:
0223 clk = "PLL2";
0224 break;
0225 case ADAV80X_CLK_XTAL:
0226 clk = "OSC";
0227 break;
0228 default:
0229 return 0;
0230 }
0231
0232 return strcmp(source->name, clk) == 0;
0233 }
0234
0235 static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source,
0236 struct snd_soc_dapm_widget *sink)
0237 {
0238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0239 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0240
0241 return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL;
0242 }
0243
0244
0245 static const struct snd_soc_dapm_route adav80x_dapm_routes[] = {
0246 { "DAC Select", "ADC", "ADC" },
0247 { "DAC Select", "Playback", "AIFIN" },
0248 { "DAC Select", "Aux Playback", "AIFAUXIN" },
0249 { "DAC", NULL, "DAC Select" },
0250
0251 { "Capture Select", "ADC", "ADC" },
0252 { "Capture Select", "Playback", "AIFIN" },
0253 { "Capture Select", "Aux Playback", "AIFAUXIN" },
0254 { "AIFOUT", NULL, "Capture Select" },
0255
0256 { "Aux Capture Select", "ADC", "ADC" },
0257 { "Aux Capture Select", "Playback", "AIFIN" },
0258 { "Aux Capture Select", "Aux Playback", "AIFAUXIN" },
0259 { "AIFAUXOUT", NULL, "Aux Capture Select" },
0260
0261 { "VOUTR", NULL, "DAC" },
0262 { "VOUTL", NULL, "DAC" },
0263
0264 { "Left PGA", NULL, "VINL" },
0265 { "Right PGA", NULL, "VINR" },
0266 { "ADC", NULL, "Left PGA" },
0267 { "ADC", NULL, "Right PGA" },
0268
0269 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
0270 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
0271 { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check },
0272 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
0273 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
0274
0275 { "ADC", NULL, "SYSCLK" },
0276 { "DAC", NULL, "SYSCLK" },
0277 { "AIFOUT", NULL, "SYSCLK" },
0278 { "AIFAUXOUT", NULL, "SYSCLK" },
0279 { "AIFIN", NULL, "SYSCLK" },
0280 { "AIFAUXIN", NULL, "SYSCLK" },
0281 };
0282
0283 static int adav80x_set_deemph(struct snd_soc_component *component)
0284 {
0285 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0286 unsigned int val;
0287
0288 if (adav80x->deemph) {
0289 switch (adav80x->rate) {
0290 case 32000:
0291 val = ADAV80X_DAC_CTRL2_DEEMPH_32;
0292 break;
0293 case 44100:
0294 val = ADAV80X_DAC_CTRL2_DEEMPH_44;
0295 break;
0296 case 48000:
0297 case 64000:
0298 case 88200:
0299 case 96000:
0300 val = ADAV80X_DAC_CTRL2_DEEMPH_48;
0301 break;
0302 default:
0303 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
0304 break;
0305 }
0306 } else {
0307 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
0308 }
0309
0310 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
0311 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
0312 }
0313
0314 static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
0315 struct snd_ctl_elem_value *ucontrol)
0316 {
0317 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0318 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0319 unsigned int deemph = ucontrol->value.integer.value[0];
0320
0321 if (deemph > 1)
0322 return -EINVAL;
0323
0324 adav80x->deemph = deemph;
0325
0326 return adav80x_set_deemph(component);
0327 }
0328
0329 static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
0330 struct snd_ctl_elem_value *ucontrol)
0331 {
0332 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0333 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0334
0335 ucontrol->value.integer.value[0] = adav80x->deemph;
0336 return 0;
0337 };
0338
0339 static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0);
0340 static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0);
0341
0342 static const struct snd_kcontrol_new adav80x_controls[] = {
0343 SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL,
0344 ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
0345 SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL,
0346 ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
0347
0348 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL,
0349 ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv),
0350
0351 SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0),
0352 SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1),
0353
0354 SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0),
0355
0356 SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0,
0357 adav80x_get_deemph, adav80x_put_deemph),
0358 };
0359
0360 static unsigned int adav80x_port_ctrl_regs[2][2] = {
0361 { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, },
0362 { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL },
0363 };
0364
0365 static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0366 {
0367 struct snd_soc_component *component = dai->component;
0368 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0369 unsigned int capture = 0x00;
0370 unsigned int playback = 0x00;
0371
0372 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0373 case SND_SOC_DAIFMT_CBP_CFP:
0374 capture |= ADAV80X_CAPTURE_MODE_MASTER;
0375 playback |= ADAV80X_PLAYBACK_MODE_MASTER;
0376 break;
0377 case SND_SOC_DAIFMT_CBC_CFC:
0378 break;
0379 default:
0380 return -EINVAL;
0381 }
0382
0383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0384 case SND_SOC_DAIFMT_I2S:
0385 capture |= ADAV80X_CAPTURE_MODE_I2S;
0386 playback |= ADAV80X_PLAYBACK_MODE_I2S;
0387 break;
0388 case SND_SOC_DAIFMT_LEFT_J:
0389 capture |= ADAV80X_CAPTURE_MODE_LEFT_J;
0390 playback |= ADAV80X_PLAYBACK_MODE_LEFT_J;
0391 break;
0392 case SND_SOC_DAIFMT_RIGHT_J:
0393 capture |= ADAV80X_CAPTURE_MODE_RIGHT_J;
0394 playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
0395 break;
0396 default:
0397 return -EINVAL;
0398 }
0399
0400 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0401 case SND_SOC_DAIFMT_NB_NF:
0402 break;
0403 default:
0404 return -EINVAL;
0405 }
0406
0407 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
0408 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
0409 capture);
0410 regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
0411 playback);
0412
0413 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0414
0415 return 0;
0416 }
0417
0418 static int adav80x_set_adc_clock(struct snd_soc_component *component,
0419 unsigned int sample_rate)
0420 {
0421 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0422 unsigned int val;
0423
0424 if (sample_rate <= 48000)
0425 val = ADAV80X_ADC_CTRL1_MODULATOR_128FS;
0426 else
0427 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
0428
0429 regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
0430 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
0431
0432 return 0;
0433 }
0434
0435 static int adav80x_set_dac_clock(struct snd_soc_component *component,
0436 unsigned int sample_rate)
0437 {
0438 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0439 unsigned int val;
0440
0441 if (sample_rate <= 48000)
0442 val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS;
0443 else
0444 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
0445
0446 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
0447 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
0448 val);
0449
0450 return 0;
0451 }
0452
0453 static int adav80x_set_capture_pcm_format(struct snd_soc_component *component,
0454 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
0455 {
0456 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0457 unsigned int val;
0458
0459 switch (params_width(params)) {
0460 case 16:
0461 val = ADAV80X_CAPTURE_WORD_LEN16;
0462 break;
0463 case 18:
0464 val = ADAV80X_CAPTRUE_WORD_LEN18;
0465 break;
0466 case 20:
0467 val = ADAV80X_CAPTURE_WORD_LEN20;
0468 break;
0469 case 24:
0470 val = ADAV80X_CAPTURE_WORD_LEN24;
0471 break;
0472 default:
0473 return -EINVAL;
0474 }
0475
0476 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
0477 ADAV80X_CAPTURE_WORD_LEN_MASK, val);
0478
0479 return 0;
0480 }
0481
0482 static int adav80x_set_playback_pcm_format(struct snd_soc_component *component,
0483 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
0484 {
0485 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0486 unsigned int val;
0487
0488 if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J)
0489 return 0;
0490
0491 switch (params_width(params)) {
0492 case 16:
0493 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16;
0494 break;
0495 case 18:
0496 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18;
0497 break;
0498 case 20:
0499 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20;
0500 break;
0501 case 24:
0502 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
0503 break;
0504 default:
0505 return -EINVAL;
0506 }
0507
0508 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
0509 ADAV80X_PLAYBACK_MODE_MASK, val);
0510
0511 return 0;
0512 }
0513
0514 static int adav80x_hw_params(struct snd_pcm_substream *substream,
0515 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0516 {
0517 struct snd_soc_component *component = dai->component;
0518 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0519 unsigned int rate = params_rate(params);
0520
0521 if (rate * 256 != adav80x->sysclk)
0522 return -EINVAL;
0523
0524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0525 adav80x_set_playback_pcm_format(component, dai, params);
0526 adav80x_set_dac_clock(component, rate);
0527 } else {
0528 adav80x_set_capture_pcm_format(component, dai, params);
0529 adav80x_set_adc_clock(component, rate);
0530 }
0531 adav80x->rate = rate;
0532 adav80x_set_deemph(component);
0533
0534 return 0;
0535 }
0536
0537 static int adav80x_set_sysclk(struct snd_soc_component *component,
0538 int clk_id, int source,
0539 unsigned int freq, int dir)
0540 {
0541 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0542 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0543
0544 if (dir == SND_SOC_CLOCK_IN) {
0545 switch (clk_id) {
0546 case ADAV80X_CLK_XIN:
0547 case ADAV80X_CLK_XTAL:
0548 case ADAV80X_CLK_MCLKI:
0549 case ADAV80X_CLK_PLL1:
0550 case ADAV80X_CLK_PLL2:
0551 break;
0552 default:
0553 return -EINVAL;
0554 }
0555
0556 adav80x->sysclk = freq;
0557
0558 if (adav80x->clk_src != clk_id) {
0559 unsigned int iclk_ctrl1, iclk_ctrl2;
0560
0561 adav80x->clk_src = clk_id;
0562 if (clk_id == ADAV80X_CLK_XTAL)
0563 clk_id = ADAV80X_CLK_XIN;
0564
0565 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) |
0566 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) |
0567 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
0568 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
0569
0570 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
0571 iclk_ctrl1);
0572 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
0573 iclk_ctrl2);
0574
0575 snd_soc_dapm_sync(dapm);
0576 }
0577 } else {
0578 unsigned int mask;
0579
0580 switch (clk_id) {
0581 case ADAV80X_CLK_SYSCLK1:
0582 case ADAV80X_CLK_SYSCLK2:
0583 case ADAV80X_CLK_SYSCLK3:
0584 break;
0585 default:
0586 return -EINVAL;
0587 }
0588
0589 clk_id -= ADAV80X_CLK_SYSCLK1;
0590 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
0591
0592 if (freq == 0) {
0593 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
0594 mask, mask);
0595 adav80x->sysclk_pd[clk_id] = true;
0596 } else {
0597 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
0598 mask, 0);
0599 adav80x->sysclk_pd[clk_id] = false;
0600 }
0601
0602 snd_soc_dapm_mutex_lock(dapm);
0603
0604 if (adav80x->sysclk_pd[0])
0605 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1");
0606 else
0607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1");
0608
0609 if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2])
0610 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2");
0611 else
0612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2");
0613
0614 snd_soc_dapm_sync_unlocked(dapm);
0615
0616 snd_soc_dapm_mutex_unlock(dapm);
0617 }
0618
0619 return 0;
0620 }
0621
0622 static int adav80x_set_pll(struct snd_soc_component *component, int pll_id,
0623 int source, unsigned int freq_in, unsigned int freq_out)
0624 {
0625 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0626 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0627 unsigned int pll_ctrl1 = 0;
0628 unsigned int pll_ctrl2 = 0;
0629 unsigned int pll_src;
0630
0631 switch (source) {
0632 case ADAV80X_PLL_SRC_XTAL:
0633 case ADAV80X_PLL_SRC_XIN:
0634 case ADAV80X_PLL_SRC_MCLKI:
0635 break;
0636 default:
0637 return -EINVAL;
0638 }
0639
0640 if (!freq_out)
0641 return 0;
0642
0643 switch (freq_in) {
0644 case 27000000:
0645 break;
0646 case 54000000:
0647 if (source == ADAV80X_PLL_SRC_XIN) {
0648 pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV;
0649 break;
0650 }
0651 fallthrough;
0652 default:
0653 return -EINVAL;
0654 }
0655
0656 if (freq_out > 12288000) {
0657 pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id);
0658 freq_out /= 2;
0659 }
0660
0661
0662 switch (freq_out) {
0663 case 8192000:
0664 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id);
0665 break;
0666 case 11289600:
0667 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id);
0668 break;
0669 case 12288000:
0670 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id);
0671 break;
0672 default:
0673 return -EINVAL;
0674 }
0675
0676 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
0677 ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
0678 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
0679 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
0680
0681 if (source != adav80x->pll_src) {
0682 if (source == ADAV80X_PLL_SRC_MCLKI)
0683 pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id);
0684 else
0685 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
0686
0687 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
0688 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
0689
0690 adav80x->pll_src = source;
0691
0692 snd_soc_dapm_sync(dapm);
0693 }
0694
0695 return 0;
0696 }
0697
0698 static int adav80x_set_bias_level(struct snd_soc_component *component,
0699 enum snd_soc_bias_level level)
0700 {
0701 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0702 unsigned int mask = ADAV80X_DAC_CTRL1_PD;
0703
0704 switch (level) {
0705 case SND_SOC_BIAS_ON:
0706 break;
0707 case SND_SOC_BIAS_PREPARE:
0708 break;
0709 case SND_SOC_BIAS_STANDBY:
0710 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
0711 0x00);
0712 break;
0713 case SND_SOC_BIAS_OFF:
0714 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
0715 mask);
0716 break;
0717 }
0718
0719 return 0;
0720 }
0721
0722
0723 static int adav80x_dai_startup(struct snd_pcm_substream *substream,
0724 struct snd_soc_dai *dai)
0725 {
0726 struct snd_soc_component *component = dai->component;
0727 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0728
0729 if (!snd_soc_component_active(component) || !adav80x->rate)
0730 return 0;
0731
0732 return snd_pcm_hw_constraint_single(substream->runtime,
0733 SNDRV_PCM_HW_PARAM_RATE, adav80x->rate);
0734 }
0735
0736 static void adav80x_dai_shutdown(struct snd_pcm_substream *substream,
0737 struct snd_soc_dai *dai)
0738 {
0739 struct snd_soc_component *component = dai->component;
0740 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0741
0742 if (!snd_soc_component_active(component))
0743 adav80x->rate = 0;
0744 }
0745
0746 static const struct snd_soc_dai_ops adav80x_dai_ops = {
0747 .set_fmt = adav80x_set_dai_fmt,
0748 .hw_params = adav80x_hw_params,
0749 .startup = adav80x_dai_startup,
0750 .shutdown = adav80x_dai_shutdown,
0751 };
0752
0753 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
0754 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \
0755 SNDRV_PCM_RATE_96000)
0756
0757 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
0758
0759 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
0760 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
0761
0762 static struct snd_soc_dai_driver adav80x_dais[] = {
0763 {
0764 .name = "adav80x-hifi",
0765 .id = 0,
0766 .playback = {
0767 .stream_name = "HiFi Playback",
0768 .channels_min = 2,
0769 .channels_max = 2,
0770 .rates = ADAV80X_PLAYBACK_RATES,
0771 .formats = ADAV80X_FORMATS,
0772 },
0773 .capture = {
0774 .stream_name = "HiFi Capture",
0775 .channels_min = 2,
0776 .channels_max = 2,
0777 .rates = ADAV80X_CAPTURE_RATES,
0778 .formats = ADAV80X_FORMATS,
0779 },
0780 .ops = &adav80x_dai_ops,
0781 },
0782 {
0783 .name = "adav80x-aux",
0784 .id = 1,
0785 .playback = {
0786 .stream_name = "Aux Playback",
0787 .channels_min = 2,
0788 .channels_max = 2,
0789 .rates = ADAV80X_PLAYBACK_RATES,
0790 .formats = ADAV80X_FORMATS,
0791 },
0792 .capture = {
0793 .stream_name = "Aux Capture",
0794 .channels_min = 2,
0795 .channels_max = 2,
0796 .rates = ADAV80X_CAPTURE_RATES,
0797 .formats = ADAV80X_FORMATS,
0798 },
0799 .ops = &adav80x_dai_ops,
0800 },
0801 };
0802
0803 static int adav80x_probe(struct snd_soc_component *component)
0804 {
0805 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0806 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0807
0808
0809 snd_soc_dapm_force_enable_pin(dapm, "PLL1");
0810 snd_soc_dapm_force_enable_pin(dapm, "PLL2");
0811
0812
0813 regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
0814
0815 regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
0816
0817 return 0;
0818 }
0819
0820 static int adav80x_resume(struct snd_soc_component *component)
0821 {
0822 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
0823
0824 regcache_sync(adav80x->regmap);
0825
0826 return 0;
0827 }
0828
0829 static const struct snd_soc_component_driver adav80x_component_driver = {
0830 .probe = adav80x_probe,
0831 .resume = adav80x_resume,
0832 .set_bias_level = adav80x_set_bias_level,
0833 .set_pll = adav80x_set_pll,
0834 .set_sysclk = adav80x_set_sysclk,
0835 .controls = adav80x_controls,
0836 .num_controls = ARRAY_SIZE(adav80x_controls),
0837 .dapm_widgets = adav80x_dapm_widgets,
0838 .num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets),
0839 .dapm_routes = adav80x_dapm_routes,
0840 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes),
0841 .suspend_bias_off = 1,
0842 .idle_bias_on = 1,
0843 .use_pmdown_time = 1,
0844 .endianness = 1,
0845 };
0846
0847 int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
0848 {
0849 struct adav80x *adav80x;
0850
0851 if (IS_ERR(regmap))
0852 return PTR_ERR(regmap);
0853
0854 adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL);
0855 if (!adav80x)
0856 return -ENOMEM;
0857
0858 dev_set_drvdata(dev, adav80x);
0859 adav80x->regmap = regmap;
0860
0861 return devm_snd_soc_register_component(dev, &adav80x_component_driver,
0862 adav80x_dais, ARRAY_SIZE(adav80x_dais));
0863 }
0864 EXPORT_SYMBOL_GPL(adav80x_bus_probe);
0865
0866 const struct regmap_config adav80x_regmap_config = {
0867 .val_bits = 8,
0868 .pad_bits = 1,
0869 .reg_bits = 7,
0870
0871 .max_register = ADAV80X_PLL_OUTE,
0872
0873 .cache_type = REGCACHE_RBTREE,
0874 .reg_defaults = adav80x_reg_defaults,
0875 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
0876 };
0877 EXPORT_SYMBOL_GPL(adav80x_regmap_config);
0878
0879 MODULE_DESCRIPTION("ASoC ADAV80x driver");
0880 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0881 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>");
0882 MODULE_LICENSE("GPL");
