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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ADAU1977/ADAU1978/ADAU1979 driver
0004  *
0005  * Copyright 2014 Analog Devices Inc.
0006  *  Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/i2c.h>
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/slab.h>
0018 
0019 #include <sound/core.h>
0020 #include <sound/initval.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/tlv.h>
0025 
0026 #include <dt-bindings/sound/adi,adau1977.h>
0027 
0028 #include "adau1977.h"
0029 
0030 #define ADAU1977_REG_POWER      0x00
0031 #define ADAU1977_REG_PLL        0x01
0032 #define ADAU1977_REG_BOOST      0x02
0033 #define ADAU1977_REG_MICBIAS        0x03
0034 #define ADAU1977_REG_BLOCK_POWER_SAI    0x04
0035 #define ADAU1977_REG_SAI_CTRL0      0x05
0036 #define ADAU1977_REG_SAI_CTRL1      0x06
0037 #define ADAU1977_REG_CMAP12     0x07
0038 #define ADAU1977_REG_CMAP34     0x08
0039 #define ADAU1977_REG_SAI_OVERTEMP   0x09
0040 #define ADAU1977_REG_POST_ADC_GAIN(x)   (0x0a + (x))
0041 #define ADAU1977_REG_MISC_CONTROL   0x0e
0042 #define ADAU1977_REG_DIAG_CONTROL   0x10
0043 #define ADAU1977_REG_STATUS(x)      (0x11 + (x))
0044 #define ADAU1977_REG_DIAG_IRQ1      0x15
0045 #define ADAU1977_REG_DIAG_IRQ2      0x16
0046 #define ADAU1977_REG_ADJUST1        0x17
0047 #define ADAU1977_REG_ADJUST2        0x18
0048 #define ADAU1977_REG_ADC_CLIP       0x19
0049 #define ADAU1977_REG_DC_HPF_CAL     0x1a
0050 
0051 #define ADAU1977_POWER_RESET            BIT(7)
0052 #define ADAU1977_POWER_PWUP         BIT(0)
0053 
0054 #define ADAU1977_PLL_CLK_S          BIT(4)
0055 #define ADAU1977_PLL_MCS_MASK           0x7
0056 
0057 #define ADAU1977_MICBIAS_MB_VOLTS_MASK      0xf0
0058 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET    4
0059 
0060 #define ADAU1977_BLOCK_POWER_SAI_LR_POL     BIT(7)
0061 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE  BIT(6)
0062 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN     BIT(5)
0063 
0064 #define ADAU1977_SAI_CTRL0_FMT_MASK     (0x3 << 6)
0065 #define ADAU1977_SAI_CTRL0_FMT_I2S      (0x0 << 6)
0066 #define ADAU1977_SAI_CTRL0_FMT_LJ       (0x1 << 6)
0067 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT     (0x2 << 6)
0068 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT     (0x3 << 6)
0069 
0070 #define ADAU1977_SAI_CTRL0_SAI_MASK     (0x7 << 3)
0071 #define ADAU1977_SAI_CTRL0_SAI_I2S      (0x0 << 3)
0072 #define ADAU1977_SAI_CTRL0_SAI_TDM_2        (0x1 << 3)
0073 #define ADAU1977_SAI_CTRL0_SAI_TDM_4        (0x2 << 3)
0074 #define ADAU1977_SAI_CTRL0_SAI_TDM_8        (0x3 << 3)
0075 #define ADAU1977_SAI_CTRL0_SAI_TDM_16       (0x4 << 3)
0076 
0077 #define ADAU1977_SAI_CTRL0_FS_MASK      (0x7)
0078 #define ADAU1977_SAI_CTRL0_FS_8000_12000    (0x0)
0079 #define ADAU1977_SAI_CTRL0_FS_16000_24000   (0x1)
0080 #define ADAU1977_SAI_CTRL0_FS_32000_48000   (0x2)
0081 #define ADAU1977_SAI_CTRL0_FS_64000_96000   (0x3)
0082 #define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
0083 
0084 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK  (0x3 << 5)
0085 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32    (0x0 << 5)
0086 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24    (0x1 << 5)
0087 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16    (0x2 << 5)
0088 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK  (0x1 << 4)
0089 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
0090 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
0091 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE      BIT(3)
0092 #define ADAU1977_SAI_CTRL1_MSB          BIT(2)
0093 #define ADAU1977_SAI_CTRL1_BCLKRATE_16      (0x1 << 1)
0094 #define ADAU1977_SAI_CTRL1_BCLKRATE_32      (0x0 << 1)
0095 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK    (0x1 << 1)
0096 #define ADAU1977_SAI_CTRL1_MASTER       BIT(0)
0097 
0098 #define ADAU1977_SAI_OVERTEMP_DRV_C(x)      BIT(4 + (x))
0099 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ       BIT(3)
0100 
0101 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
0102 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH  (0x2 << 6)
0103 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH  (0x1 << 6)
0104 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH  (0x0 << 6)
0105 #define ADAU1977_MISC_CONTROL_MMUTE     BIT(4)
0106 #define ADAU1977_MISC_CONTROL_DC_CAL        BIT(0)
0107 
0108 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET    4
0109 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
0110 
0111 struct adau1977 {
0112     struct regmap *regmap;
0113     bool right_j;
0114     unsigned int sysclk;
0115     enum adau1977_sysclk_src sysclk_src;
0116     struct gpio_desc *reset_gpio;
0117     enum adau1977_type type;
0118 
0119     struct regulator *avdd_reg;
0120     struct regulator *dvdd_reg;
0121 
0122     struct snd_pcm_hw_constraint_list constraints;
0123 
0124     struct device *dev;
0125     void (*switch_mode)(struct device *dev);
0126 
0127     unsigned int max_clock_provider_fs;
0128     unsigned int slot_width;
0129     bool enabled;
0130     bool clock_provider;
0131 };
0132 
0133 static const struct reg_default adau1977_reg_defaults[] = {
0134     { 0x00, 0x00 },
0135     { 0x01, 0x41 },
0136     { 0x02, 0x4a },
0137     { 0x03, 0x7d },
0138     { 0x04, 0x3d },
0139     { 0x05, 0x02 },
0140     { 0x06, 0x00 },
0141     { 0x07, 0x10 },
0142     { 0x08, 0x32 },
0143     { 0x09, 0xf0 },
0144     { 0x0a, 0xa0 },
0145     { 0x0b, 0xa0 },
0146     { 0x0c, 0xa0 },
0147     { 0x0d, 0xa0 },
0148     { 0x0e, 0x02 },
0149     { 0x10, 0x0f },
0150     { 0x15, 0x20 },
0151     { 0x16, 0x00 },
0152     { 0x17, 0x00 },
0153     { 0x18, 0x00 },
0154     { 0x1a, 0x00 },
0155 };
0156 
0157 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
0158 
0159 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
0160     SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
0161         3, 0, NULL, 0)
0162 };
0163 
0164 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
0165     SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
0166         4, 0, NULL, 0),
0167 
0168     SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
0169     SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
0170     SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
0171     SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
0172 
0173     SND_SOC_DAPM_INPUT("AIN1"),
0174     SND_SOC_DAPM_INPUT("AIN2"),
0175     SND_SOC_DAPM_INPUT("AIN3"),
0176     SND_SOC_DAPM_INPUT("AIN4"),
0177 
0178     SND_SOC_DAPM_OUTPUT("VREF"),
0179 };
0180 
0181 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
0182     { "ADC1", NULL, "AIN1" },
0183     { "ADC2", NULL, "AIN2" },
0184     { "ADC3", NULL, "AIN3" },
0185     { "ADC4", NULL, "AIN4" },
0186 
0187     { "ADC1", NULL, "Vref" },
0188     { "ADC2", NULL, "Vref" },
0189     { "ADC3", NULL, "Vref" },
0190     { "ADC4", NULL, "Vref" },
0191 
0192     { "VREF", NULL, "Vref" },
0193 };
0194 
0195 #define ADAU1977_VOLUME(x) \
0196     SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
0197         ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
0198         0, 255, 1, adau1977_adc_gain)
0199 
0200 #define ADAU1977_HPF_SWITCH(x) \
0201     SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
0202         ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
0203 
0204 #define ADAU1977_DC_SUB_SWITCH(x) \
0205     SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
0206         ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
0207 
0208 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
0209     ADAU1977_VOLUME(1),
0210     ADAU1977_VOLUME(2),
0211     ADAU1977_VOLUME(3),
0212     ADAU1977_VOLUME(4),
0213 
0214     ADAU1977_HPF_SWITCH(1),
0215     ADAU1977_HPF_SWITCH(2),
0216     ADAU1977_HPF_SWITCH(3),
0217     ADAU1977_HPF_SWITCH(4),
0218 
0219     ADAU1977_DC_SUB_SWITCH(1),
0220     ADAU1977_DC_SUB_SWITCH(2),
0221     ADAU1977_DC_SUB_SWITCH(3),
0222     ADAU1977_DC_SUB_SWITCH(4),
0223 };
0224 
0225 static int adau1977_reset(struct adau1977 *adau1977)
0226 {
0227     int ret;
0228 
0229     /*
0230      * The reset bit is obviously volatile, but we need to be able to cache
0231      * the other bits in the register, so we can't just mark the whole
0232      * register as volatile. Since this is the only place where we'll ever
0233      * touch the reset bit just bypass the cache for this operation.
0234      */
0235     regcache_cache_bypass(adau1977->regmap, true);
0236     ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
0237             ADAU1977_POWER_RESET);
0238     regcache_cache_bypass(adau1977->regmap, false);
0239 
0240     return ret;
0241 }
0242 
0243 /*
0244  * Returns the appropriate setting for ths FS field in the CTRL0 register
0245  * depending on the rate.
0246  */
0247 static int adau1977_lookup_fs(unsigned int rate)
0248 {
0249     if (rate >= 8000 && rate <= 12000)
0250         return ADAU1977_SAI_CTRL0_FS_8000_12000;
0251     else if (rate >= 16000 && rate <= 24000)
0252         return ADAU1977_SAI_CTRL0_FS_16000_24000;
0253     else if (rate >= 32000 && rate <= 48000)
0254         return ADAU1977_SAI_CTRL0_FS_32000_48000;
0255     else if (rate >= 64000 && rate <= 96000)
0256         return ADAU1977_SAI_CTRL0_FS_64000_96000;
0257     else if (rate >= 128000 && rate <= 192000)
0258         return ADAU1977_SAI_CTRL0_FS_128000_192000;
0259     else
0260         return -EINVAL;
0261 }
0262 
0263 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
0264     unsigned int fs)
0265 {
0266     unsigned int mcs;
0267 
0268     /*
0269      * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
0270      * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
0271      * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
0272      */
0273 
0274     rate *= 512 >> fs;
0275 
0276     if (adau1977->sysclk % rate != 0)
0277         return -EINVAL;
0278 
0279     mcs = adau1977->sysclk / rate;
0280 
0281     /* The factors configured by MCS are 1, 2, 3, 4, 6 */
0282     if (mcs < 1 || mcs > 6 || mcs == 5)
0283         return -EINVAL;
0284 
0285     mcs = mcs - 1;
0286     if (mcs == 5)
0287         mcs = 4;
0288 
0289     return mcs;
0290 }
0291 
0292 static int adau1977_hw_params(struct snd_pcm_substream *substream,
0293     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0294 {
0295     struct snd_soc_component *component = dai->component;
0296     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
0297     unsigned int rate = params_rate(params);
0298     unsigned int slot_width;
0299     unsigned int ctrl0, ctrl0_mask;
0300     unsigned int ctrl1;
0301     int mcs, fs;
0302     int ret;
0303 
0304     fs = adau1977_lookup_fs(rate);
0305     if (fs < 0)
0306         return fs;
0307 
0308     if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
0309         mcs = adau1977_lookup_mcs(adau1977, rate, fs);
0310         if (mcs < 0)
0311             return mcs;
0312     } else {
0313         mcs = 0;
0314     }
0315 
0316     ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
0317     ctrl0 = fs;
0318 
0319     if (adau1977->right_j) {
0320         switch (params_width(params)) {
0321         case 16:
0322             ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
0323             break;
0324         case 24:
0325             ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
0326             break;
0327         default:
0328             return -EINVAL;
0329         }
0330         ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
0331     }
0332 
0333     if (adau1977->clock_provider) {
0334         switch (params_width(params)) {
0335         case 16:
0336             ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
0337             slot_width = 16;
0338             break;
0339         case 24:
0340         case 32:
0341             ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
0342             slot_width = 32;
0343             break;
0344         default:
0345             return -EINVAL;
0346         }
0347 
0348         /* In TDM mode there is a fixed slot width */
0349         if (adau1977->slot_width)
0350             slot_width = adau1977->slot_width;
0351 
0352         if (slot_width == 16)
0353             ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
0354         else
0355             ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
0356 
0357         ret = regmap_update_bits(adau1977->regmap,
0358             ADAU1977_REG_SAI_CTRL1,
0359             ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
0360             ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
0361             ctrl1);
0362         if (ret < 0)
0363             return ret;
0364     }
0365 
0366     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
0367                 ctrl0_mask, ctrl0);
0368     if (ret < 0)
0369         return ret;
0370 
0371     return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
0372                 ADAU1977_PLL_MCS_MASK, mcs);
0373 }
0374 
0375 static int adau1977_power_disable(struct adau1977 *adau1977)
0376 {
0377     int ret = 0;
0378 
0379     if (!adau1977->enabled)
0380         return 0;
0381 
0382     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
0383         ADAU1977_POWER_PWUP, 0);
0384     if (ret)
0385         return ret;
0386 
0387     regcache_mark_dirty(adau1977->regmap);
0388 
0389     gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
0390 
0391     regcache_cache_only(adau1977->regmap, true);
0392 
0393     regulator_disable(adau1977->avdd_reg);
0394     if (adau1977->dvdd_reg)
0395         regulator_disable(adau1977->dvdd_reg);
0396 
0397     adau1977->enabled = false;
0398 
0399     return 0;
0400 }
0401 
0402 static int adau1977_power_enable(struct adau1977 *adau1977)
0403 {
0404     unsigned int val;
0405     int ret = 0;
0406 
0407     if (adau1977->enabled)
0408         return 0;
0409 
0410     ret = regulator_enable(adau1977->avdd_reg);
0411     if (ret)
0412         return ret;
0413 
0414     if (adau1977->dvdd_reg) {
0415         ret = regulator_enable(adau1977->dvdd_reg);
0416         if (ret)
0417             goto err_disable_avdd;
0418     }
0419 
0420     gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
0421 
0422     regcache_cache_only(adau1977->regmap, false);
0423 
0424     if (adau1977->switch_mode)
0425         adau1977->switch_mode(adau1977->dev);
0426 
0427     ret = adau1977_reset(adau1977);
0428     if (ret)
0429         goto err_disable_dvdd;
0430 
0431     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
0432         ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
0433     if (ret)
0434         goto err_disable_dvdd;
0435 
0436     ret = regcache_sync(adau1977->regmap);
0437     if (ret)
0438         goto err_disable_dvdd;
0439 
0440     /*
0441      * The PLL register is not affected by the software reset. It is
0442      * possible that the value of the register was changed to the
0443      * default value while we were in cache only mode. In this case
0444      * regcache_sync will skip over it and we have to manually sync
0445      * it.
0446      */
0447     ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
0448     if (ret)
0449         goto err_disable_dvdd;
0450 
0451     if (val == 0x41) {
0452         regcache_cache_bypass(adau1977->regmap, true);
0453         ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
0454             0x41);
0455         if (ret)
0456             goto err_disable_dvdd;
0457         regcache_cache_bypass(adau1977->regmap, false);
0458     }
0459 
0460     adau1977->enabled = true;
0461 
0462     return ret;
0463 
0464 err_disable_dvdd:
0465     if (adau1977->dvdd_reg)
0466         regulator_disable(adau1977->dvdd_reg);
0467 err_disable_avdd:
0468         regulator_disable(adau1977->avdd_reg);
0469     return ret;
0470 }
0471 
0472 static int adau1977_set_bias_level(struct snd_soc_component *component,
0473     enum snd_soc_bias_level level)
0474 {
0475     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
0476     int ret = 0;
0477 
0478     switch (level) {
0479     case SND_SOC_BIAS_ON:
0480         break;
0481     case SND_SOC_BIAS_PREPARE:
0482         break;
0483     case SND_SOC_BIAS_STANDBY:
0484         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
0485             ret = adau1977_power_enable(adau1977);
0486         break;
0487     case SND_SOC_BIAS_OFF:
0488         ret = adau1977_power_disable(adau1977);
0489         break;
0490     }
0491 
0492     return ret;
0493 }
0494 
0495 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0496     unsigned int rx_mask, int slots, int width)
0497 {
0498     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
0499     unsigned int ctrl0, ctrl1, drv;
0500     unsigned int slot[4];
0501     unsigned int i;
0502     int ret;
0503 
0504     if (slots == 0) {
0505         /* 0 = No fixed slot width */
0506         adau1977->slot_width = 0;
0507         adau1977->max_clock_provider_fs = 192000;
0508         return regmap_update_bits(adau1977->regmap,
0509             ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
0510             ADAU1977_SAI_CTRL0_SAI_I2S);
0511     }
0512 
0513     if (rx_mask == 0 || tx_mask != 0)
0514         return -EINVAL;
0515 
0516     drv = 0;
0517     for (i = 0; i < 4; i++) {
0518         slot[i] = __ffs(rx_mask);
0519         drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
0520         rx_mask &= ~(1 << slot[i]);
0521         if (slot[i] >= slots)
0522             return -EINVAL;
0523         if (rx_mask == 0)
0524             break;
0525     }
0526 
0527     if (rx_mask != 0)
0528         return -EINVAL;
0529 
0530     switch (width) {
0531     case 16:
0532         ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
0533         break;
0534     case 24:
0535         /* We can only generate 16 bit or 32 bit wide slots */
0536         if (adau1977->clock_provider)
0537             return -EINVAL;
0538         ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
0539         break;
0540     case 32:
0541         ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
0542         break;
0543     default:
0544         return -EINVAL;
0545     }
0546 
0547     switch (slots) {
0548     case 2:
0549         ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
0550         break;
0551     case 4:
0552         ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
0553         break;
0554     case 8:
0555         ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
0556         break;
0557     case 16:
0558         ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
0559         break;
0560     default:
0561         return -EINVAL;
0562     }
0563 
0564     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
0565         ADAU1977_SAI_OVERTEMP_DRV_C(0) |
0566         ADAU1977_SAI_OVERTEMP_DRV_C(1) |
0567         ADAU1977_SAI_OVERTEMP_DRV_C(2) |
0568         ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
0569     if (ret)
0570         return ret;
0571 
0572     ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
0573         (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
0574         (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
0575     if (ret)
0576         return ret;
0577 
0578     ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
0579         (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
0580         (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
0581     if (ret)
0582         return ret;
0583 
0584     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
0585         ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
0586     if (ret)
0587         return ret;
0588 
0589     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
0590         ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
0591     if (ret)
0592         return ret;
0593 
0594     adau1977->slot_width = width;
0595 
0596     /* In clock provider mode the maximum bitclock is 24.576 MHz */
0597     adau1977->max_clock_provider_fs = min(192000, 24576000 / width / slots);
0598 
0599     return 0;
0600 }
0601 
0602 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
0603 {
0604     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
0605     unsigned int val;
0606 
0607     if (mute)
0608         val = ADAU1977_MISC_CONTROL_MMUTE;
0609     else
0610         val = 0;
0611 
0612     return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
0613             ADAU1977_MISC_CONTROL_MMUTE, val);
0614 }
0615 
0616 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0617 {
0618     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
0619     unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
0620     bool invert_lrclk;
0621     int ret;
0622 
0623     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0624     case SND_SOC_DAIFMT_CBC_CFC:
0625         adau1977->clock_provider = false;
0626         break;
0627     case SND_SOC_DAIFMT_CBP_CFP:
0628         ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
0629         adau1977->clock_provider = true;
0630         break;
0631     default:
0632         return -EINVAL;
0633     }
0634 
0635     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0636     case SND_SOC_DAIFMT_NB_NF:
0637         invert_lrclk = false;
0638         break;
0639     case SND_SOC_DAIFMT_IB_NF:
0640         block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
0641         invert_lrclk = false;
0642         break;
0643     case SND_SOC_DAIFMT_NB_IF:
0644         invert_lrclk = true;
0645         break;
0646     case SND_SOC_DAIFMT_IB_IF:
0647         block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
0648         invert_lrclk = true;
0649         break;
0650     default:
0651         return -EINVAL;
0652     }
0653 
0654     adau1977->right_j = false;
0655     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0656     case SND_SOC_DAIFMT_I2S:
0657         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
0658         break;
0659     case SND_SOC_DAIFMT_LEFT_J:
0660         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
0661         invert_lrclk = !invert_lrclk;
0662         break;
0663     case SND_SOC_DAIFMT_RIGHT_J:
0664         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
0665         adau1977->right_j = true;
0666         invert_lrclk = !invert_lrclk;
0667         break;
0668     case SND_SOC_DAIFMT_DSP_A:
0669         ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
0670         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
0671         invert_lrclk = false;
0672         break;
0673     case SND_SOC_DAIFMT_DSP_B:
0674         ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
0675         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
0676         invert_lrclk = false;
0677         break;
0678     default:
0679         return -EINVAL;
0680     }
0681 
0682     if (invert_lrclk)
0683         block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
0684 
0685     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
0686         ADAU1977_BLOCK_POWER_SAI_LR_POL |
0687         ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
0688     if (ret)
0689         return ret;
0690 
0691     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
0692         ADAU1977_SAI_CTRL0_FMT_MASK,
0693         ctrl0);
0694     if (ret)
0695         return ret;
0696 
0697     return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
0698         ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
0699         ctrl1);
0700 }
0701 
0702 static int adau1977_startup(struct snd_pcm_substream *substream,
0703     struct snd_soc_dai *dai)
0704 {
0705     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
0706     u64 formats = 0;
0707 
0708     if (adau1977->slot_width == 16)
0709         formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
0710     else if (adau1977->right_j || adau1977->slot_width == 24)
0711         formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
0712             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
0713 
0714     snd_pcm_hw_constraint_list(substream->runtime, 0,
0715         SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
0716 
0717     if (adau1977->clock_provider)
0718         snd_pcm_hw_constraint_minmax(substream->runtime,
0719             SNDRV_PCM_HW_PARAM_RATE, 8000,
0720                          adau1977->max_clock_provider_fs);
0721 
0722     if (formats != 0)
0723         snd_pcm_hw_constraint_mask64(substream->runtime,
0724             SNDRV_PCM_HW_PARAM_FORMAT, formats);
0725 
0726     return 0;
0727 }
0728 
0729 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
0730 {
0731     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
0732     unsigned int val;
0733 
0734     if (tristate)
0735         val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
0736     else
0737         val = 0;
0738 
0739     return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
0740         ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
0741 }
0742 
0743 static const struct snd_soc_dai_ops adau1977_dai_ops = {
0744     .startup    = adau1977_startup,
0745     .hw_params  = adau1977_hw_params,
0746     .mute_stream    = adau1977_mute,
0747     .set_fmt    = adau1977_set_dai_fmt,
0748     .set_tdm_slot   = adau1977_set_tdm_slot,
0749     .set_tristate   = adau1977_set_tristate,
0750 };
0751 
0752 static struct snd_soc_dai_driver adau1977_dai = {
0753     .name = "adau1977-hifi",
0754     .capture = {
0755         .stream_name = "Capture",
0756         .channels_min = 1,
0757         .channels_max = 4,
0758         .rates = SNDRV_PCM_RATE_KNOT,
0759         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
0760             SNDRV_PCM_FMTBIT_S32_LE,
0761         .sig_bits = 24,
0762     },
0763     .ops = &adau1977_dai_ops,
0764 };
0765 
0766 static const unsigned int adau1977_rates[] = {
0767     8000, 16000, 32000, 64000, 128000,
0768     11025, 22050, 44100, 88200, 172400,
0769     12000, 24000, 48000, 96000, 192000,
0770 };
0771 
0772 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
0773 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
0774 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
0775 /* All rates >= 32000 */
0776 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
0777 
0778 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
0779 {
0780     unsigned int mcs;
0781 
0782     if (mclk % (base_freq * 128) != 0)
0783         return false;
0784 
0785     mcs = mclk / (128 * base_freq);
0786     if (mcs < 1 || mcs > 6 || mcs == 5)
0787         return false;
0788 
0789     return true;
0790 }
0791 
0792 static int adau1977_set_sysclk(struct snd_soc_component *component,
0793     int clk_id, int source, unsigned int freq, int dir)
0794 {
0795     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
0796     unsigned int mask = 0;
0797     unsigned int clk_src;
0798     unsigned int ret;
0799 
0800     if (dir != SND_SOC_CLOCK_IN)
0801         return -EINVAL;
0802 
0803     if (clk_id != ADAU1977_SYSCLK)
0804         return -EINVAL;
0805 
0806     switch (source) {
0807     case ADAU1977_SYSCLK_SRC_MCLK:
0808         clk_src = 0;
0809         break;
0810     case ADAU1977_SYSCLK_SRC_LRCLK:
0811         clk_src = ADAU1977_PLL_CLK_S;
0812         break;
0813     default:
0814         return -EINVAL;
0815     }
0816 
0817     if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
0818         if (freq < 4000000 || freq > 36864000)
0819             return -EINVAL;
0820 
0821         if (adau1977_check_sysclk(freq, 32000))
0822             mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
0823         if (adau1977_check_sysclk(freq, 44100))
0824             mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
0825         if (adau1977_check_sysclk(freq, 48000))
0826             mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
0827 
0828         if (mask == 0)
0829             return -EINVAL;
0830     } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
0831         mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
0832     }
0833 
0834     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
0835         ADAU1977_PLL_CLK_S, clk_src);
0836     if (ret)
0837         return ret;
0838 
0839     adau1977->constraints.mask = mask;
0840     adau1977->sysclk_src = source;
0841     adau1977->sysclk = freq;
0842 
0843     return 0;
0844 }
0845 
0846 static int adau1977_component_probe(struct snd_soc_component *component)
0847 {
0848     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0849     struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
0850     int ret;
0851 
0852     switch (adau1977->type) {
0853     case ADAU1977:
0854         ret = snd_soc_dapm_new_controls(dapm,
0855             adau1977_micbias_dapm_widgets,
0856             ARRAY_SIZE(adau1977_micbias_dapm_widgets));
0857         if (ret < 0)
0858             return ret;
0859         break;
0860     default:
0861         break;
0862     }
0863 
0864     return 0;
0865 }
0866 
0867 static const struct snd_soc_component_driver adau1977_component_driver = {
0868     .probe          = adau1977_component_probe,
0869     .set_bias_level     = adau1977_set_bias_level,
0870     .set_sysclk     = adau1977_set_sysclk,
0871     .controls       = adau1977_snd_controls,
0872     .num_controls       = ARRAY_SIZE(adau1977_snd_controls),
0873     .dapm_widgets       = adau1977_dapm_widgets,
0874     .num_dapm_widgets   = ARRAY_SIZE(adau1977_dapm_widgets),
0875     .dapm_routes        = adau1977_dapm_routes,
0876     .num_dapm_routes    = ARRAY_SIZE(adau1977_dapm_routes),
0877     .use_pmdown_time    = 1,
0878     .endianness     = 1,
0879 };
0880 
0881 static int adau1977_setup_micbias(struct adau1977 *adau1977)
0882 {
0883     unsigned int micbias;
0884 
0885     if (device_property_read_u32(adau1977->dev, "adi,micbias", &micbias))
0886         micbias = ADAU1977_MICBIAS_8V5;
0887 
0888     if (micbias > ADAU1977_MICBIAS_9V0) {
0889         dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
0890         return -EINVAL;
0891     }
0892 
0893     return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
0894         ADAU1977_MICBIAS_MB_VOLTS_MASK,
0895         micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
0896 }
0897 
0898 int adau1977_probe(struct device *dev, struct regmap *regmap,
0899     enum adau1977_type type, void (*switch_mode)(struct device *dev))
0900 {
0901     unsigned int power_off_mask;
0902     struct adau1977 *adau1977;
0903     int ret;
0904 
0905     if (IS_ERR(regmap))
0906         return PTR_ERR(regmap);
0907 
0908     adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
0909     if (adau1977 == NULL)
0910         return -ENOMEM;
0911 
0912     adau1977->dev = dev;
0913     adau1977->type = type;
0914     adau1977->regmap = regmap;
0915     adau1977->switch_mode = switch_mode;
0916     adau1977->max_clock_provider_fs = 192000;
0917 
0918     adau1977->constraints.list = adau1977_rates;
0919     adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
0920 
0921     adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
0922     if (IS_ERR(adau1977->avdd_reg))
0923         return PTR_ERR(adau1977->avdd_reg);
0924 
0925     adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
0926     if (IS_ERR(adau1977->dvdd_reg)) {
0927         if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
0928             return PTR_ERR(adau1977->dvdd_reg);
0929         adau1977->dvdd_reg = NULL;
0930     }
0931 
0932     adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
0933                                GPIOD_OUT_LOW);
0934     if (IS_ERR(adau1977->reset_gpio))
0935         return PTR_ERR(adau1977->reset_gpio);
0936 
0937     dev_set_drvdata(dev, adau1977);
0938 
0939     if (adau1977->reset_gpio)
0940         ndelay(100);
0941 
0942     ret = adau1977_power_enable(adau1977);
0943     if (ret)
0944         return ret;
0945 
0946     if (type == ADAU1977) {
0947         ret = adau1977_setup_micbias(adau1977);
0948         if (ret)
0949             goto err_poweroff;
0950     }
0951 
0952     if (adau1977->dvdd_reg)
0953         power_off_mask = ~0;
0954     else
0955         power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
0956 
0957     ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
0958                 power_off_mask, 0x00);
0959     if (ret)
0960         goto err_poweroff;
0961 
0962     ret = adau1977_power_disable(adau1977);
0963     if (ret)
0964         return ret;
0965 
0966     return devm_snd_soc_register_component(dev, &adau1977_component_driver,
0967             &adau1977_dai, 1);
0968 
0969 err_poweroff:
0970     adau1977_power_disable(adau1977);
0971     return ret;
0972 
0973 }
0974 EXPORT_SYMBOL_GPL(adau1977_probe);
0975 
0976 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
0977 {
0978     switch (reg) {
0979     case ADAU1977_REG_STATUS(0):
0980     case ADAU1977_REG_STATUS(1):
0981     case ADAU1977_REG_STATUS(2):
0982     case ADAU1977_REG_STATUS(3):
0983     case ADAU1977_REG_ADC_CLIP:
0984         return true;
0985     }
0986 
0987     return false;
0988 }
0989 
0990 const struct regmap_config adau1977_regmap_config = {
0991     .max_register = ADAU1977_REG_DC_HPF_CAL,
0992     .volatile_reg = adau1977_register_volatile,
0993 
0994     .cache_type = REGCACHE_RBTREE,
0995     .reg_defaults = adau1977_reg_defaults,
0996     .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
0997 };
0998 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
0999 
1000 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1001 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1002 MODULE_LICENSE("GPL");
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