soc/codecs/adau17x1.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ADAU17X1_H__
0003 #define __ADAU17X1_H__
0004
0005 #include <linux/regmap.h>
0006 #include <linux/platform_data/adau17x1.h>
0007
0008 #include "sigmadsp.h"
0009
0010 enum adau17x1_type {
0011     ADAU1361,
0012     ADAU1761,
0013     ADAU1761_AS_1361,
0014     ADAU1381,
0015     ADAU1781,
0016 };
0017
0018 enum adau17x1_pll {
0019     ADAU17X1_PLL,
0020 };
0021
0022 enum adau17x1_pll_src {
0023     ADAU17X1_PLL_SRC_MCLK,
0024 };
0025
0026 enum adau17x1_clk_src {
0027     /* Automatically configure PLL based on the sample rate */
0028     ADAU17X1_CLK_SRC_PLL_AUTO,
0029     ADAU17X1_CLK_SRC_MCLK,
0030     ADAU17X1_CLK_SRC_PLL,
0031 };
0032
0033 struct clk;
0034
0035 struct adau {
0036     unsigned int sysclk;
0037     unsigned int pll_freq;
0038     struct clk *mclk;
0039
0040     enum adau17x1_clk_src clk_src;
0041     enum adau17x1_type type;
0042     void (*switch_mode)(struct device *dev);
0043
0044     unsigned int dai_fmt;
0045
0046     uint8_t pll_regs[6];
0047
0048     bool master;
0049
0050     unsigned int tdm_slot[2];
0051     bool dsp_bypass[2];
0052
0053     struct regmap *regmap;
0054     struct sigmadsp *sigmadsp;
0055 };
0056
0057 int adau17x1_add_widgets(struct snd_soc_component *component);
0058 int adau17x1_add_routes(struct snd_soc_component *component);
0059 int adau17x1_probe(struct device *dev, struct regmap *regmap,
0060     enum adau17x1_type type, void (*switch_mode)(struct device *dev),
0061     const char *firmware_name);
0062 void adau17x1_remove(struct device *dev);
0063 int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
0064     enum adau17x1_micbias_voltage micbias);
0065 bool adau17x1_readable_register(struct device *dev, unsigned int reg);
0066 bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
0067 bool adau17x1_precious_register(struct device *dev, unsigned int reg);
0068 int adau17x1_resume(struct snd_soc_component *component);
0069
0070 extern const struct snd_soc_dai_ops adau17x1_dai_ops;
0071
0072 #define ADAU17X1_CLOCK_CONTROL          0x4000
0073 #define ADAU17X1_PLL_CONTROL            0x4002
0074 #define ADAU17X1_REC_POWER_MGMT         0x4009
0075 #define ADAU17X1_MICBIAS            0x4010
0076 #define ADAU17X1_SERIAL_PORT0           0x4015
0077 #define ADAU17X1_SERIAL_PORT1           0x4016
0078 #define ADAU17X1_CONVERTER0         0x4017
0079 #define ADAU17X1_CONVERTER1         0x4018
0080 #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL     0x401a
0081 #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL    0x401b
0082 #define ADAU17X1_ADC_CONTROL            0x4019
0083 #define ADAU17X1_PLAY_POWER_MGMT        0x4029
0084 #define ADAU17X1_DAC_CONTROL0           0x402a
0085 #define ADAU17X1_DAC_CONTROL1           0x402b
0086 #define ADAU17X1_DAC_CONTROL2           0x402c
0087 #define ADAU17X1_SERIAL_PORT_PAD        0x402d
0088 #define ADAU17X1_CONTROL_PORT_PAD0      0x402f
0089 #define ADAU17X1_CONTROL_PORT_PAD1      0x4030
0090 #define ADAU17X1_DSP_SAMPLING_RATE      0x40eb
0091 #define ADAU17X1_SERIAL_INPUT_ROUTE     0x40f2
0092 #define ADAU17X1_SERIAL_OUTPUT_ROUTE        0x40f3
0093 #define ADAU17X1_DSP_ENABLE         0x40f5
0094 #define ADAU17X1_DSP_RUN            0x40f6
0095 #define ADAU17X1_SERIAL_SAMPLING_RATE       0x40f8
0096
0097 #define ADAU17X1_SERIAL_PORT0_BCLK_POL      BIT(4)
0098 #define ADAU17X1_SERIAL_PORT0_LRCLK_POL     BIT(3)
0099 #define ADAU17X1_SERIAL_PORT0_MASTER        BIT(0)
0100
0101 #define ADAU17X1_SERIAL_PORT1_DELAY1        0x00
0102 #define ADAU17X1_SERIAL_PORT1_DELAY0        0x01
0103 #define ADAU17X1_SERIAL_PORT1_DELAY8        0x02
0104 #define ADAU17X1_SERIAL_PORT1_DELAY16       0x03
0105 #define ADAU17X1_SERIAL_PORT1_DELAY_MASK    0x03
0106
0107 #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK  0x6
0108 #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL  BIT(3)
0109 #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN    BIT(0)
0110
0111 #define ADAU17X1_SERIAL_PORT1_BCLK64        (0x0 << 5)
0112 #define ADAU17X1_SERIAL_PORT1_BCLK32        (0x1 << 5)
0113 #define ADAU17X1_SERIAL_PORT1_BCLK48        (0x2 << 5)
0114 #define ADAU17X1_SERIAL_PORT1_BCLK128       (0x3 << 5)
0115 #define ADAU17X1_SERIAL_PORT1_BCLK256       (0x4 << 5)
0116 #define ADAU17X1_SERIAL_PORT1_BCLK_MASK     (0x7 << 5)
0117
0118 #define ADAU17X1_SERIAL_PORT0_STEREO        (0x0 << 1)
0119 #define ADAU17X1_SERIAL_PORT0_TDM4      (0x1 << 1)
0120 #define ADAU17X1_SERIAL_PORT0_TDM8      (0x2 << 1)
0121 #define ADAU17X1_SERIAL_PORT0_TDM_MASK      (0x3 << 1)
0122 #define ADAU17X1_SERIAL_PORT0_PULSE_MODE    BIT(5)
0123
0124 #define ADAU17X1_CONVERTER0_DAC_PAIR(x)     (((x) - 1) << 5)
0125 #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK   (0x3 << 5)
0126 #define ADAU17X1_CONVERTER1_ADC_PAIR(x)     ((x) - 1)
0127 #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK   0x3
0128
0129 #define ADAU17X1_CONVERTER0_CONVSR_MASK     0x7
0130
0131 #define ADAU17X1_CONVERTER0_ADOSR       BIT(3)
0132
0133
0134 #endif