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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Common code for ADAU1X61 and ADAU1X81 codecs
0004  *
0005  * Copyright 2011-2014 Analog Devices Inc.
0006  * Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/slab.h>
0014 #include <sound/core.h>
0015 #include <sound/pcm.h>
0016 #include <sound/pcm_params.h>
0017 #include <sound/soc.h>
0018 #include <sound/tlv.h>
0019 #include <linux/gcd.h>
0020 #include <linux/i2c.h>
0021 #include <linux/spi/spi.h>
0022 #include <linux/regmap.h>
0023 #include <asm/unaligned.h>
0024 
0025 #include "sigmadsp.h"
0026 #include "adau17x1.h"
0027 #include "adau-utils.h"
0028 
0029 #define ADAU17X1_SAFELOAD_TARGET_ADDRESS 0x0006
0030 #define ADAU17X1_SAFELOAD_TRIGGER 0x0007
0031 #define ADAU17X1_SAFELOAD_DATA 0x0001
0032 #define ADAU17X1_SAFELOAD_DATA_SIZE 20
0033 #define ADAU17X1_WORD_SIZE 4
0034 
0035 static const char * const adau17x1_capture_mixer_boost_text[] = {
0036     "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
0037 };
0038 
0039 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
0040     ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
0041 
0042 static const char * const adau17x1_mic_bias_mode_text[] = {
0043     "Normal operation", "High performance",
0044 };
0045 
0046 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
0047     ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
0048 
0049 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
0050 
0051 static const struct snd_kcontrol_new adau17x1_controls[] = {
0052     SOC_DOUBLE_R_TLV("Digital Capture Volume",
0053         ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
0054         ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
0055         0, 0xff, 1, adau17x1_digital_tlv),
0056     SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
0057         ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
0058 
0059     SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
0060         5, 1, 0),
0061     SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
0062         2, 1, 0),
0063 
0064     SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
0065 
0066     SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
0067 };
0068 
0069 static int adau17x1_setup_firmware(struct snd_soc_component *component,
0070     unsigned int rate);
0071 
0072 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
0073     struct snd_kcontrol *kcontrol, int event)
0074 {
0075     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0076     struct adau *adau = snd_soc_component_get_drvdata(component);
0077 
0078     if (SND_SOC_DAPM_EVENT_ON(event)) {
0079         adau->pll_regs[5] = 1;
0080     } else {
0081         adau->pll_regs[5] = 0;
0082         /* Bypass the PLL when disabled, otherwise registers will become
0083          * inaccessible. */
0084         regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
0085             ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
0086     }
0087 
0088     /* The PLL register is 6 bytes long and can only be written at once. */
0089     regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
0090             adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
0091 
0092     if (SND_SOC_DAPM_EVENT_ON(event)) {
0093         mdelay(5);
0094         regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
0095             ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
0096             ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
0097     }
0098 
0099     return 0;
0100 }
0101 
0102 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
0103     struct snd_kcontrol *kcontrol, int event)
0104 {
0105     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0106     struct adau *adau = snd_soc_component_get_drvdata(component);
0107 
0108     /*
0109      * If we are capturing, toggle the ADOSR bit in Converter Control 0 to
0110      * avoid losing SNR (workaround from ADI). This must be done after
0111      * the ADC(s) have been enabled. According to the data sheet, it is
0112      * normally illegal to set this bit when the sampling rate is 96 kHz,
0113      * but according to ADI it is acceptable for this workaround.
0114      */
0115     regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
0116         ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
0117     regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
0118         ADAU17X1_CONVERTER0_ADOSR, 0);
0119 
0120     return 0;
0121 }
0122 
0123 static const char * const adau17x1_mono_stereo_text[] = {
0124     "Stereo",
0125     "Mono Left Channel (L+R)",
0126     "Mono Right Channel (L+R)",
0127     "Mono (L+R)",
0128 };
0129 
0130 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
0131     ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
0132 
0133 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
0134     SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
0135 
0136 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
0137     SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
0138         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0139 
0140     SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
0141 
0142     SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
0143 
0144     SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
0145         0, 0, NULL, 0),
0146     SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
0147         1, 0, NULL, 0),
0148 
0149     SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
0150         &adau17x1_dac_mode_mux),
0151     SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
0152         &adau17x1_dac_mode_mux),
0153 
0154     SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
0155                adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
0156     SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
0157     SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
0158     SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
0159 };
0160 
0161 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
0162     { "Left Decimator", NULL, "SYSCLK" },
0163     { "Right Decimator", NULL, "SYSCLK" },
0164     { "Left DAC", NULL, "SYSCLK" },
0165     { "Right DAC", NULL, "SYSCLK" },
0166     { "Capture", NULL, "SYSCLK" },
0167     { "Playback", NULL, "SYSCLK" },
0168 
0169     { "Left DAC", NULL, "Left DAC Mode Mux" },
0170     { "Right DAC", NULL, "Right DAC Mode Mux" },
0171 
0172     { "Capture", NULL, "AIFCLK" },
0173     { "Playback", NULL, "AIFCLK" },
0174 };
0175 
0176 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
0177     "SYSCLK", NULL, "PLL",
0178 };
0179 
0180 /*
0181  * The MUX register for the Capture and Playback MUXs selects either DSP as
0182  * source/destination or one of the TDM slots. The TDM slot is selected via
0183  * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
0184  * directly to the DAI interface with this control.
0185  */
0186 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
0187     struct snd_ctl_elem_value *ucontrol)
0188 {
0189     struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
0190     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0191     struct adau *adau = snd_soc_component_get_drvdata(component);
0192     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0193     struct snd_soc_dapm_update update = {};
0194     unsigned int stream = e->shift_l;
0195     unsigned int val, change;
0196     int reg;
0197 
0198     if (ucontrol->value.enumerated.item[0] >= e->items)
0199         return -EINVAL;
0200 
0201     switch (ucontrol->value.enumerated.item[0]) {
0202     case 0:
0203         val = 0;
0204         adau->dsp_bypass[stream] = false;
0205         break;
0206     default:
0207         val = (adau->tdm_slot[stream] * 2) + 1;
0208         adau->dsp_bypass[stream] = true;
0209         break;
0210     }
0211 
0212     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0213         reg = ADAU17X1_SERIAL_INPUT_ROUTE;
0214     else
0215         reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
0216 
0217     change = snd_soc_component_test_bits(component, reg, 0xff, val);
0218     if (change) {
0219         update.kcontrol = kcontrol;
0220         update.mask = 0xff;
0221         update.reg = reg;
0222         update.val = val;
0223 
0224         snd_soc_dapm_mux_update_power(dapm, kcontrol,
0225                 ucontrol->value.enumerated.item[0], e, &update);
0226     }
0227 
0228     return change;
0229 }
0230 
0231 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
0232     struct snd_ctl_elem_value *ucontrol)
0233 {
0234     struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
0235     struct adau *adau = snd_soc_component_get_drvdata(component);
0236     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0237     unsigned int stream = e->shift_l;
0238     unsigned int reg, val;
0239     int ret;
0240 
0241     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0242         reg = ADAU17X1_SERIAL_INPUT_ROUTE;
0243     else
0244         reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
0245 
0246     ret = regmap_read(adau->regmap, reg, &val);
0247     if (ret)
0248         return ret;
0249 
0250     if (val != 0)
0251         val = 1;
0252     ucontrol->value.enumerated.item[0] = val;
0253 
0254     return 0;
0255 }
0256 
0257 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
0258     const struct snd_kcontrol_new _name = \
0259         SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
0260             SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
0261                 ARRAY_SIZE(_text), _text), \
0262             adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
0263 
0264 static const char * const adau17x1_dac_mux_text[] = {
0265     "DSP",
0266     "AIFIN",
0267 };
0268 
0269 static const char * const adau17x1_capture_mux_text[] = {
0270     "DSP",
0271     "Decimator",
0272 };
0273 
0274 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
0275     SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
0276 
0277 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
0278     SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
0279 
0280 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
0281     SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
0282     SND_SOC_DAPM_SIGGEN("DSP Siggen"),
0283 
0284     SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
0285         &adau17x1_dac_mux),
0286     SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
0287         &adau17x1_capture_mux),
0288 };
0289 
0290 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
0291     { "DAC Playback Mux", "DSP", "DSP" },
0292     { "DAC Playback Mux", "AIFIN", "Playback" },
0293 
0294     { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
0295     { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
0296     { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
0297     { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
0298     { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
0299     { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
0300 
0301     { "Capture Mux", "DSP", "DSP" },
0302     { "Capture Mux", "Decimator", "Left Decimator" },
0303     { "Capture Mux", "Decimator", "Right Decimator" },
0304 
0305     { "Capture", NULL, "Capture Mux" },
0306 
0307     { "DSP", NULL, "DSP Siggen" },
0308 
0309     { "DSP", NULL, "Left Decimator" },
0310     { "DSP", NULL, "Right Decimator" },
0311     { "DSP", NULL, "Playback" },
0312 };
0313 
0314 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
0315     { "Left DAC Mode Mux", "Stereo", "Playback" },
0316     { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
0317     { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
0318     { "Right DAC Mode Mux", "Stereo", "Playback" },
0319     { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
0320     { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
0321     { "Capture", NULL, "Left Decimator" },
0322     { "Capture", NULL, "Right Decimator" },
0323 };
0324 
0325 static bool adau17x1_has_dsp(struct adau *adau)
0326 {
0327     switch (adau->type) {
0328     case ADAU1761:
0329     case ADAU1381:
0330     case ADAU1781:
0331         return true;
0332     default:
0333         return false;
0334     }
0335 }
0336 
0337 /* Chip has a DSP but we're pretending it doesn't. */
0338 static bool adau17x1_has_disused_dsp(struct adau *adau)
0339 {
0340     switch (adau->type) {
0341     case ADAU1761_AS_1361:
0342         return true;
0343     default:
0344         return false;
0345     }
0346 }
0347 
0348 static bool adau17x1_has_safeload(struct adau *adau)
0349 {
0350     switch (adau->type) {
0351     case ADAU1761:
0352     case ADAU1781:
0353         return true;
0354     default:
0355         return false;
0356     }
0357 }
0358 
0359 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
0360     int source, unsigned int freq_in, unsigned int freq_out)
0361 {
0362     struct snd_soc_component *component = dai->component;
0363     struct adau *adau = snd_soc_component_get_drvdata(component);
0364     int ret;
0365 
0366     if (freq_in < 8000000 || freq_in > 27000000)
0367         return -EINVAL;
0368 
0369     ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
0370     if (ret < 0)
0371         return ret;
0372 
0373     /* The PLL register is 6 bytes long and can only be written at once. */
0374     ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
0375             adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
0376     if (ret)
0377         return ret;
0378 
0379     adau->pll_freq = freq_out;
0380 
0381     return 0;
0382 }
0383 
0384 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
0385         int clk_id, unsigned int freq, int dir)
0386 {
0387     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);
0388     struct adau *adau = snd_soc_component_get_drvdata(dai->component);
0389     bool is_pll;
0390     bool was_pll;
0391 
0392     switch (clk_id) {
0393     case ADAU17X1_CLK_SRC_MCLK:
0394         is_pll = false;
0395         break;
0396     case ADAU17X1_CLK_SRC_PLL_AUTO:
0397         if (!adau->mclk)
0398             return -EINVAL;
0399         fallthrough;
0400     case ADAU17X1_CLK_SRC_PLL:
0401         is_pll = true;
0402         break;
0403     default:
0404         return -EINVAL;
0405     }
0406 
0407     switch (adau->clk_src) {
0408     case ADAU17X1_CLK_SRC_MCLK:
0409         was_pll = false;
0410         break;
0411     case ADAU17X1_CLK_SRC_PLL:
0412     case ADAU17X1_CLK_SRC_PLL_AUTO:
0413         was_pll = true;
0414         break;
0415     default:
0416         return -EINVAL;
0417     }
0418 
0419     adau->sysclk = freq;
0420 
0421     if (is_pll != was_pll) {
0422         if (is_pll) {
0423             snd_soc_dapm_add_routes(dapm,
0424                 &adau17x1_dapm_pll_route, 1);
0425         } else {
0426             snd_soc_dapm_del_routes(dapm,
0427                 &adau17x1_dapm_pll_route, 1);
0428         }
0429     }
0430 
0431     adau->clk_src = clk_id;
0432 
0433     return 0;
0434 }
0435 
0436 static int adau17x1_auto_pll(struct snd_soc_dai *dai,
0437     struct snd_pcm_hw_params *params)
0438 {
0439     struct adau *adau = snd_soc_dai_get_drvdata(dai);
0440     unsigned int pll_rate;
0441 
0442     switch (params_rate(params)) {
0443     case 48000:
0444     case 8000:
0445     case 12000:
0446     case 16000:
0447     case 24000:
0448     case 32000:
0449     case 96000:
0450         pll_rate = 48000 * 1024;
0451         break;
0452     case 44100:
0453     case 7350:
0454     case 11025:
0455     case 14700:
0456     case 22050:
0457     case 29400:
0458     case 88200:
0459         pll_rate = 44100 * 1024;
0460         break;
0461     default:
0462         return -EINVAL;
0463     }
0464 
0465     return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
0466         clk_get_rate(adau->mclk), pll_rate);
0467 }
0468 
0469 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
0470     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0471 {
0472     struct snd_soc_component *component = dai->component;
0473     struct adau *adau = snd_soc_component_get_drvdata(component);
0474     unsigned int val, div, dsp_div;
0475     unsigned int freq;
0476     int ret;
0477 
0478     switch (adau->clk_src) {
0479     case ADAU17X1_CLK_SRC_PLL_AUTO:
0480         ret = adau17x1_auto_pll(dai, params);
0481         if (ret)
0482             return ret;
0483         fallthrough;
0484     case ADAU17X1_CLK_SRC_PLL:
0485         freq = adau->pll_freq;
0486         break;
0487     default:
0488         freq = adau->sysclk;
0489         break;
0490     }
0491 
0492     if (freq % params_rate(params) != 0)
0493         return -EINVAL;
0494 
0495     switch (freq / params_rate(params)) {
0496     case 1024: /* fs */
0497         div = 0;
0498         dsp_div = 1;
0499         break;
0500     case 6144: /* fs / 6 */
0501         div = 1;
0502         dsp_div = 6;
0503         break;
0504     case 4096: /* fs / 4 */
0505         div = 2;
0506         dsp_div = 5;
0507         break;
0508     case 3072: /* fs / 3 */
0509         div = 3;
0510         dsp_div = 4;
0511         break;
0512     case 2048: /* fs / 2 */
0513         div = 4;
0514         dsp_div = 3;
0515         break;
0516     case 1536: /* fs / 1.5 */
0517         div = 5;
0518         dsp_div = 2;
0519         break;
0520     case 512: /* fs / 0.5 */
0521         div = 6;
0522         dsp_div = 0;
0523         break;
0524     default:
0525         return -EINVAL;
0526     }
0527 
0528     regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
0529         ADAU17X1_CONVERTER0_CONVSR_MASK, div);
0530 
0531     if (adau17x1_has_dsp(adau) || adau17x1_has_disused_dsp(adau))
0532         regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
0533     if (adau17x1_has_dsp(adau))
0534         regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
0535 
0536     if (adau->sigmadsp) {
0537         ret = adau17x1_setup_firmware(component, params_rate(params));
0538         if (ret < 0)
0539             return ret;
0540     }
0541 
0542     if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
0543         return 0;
0544 
0545     switch (params_width(params)) {
0546     case 16:
0547         val = ADAU17X1_SERIAL_PORT1_DELAY16;
0548         break;
0549     case 24:
0550         val = ADAU17X1_SERIAL_PORT1_DELAY8;
0551         break;
0552     case 32:
0553         val = ADAU17X1_SERIAL_PORT1_DELAY0;
0554         break;
0555     default:
0556         return -EINVAL;
0557     }
0558 
0559     return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
0560             ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
0561 }
0562 
0563 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
0564         unsigned int fmt)
0565 {
0566     struct adau *adau = snd_soc_component_get_drvdata(dai->component);
0567     unsigned int ctrl0, ctrl1;
0568     unsigned int ctrl0_mask;
0569     int lrclk_pol;
0570 
0571     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0572     case SND_SOC_DAIFMT_CBP_CFP:
0573         ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
0574         adau->master = true;
0575         break;
0576     case SND_SOC_DAIFMT_CBC_CFC:
0577         ctrl0 = 0;
0578         adau->master = false;
0579         break;
0580     default:
0581         return -EINVAL;
0582     }
0583 
0584     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0585     case SND_SOC_DAIFMT_I2S:
0586         lrclk_pol = 0;
0587         ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
0588         break;
0589     case SND_SOC_DAIFMT_LEFT_J:
0590     case SND_SOC_DAIFMT_RIGHT_J:
0591         lrclk_pol = 1;
0592         ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
0593         break;
0594     case SND_SOC_DAIFMT_DSP_A:
0595         lrclk_pol = 1;
0596         ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
0597         ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
0598         break;
0599     case SND_SOC_DAIFMT_DSP_B:
0600         lrclk_pol = 1;
0601         ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
0602         ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
0603         break;
0604     default:
0605         return -EINVAL;
0606     }
0607 
0608     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0609     case SND_SOC_DAIFMT_NB_NF:
0610         break;
0611     case SND_SOC_DAIFMT_IB_NF:
0612         ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
0613         break;
0614     case SND_SOC_DAIFMT_NB_IF:
0615         lrclk_pol = !lrclk_pol;
0616         break;
0617     case SND_SOC_DAIFMT_IB_IF:
0618         ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
0619         lrclk_pol = !lrclk_pol;
0620         break;
0621     default:
0622         return -EINVAL;
0623     }
0624 
0625     if (lrclk_pol)
0626         ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
0627 
0628     /* Set the mask to update all relevant bits in ADAU17X1_SERIAL_PORT0 */
0629     ctrl0_mask = ADAU17X1_SERIAL_PORT0_MASTER |
0630              ADAU17X1_SERIAL_PORT0_LRCLK_POL |
0631              ADAU17X1_SERIAL_PORT0_BCLK_POL |
0632              ADAU17X1_SERIAL_PORT0_PULSE_MODE;
0633 
0634     regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0_mask,
0635                ctrl0);
0636     regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
0637                ADAU17X1_SERIAL_PORT1_DELAY_MASK, ctrl1);
0638 
0639     adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0640 
0641     return 0;
0642 }
0643 
0644 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
0645     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
0646 {
0647     struct adau *adau = snd_soc_component_get_drvdata(dai->component);
0648     unsigned int ser_ctrl0, ser_ctrl1;
0649     unsigned int conv_ctrl0, conv_ctrl1;
0650 
0651     /* I2S mode */
0652     if (slots == 0) {
0653         slots = 2;
0654         rx_mask = 3;
0655         tx_mask = 3;
0656         slot_width = 32;
0657     }
0658 
0659     switch (slots) {
0660     case 2:
0661         ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
0662         break;
0663     case 4:
0664         ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
0665         break;
0666     case 8:
0667         if (adau->type == ADAU1361)
0668             return -EINVAL;
0669 
0670         ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
0671         break;
0672     default:
0673         return -EINVAL;
0674     }
0675 
0676     switch (slot_width * slots) {
0677     case 32:
0678         if (adau->type == ADAU1761 || adau->type == ADAU1761_AS_1361)
0679             return -EINVAL;
0680 
0681         ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
0682         break;
0683     case 64:
0684         ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
0685         break;
0686     case 48:
0687         ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
0688         break;
0689     case 128:
0690         ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
0691         break;
0692     case 256:
0693         if (adau->type == ADAU1361)
0694             return -EINVAL;
0695 
0696         ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
0697         break;
0698     default:
0699         return -EINVAL;
0700     }
0701 
0702     switch (rx_mask) {
0703     case 0x03:
0704         conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
0705         adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
0706         break;
0707     case 0x0c:
0708         conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
0709         adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
0710         break;
0711     case 0x30:
0712         conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
0713         adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
0714         break;
0715     case 0xc0:
0716         conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
0717         adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
0718         break;
0719     default:
0720         return -EINVAL;
0721     }
0722 
0723     switch (tx_mask) {
0724     case 0x03:
0725         conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
0726         adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
0727         break;
0728     case 0x0c:
0729         conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
0730         adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
0731         break;
0732     case 0x30:
0733         conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
0734         adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
0735         break;
0736     case 0xc0:
0737         conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
0738         adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
0739         break;
0740     default:
0741         return -EINVAL;
0742     }
0743 
0744     regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
0745         ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
0746     regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
0747         ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
0748     regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
0749         ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
0750     regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
0751         ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
0752 
0753     if (!adau17x1_has_dsp(adau) && !adau17x1_has_disused_dsp(adau))
0754         return 0;
0755 
0756     if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
0757         regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
0758             (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
0759     }
0760 
0761     if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
0762         regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
0763             (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
0764     }
0765 
0766     return 0;
0767 }
0768 
0769 static int adau17x1_startup(struct snd_pcm_substream *substream,
0770     struct snd_soc_dai *dai)
0771 {
0772     struct adau *adau = snd_soc_component_get_drvdata(dai->component);
0773 
0774     if (adau->sigmadsp)
0775         return sigmadsp_restrict_params(adau->sigmadsp, substream);
0776 
0777     return 0;
0778 }
0779 
0780 const struct snd_soc_dai_ops adau17x1_dai_ops = {
0781     .hw_params  = adau17x1_hw_params,
0782     .set_sysclk = adau17x1_set_dai_sysclk,
0783     .set_fmt    = adau17x1_set_dai_fmt,
0784     .set_pll    = adau17x1_set_dai_pll,
0785     .set_tdm_slot   = adau17x1_set_dai_tdm_slot,
0786     .startup    = adau17x1_startup,
0787 };
0788 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
0789 
0790 int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
0791     enum adau17x1_micbias_voltage micbias)
0792 {
0793     struct adau *adau = snd_soc_component_get_drvdata(component);
0794 
0795     switch (micbias) {
0796     case ADAU17X1_MICBIAS_0_90_AVDD:
0797     case ADAU17X1_MICBIAS_0_65_AVDD:
0798         break;
0799     default:
0800         return -EINVAL;
0801     }
0802 
0803     return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
0804 }
0805 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
0806 
0807 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
0808 {
0809     /* SigmaDSP parameter memory */
0810     if (reg < 0x400)
0811         return true;
0812 
0813     return false;
0814 }
0815 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
0816 
0817 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
0818 {
0819     /* SigmaDSP parameter memory */
0820     if (reg < 0x400)
0821         return true;
0822 
0823     switch (reg) {
0824     case ADAU17X1_CLOCK_CONTROL:
0825     case ADAU17X1_PLL_CONTROL:
0826     case ADAU17X1_REC_POWER_MGMT:
0827     case ADAU17X1_MICBIAS:
0828     case ADAU17X1_SERIAL_PORT0:
0829     case ADAU17X1_SERIAL_PORT1:
0830     case ADAU17X1_CONVERTER0:
0831     case ADAU17X1_CONVERTER1:
0832     case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
0833     case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
0834     case ADAU17X1_ADC_CONTROL:
0835     case ADAU17X1_PLAY_POWER_MGMT:
0836     case ADAU17X1_DAC_CONTROL0:
0837     case ADAU17X1_DAC_CONTROL1:
0838     case ADAU17X1_DAC_CONTROL2:
0839     case ADAU17X1_SERIAL_PORT_PAD:
0840     case ADAU17X1_CONTROL_PORT_PAD0:
0841     case ADAU17X1_CONTROL_PORT_PAD1:
0842     case ADAU17X1_DSP_SAMPLING_RATE:
0843     case ADAU17X1_SERIAL_INPUT_ROUTE:
0844     case ADAU17X1_SERIAL_OUTPUT_ROUTE:
0845     case ADAU17X1_DSP_ENABLE:
0846     case ADAU17X1_DSP_RUN:
0847     case ADAU17X1_SERIAL_SAMPLING_RATE:
0848         return true;
0849     default:
0850         break;
0851     }
0852     return false;
0853 }
0854 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
0855 
0856 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
0857 {
0858     /* SigmaDSP parameter and program memory */
0859     if (reg < 0x4000)
0860         return true;
0861 
0862     switch (reg) {
0863     /* The PLL register is 6 bytes long */
0864     case ADAU17X1_PLL_CONTROL:
0865     case ADAU17X1_PLL_CONTROL + 1:
0866     case ADAU17X1_PLL_CONTROL + 2:
0867     case ADAU17X1_PLL_CONTROL + 3:
0868     case ADAU17X1_PLL_CONTROL + 4:
0869     case ADAU17X1_PLL_CONTROL + 5:
0870         return true;
0871     default:
0872         break;
0873     }
0874 
0875     return false;
0876 }
0877 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
0878 
0879 static int adau17x1_setup_firmware(struct snd_soc_component *component,
0880     unsigned int rate)
0881 {
0882     int ret;
0883     int dspsr, dsp_run;
0884     struct adau *adau = snd_soc_component_get_drvdata(component);
0885     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0886 
0887     /* Check if sample rate is the same as before. If it is there is no
0888      * point in performing the below steps as the call to
0889      * sigmadsp_setup(...) will return directly when it finds the sample
0890      * rate to be the same as before. By checking this we can prevent an
0891      * audiable popping noise which occours when toggling DSP_RUN.
0892      */
0893     if (adau->sigmadsp->current_samplerate == rate)
0894         return 0;
0895 
0896     snd_soc_dapm_mutex_lock(dapm);
0897 
0898     ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
0899     if (ret)
0900         goto err;
0901 
0902     ret = regmap_read(adau->regmap, ADAU17X1_DSP_RUN, &dsp_run);
0903     if (ret)
0904         goto err;
0905 
0906     regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
0907     regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
0908     regmap_write(adau->regmap, ADAU17X1_DSP_RUN, 0);
0909 
0910     ret = sigmadsp_setup(adau->sigmadsp, rate);
0911     if (ret) {
0912         regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
0913         goto err;
0914     }
0915     regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
0916     regmap_write(adau->regmap, ADAU17X1_DSP_RUN, dsp_run);
0917 
0918 err:
0919     snd_soc_dapm_mutex_unlock(dapm);
0920 
0921     return ret;
0922 }
0923 
0924 int adau17x1_add_widgets(struct snd_soc_component *component)
0925 {
0926     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0927     struct adau *adau = snd_soc_component_get_drvdata(component);
0928     int ret;
0929 
0930     ret = snd_soc_add_component_controls(component, adau17x1_controls,
0931         ARRAY_SIZE(adau17x1_controls));
0932     if (ret)
0933         return ret;
0934     ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
0935         ARRAY_SIZE(adau17x1_dapm_widgets));
0936     if (ret)
0937         return ret;
0938 
0939     if (adau17x1_has_dsp(adau)) {
0940         ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
0941             ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
0942         if (ret)
0943             return ret;
0944 
0945         if (!adau->sigmadsp)
0946             return 0;
0947 
0948         ret = sigmadsp_attach(adau->sigmadsp, component);
0949         if (ret) {
0950             dev_err(component->dev, "Failed to attach firmware: %d\n",
0951                 ret);
0952             return ret;
0953         }
0954     }
0955 
0956     return 0;
0957 }
0958 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
0959 
0960 int adau17x1_add_routes(struct snd_soc_component *component)
0961 {
0962     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0963     struct adau *adau = snd_soc_component_get_drvdata(component);
0964     int ret;
0965 
0966     ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
0967         ARRAY_SIZE(adau17x1_dapm_routes));
0968     if (ret)
0969         return ret;
0970 
0971     if (adau17x1_has_dsp(adau)) {
0972         ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
0973             ARRAY_SIZE(adau17x1_dsp_dapm_routes));
0974     } else {
0975         ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
0976             ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
0977     }
0978 
0979     if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
0980         snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
0981 
0982     return ret;
0983 }
0984 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
0985 
0986 int adau17x1_resume(struct snd_soc_component *component)
0987 {
0988     struct adau *adau = snd_soc_component_get_drvdata(component);
0989 
0990     if (adau->switch_mode)
0991         adau->switch_mode(component->dev);
0992 
0993     regcache_sync(adau->regmap);
0994 
0995     return 0;
0996 }
0997 EXPORT_SYMBOL_GPL(adau17x1_resume);
0998 
0999 static int adau17x1_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
1000     const uint8_t bytes[], size_t len)
1001 {
1002     uint8_t buf[ADAU17X1_WORD_SIZE];
1003     uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE];
1004     unsigned int addr_offset;
1005     unsigned int nbr_words;
1006     int ret;
1007 
1008     /* write data to safeload addresses. Check if len is not a multiple of
1009      * 4 bytes, if so we need to zero pad.
1010      */
1011     nbr_words = len / ADAU17X1_WORD_SIZE;
1012     if ((len - nbr_words * ADAU17X1_WORD_SIZE) == 0) {
1013         ret = regmap_raw_write(sigmadsp->control_data,
1014             ADAU17X1_SAFELOAD_DATA, bytes, len);
1015     } else {
1016         nbr_words++;
1017         memset(data, 0, ADAU17X1_SAFELOAD_DATA_SIZE);
1018         memcpy(data, bytes, len);
1019         ret = regmap_raw_write(sigmadsp->control_data,
1020             ADAU17X1_SAFELOAD_DATA, data,
1021             nbr_words * ADAU17X1_WORD_SIZE);
1022     }
1023 
1024     if (ret < 0)
1025         return ret;
1026 
1027     /* Write target address, target address is offset by 1 */
1028     addr_offset = addr - 1;
1029     put_unaligned_be32(addr_offset, buf);
1030     ret = regmap_raw_write(sigmadsp->control_data,
1031         ADAU17X1_SAFELOAD_TARGET_ADDRESS, buf, ADAU17X1_WORD_SIZE);
1032     if (ret < 0)
1033         return ret;
1034 
1035     /* write nbr of words to trigger address */
1036     put_unaligned_be32(nbr_words, buf);
1037     ret = regmap_raw_write(sigmadsp->control_data,
1038         ADAU17X1_SAFELOAD_TRIGGER, buf, ADAU17X1_WORD_SIZE);
1039     if (ret < 0)
1040         return ret;
1041 
1042     return 0;
1043 }
1044 
1045 static const struct sigmadsp_ops adau17x1_sigmadsp_ops = {
1046     .safeload = adau17x1_safeload,
1047 };
1048 
1049 int adau17x1_probe(struct device *dev, struct regmap *regmap,
1050     enum adau17x1_type type, void (*switch_mode)(struct device *dev),
1051     const char *firmware_name)
1052 {
1053     struct adau *adau;
1054     int ret;
1055 
1056     if (IS_ERR(regmap))
1057         return PTR_ERR(regmap);
1058 
1059     adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
1060     if (!adau)
1061         return -ENOMEM;
1062 
1063     adau->mclk = devm_clk_get(dev, "mclk");
1064     if (IS_ERR(adau->mclk)) {
1065         if (PTR_ERR(adau->mclk) != -ENOENT)
1066             return PTR_ERR(adau->mclk);
1067         /* Clock is optional (for the driver) */
1068         adau->mclk = NULL;
1069     } else if (adau->mclk) {
1070         adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
1071 
1072         /*
1073          * Any valid PLL output rate will work at this point, use one
1074          * that is likely to be chosen later as well. The register will
1075          * be written when the PLL is powered up for the first time.
1076          */
1077         ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
1078                 adau->pll_regs);
1079         if (ret < 0)
1080             return ret;
1081 
1082         ret = clk_prepare_enable(adau->mclk);
1083         if (ret)
1084             return ret;
1085     }
1086 
1087     adau->regmap = regmap;
1088     adau->switch_mode = switch_mode;
1089     adau->type = type;
1090 
1091     dev_set_drvdata(dev, adau);
1092 
1093     if (firmware_name) {
1094         if (adau17x1_has_safeload(adau)) {
1095             adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
1096                 &adau17x1_sigmadsp_ops, firmware_name);
1097         } else {
1098             adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap,
1099                 NULL, firmware_name);
1100         }
1101         if (IS_ERR(adau->sigmadsp)) {
1102             dev_warn(dev, "Could not find firmware file: %ld\n",
1103                 PTR_ERR(adau->sigmadsp));
1104             adau->sigmadsp = NULL;
1105         }
1106     }
1107 
1108     if (switch_mode)
1109         switch_mode(dev);
1110 
1111     return 0;
1112 }
1113 EXPORT_SYMBOL_GPL(adau17x1_probe);
1114 
1115 void adau17x1_remove(struct device *dev)
1116 {
1117     struct adau *adau = dev_get_drvdata(dev);
1118 
1119     clk_disable_unprepare(adau->mclk);
1120 }
1121 EXPORT_SYMBOL_GPL(adau17x1_remove);
1122 
1123 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
1124 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1125 MODULE_LICENSE("GPL");
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