0001
0002 #ifndef __ADAU1373_H__
0003 #define __ADAU1373_H__
0004
0005 enum adau1373_pll_src {
0006 ADAU1373_PLL_SRC_MCLK1 = 0,
0007 ADAU1373_PLL_SRC_BCLK1 = 1,
0008 ADAU1373_PLL_SRC_BCLK2 = 2,
0009 ADAU1373_PLL_SRC_BCLK3 = 3,
0010 ADAU1373_PLL_SRC_LRCLK1 = 4,
0011 ADAU1373_PLL_SRC_LRCLK2 = 5,
0012 ADAU1373_PLL_SRC_LRCLK3 = 6,
0013 ADAU1373_PLL_SRC_GPIO1 = 7,
0014 ADAU1373_PLL_SRC_GPIO2 = 8,
0015 ADAU1373_PLL_SRC_GPIO3 = 9,
0016 ADAU1373_PLL_SRC_GPIO4 = 10,
0017 ADAU1373_PLL_SRC_MCLK2 = 11,
0018 };
0019
0020 enum adau1373_pll {
0021 ADAU1373_PLL1 = 0,
0022 ADAU1373_PLL2 = 1,
0023 };
0024
0025 enum adau1373_clk_src {
0026 ADAU1373_CLK_SRC_PLL1 = 0,
0027 ADAU1373_CLK_SRC_PLL2 = 1,
0028 };
0029
0030 #endif