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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Analog Devices ADAU1373 Audio Codec drive
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  * Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/delay.h>
0012 #include <linux/pm.h>
0013 #include <linux/i2c.h>
0014 #include <linux/slab.h>
0015 #include <linux/gcd.h>
0016 
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/tlv.h>
0021 #include <sound/soc.h>
0022 #include <sound/adau1373.h>
0023 
0024 #include "adau1373.h"
0025 #include "adau-utils.h"
0026 
0027 struct adau1373_dai {
0028     unsigned int clk_src;
0029     unsigned int sysclk;
0030     bool enable_src;
0031     bool clock_provider;
0032 };
0033 
0034 struct adau1373 {
0035     struct regmap *regmap;
0036     struct adau1373_dai dais[3];
0037 };
0038 
0039 #define ADAU1373_INPUT_MODE 0x00
0040 #define ADAU1373_AINL_CTRL(x)   (0x01 + (x) * 2)
0041 #define ADAU1373_AINR_CTRL(x)   (0x02 + (x) * 2)
0042 #define ADAU1373_LLINE_OUT(x)   (0x9 + (x) * 2)
0043 #define ADAU1373_RLINE_OUT(x)   (0xa + (x) * 2)
0044 #define ADAU1373_LSPK_OUT   0x0d
0045 #define ADAU1373_RSPK_OUT   0x0e
0046 #define ADAU1373_LHP_OUT    0x0f
0047 #define ADAU1373_RHP_OUT    0x10
0048 #define ADAU1373_ADC_GAIN   0x11
0049 #define ADAU1373_LADC_MIXER 0x12
0050 #define ADAU1373_RADC_MIXER 0x13
0051 #define ADAU1373_LLINE1_MIX 0x14
0052 #define ADAU1373_RLINE1_MIX 0x15
0053 #define ADAU1373_LLINE2_MIX 0x16
0054 #define ADAU1373_RLINE2_MIX 0x17
0055 #define ADAU1373_LSPK_MIX   0x18
0056 #define ADAU1373_RSPK_MIX   0x19
0057 #define ADAU1373_LHP_MIX    0x1a
0058 #define ADAU1373_RHP_MIX    0x1b
0059 #define ADAU1373_EP_MIX     0x1c
0060 #define ADAU1373_HP_CTRL    0x1d
0061 #define ADAU1373_HP_CTRL2   0x1e
0062 #define ADAU1373_LS_CTRL    0x1f
0063 #define ADAU1373_EP_CTRL    0x21
0064 #define ADAU1373_MICBIAS_CTRL1  0x22
0065 #define ADAU1373_MICBIAS_CTRL2  0x23
0066 #define ADAU1373_OUTPUT_CTRL    0x24
0067 #define ADAU1373_PWDN_CTRL1 0x25
0068 #define ADAU1373_PWDN_CTRL2 0x26
0069 #define ADAU1373_PWDN_CTRL3 0x27
0070 #define ADAU1373_DPLL_CTRL(x)   (0x28 + (x) * 7)
0071 #define ADAU1373_PLL_CTRL1(x)   (0x29 + (x) * 7)
0072 #define ADAU1373_PLL_CTRL2(x)   (0x2a + (x) * 7)
0073 #define ADAU1373_PLL_CTRL3(x)   (0x2b + (x) * 7)
0074 #define ADAU1373_PLL_CTRL4(x)   (0x2c + (x) * 7)
0075 #define ADAU1373_PLL_CTRL5(x)   (0x2d + (x) * 7)
0076 #define ADAU1373_PLL_CTRL6(x)   (0x2e + (x) * 7)
0077 #define ADAU1373_HEADDECT   0x36
0078 #define ADAU1373_ADC_DAC_STATUS 0x37
0079 #define ADAU1373_ADC_CTRL   0x3c
0080 #define ADAU1373_DAI(x)     (0x44 + (x))
0081 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
0082 #define ADAU1373_BCLKDIV(x) (0x47 + (x))
0083 #define ADAU1373_SRC_RATIOA(x)  (0x4a + (x) * 2)
0084 #define ADAU1373_SRC_RATIOB(x)  (0x4b + (x) * 2)
0085 #define ADAU1373_DEEMP_CTRL 0x50
0086 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
0087 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
0088 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
0089 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
0090 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
0091 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
0092 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
0093 #define ADAU1373_DAC1_PBL_VOL   0x6e
0094 #define ADAU1373_DAC1_PBR_VOL   0x6f
0095 #define ADAU1373_DAC2_PBL_VOL   0x70
0096 #define ADAU1373_DAC2_PBR_VOL   0x71
0097 #define ADAU1373_ADC_RECL_VOL   0x72
0098 #define ADAU1373_ADC_RECR_VOL   0x73
0099 #define ADAU1373_DMIC_RECL_VOL  0x74
0100 #define ADAU1373_DMIC_RECR_VOL  0x75
0101 #define ADAU1373_VOL_GAIN1  0x76
0102 #define ADAU1373_VOL_GAIN2  0x77
0103 #define ADAU1373_VOL_GAIN3  0x78
0104 #define ADAU1373_HPF_CTRL   0x7d
0105 #define ADAU1373_BASS1      0x7e
0106 #define ADAU1373_BASS2      0x7f
0107 #define ADAU1373_DRC(x)     (0x80 + (x) * 0x10)
0108 #define ADAU1373_3D_CTRL1   0xc0
0109 #define ADAU1373_3D_CTRL2   0xc1
0110 #define ADAU1373_FDSP_SEL1  0xdc
0111 #define ADAU1373_FDSP_SEL2  0xdd
0112 #define ADAU1373_FDSP_SEL3  0xde
0113 #define ADAU1373_FDSP_SEL4  0xdf
0114 #define ADAU1373_DIGMICCTRL 0xe2
0115 #define ADAU1373_DIGEN      0xeb
0116 #define ADAU1373_SOFT_RESET 0xff
0117 
0118 
0119 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS  BIT(1)
0120 #define ADAU1373_PLL_CTRL6_PLL_EN   BIT(0)
0121 
0122 #define ADAU1373_DAI_INVERT_BCLK    BIT(7)
0123 #define ADAU1373_DAI_MASTER     BIT(6)
0124 #define ADAU1373_DAI_INVERT_LRCLK   BIT(4)
0125 #define ADAU1373_DAI_WLEN_16        0x0
0126 #define ADAU1373_DAI_WLEN_20        0x4
0127 #define ADAU1373_DAI_WLEN_24        0x8
0128 #define ADAU1373_DAI_WLEN_32        0xc
0129 #define ADAU1373_DAI_WLEN_MASK      0xc
0130 #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0
0131 #define ADAU1373_DAI_FORMAT_LEFT_J  0x1
0132 #define ADAU1373_DAI_FORMAT_I2S     0x2
0133 #define ADAU1373_DAI_FORMAT_DSP     0x3
0134 
0135 #define ADAU1373_BCLKDIV_SOURCE     BIT(5)
0136 #define ADAU1373_BCLKDIV_SR_MASK    (0x07 << 2)
0137 #define ADAU1373_BCLKDIV_BCLK_MASK  0x03
0138 #define ADAU1373_BCLKDIV_32     0x03
0139 #define ADAU1373_BCLKDIV_64     0x02
0140 #define ADAU1373_BCLKDIV_128        0x01
0141 #define ADAU1373_BCLKDIV_256        0x00
0142 
0143 #define ADAU1373_ADC_CTRL_PEAK_DETECT   BIT(0)
0144 #define ADAU1373_ADC_CTRL_RESET     BIT(1)
0145 #define ADAU1373_ADC_CTRL_RESET_FORCE   BIT(2)
0146 
0147 #define ADAU1373_OUTPUT_CTRL_LDIFF  BIT(3)
0148 #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2)
0149 
0150 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
0151 
0152 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
0153 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
0154 
0155 static const struct reg_default adau1373_reg_defaults[] = {
0156     { ADAU1373_INPUT_MODE,      0x00 },
0157     { ADAU1373_AINL_CTRL(0),    0x00 },
0158     { ADAU1373_AINR_CTRL(0),    0x00 },
0159     { ADAU1373_AINL_CTRL(1),    0x00 },
0160     { ADAU1373_AINR_CTRL(1),    0x00 },
0161     { ADAU1373_AINL_CTRL(2),    0x00 },
0162     { ADAU1373_AINR_CTRL(2),    0x00 },
0163     { ADAU1373_AINL_CTRL(3),    0x00 },
0164     { ADAU1373_AINR_CTRL(3),    0x00 },
0165     { ADAU1373_LLINE_OUT(0),    0x00 },
0166     { ADAU1373_RLINE_OUT(0),    0x00 },
0167     { ADAU1373_LLINE_OUT(1),    0x00 },
0168     { ADAU1373_RLINE_OUT(1),    0x00 },
0169     { ADAU1373_LSPK_OUT,        0x00 },
0170     { ADAU1373_RSPK_OUT,        0x00 },
0171     { ADAU1373_LHP_OUT,     0x00 },
0172     { ADAU1373_RHP_OUT,     0x00 },
0173     { ADAU1373_ADC_GAIN,        0x00 },
0174     { ADAU1373_LADC_MIXER,      0x00 },
0175     { ADAU1373_RADC_MIXER,      0x00 },
0176     { ADAU1373_LLINE1_MIX,      0x00 },
0177     { ADAU1373_RLINE1_MIX,      0x00 },
0178     { ADAU1373_LLINE2_MIX,      0x00 },
0179     { ADAU1373_RLINE2_MIX,      0x00 },
0180     { ADAU1373_LSPK_MIX,        0x00 },
0181     { ADAU1373_RSPK_MIX,        0x00 },
0182     { ADAU1373_LHP_MIX,     0x00 },
0183     { ADAU1373_RHP_MIX,     0x00 },
0184     { ADAU1373_EP_MIX,      0x00 },
0185     { ADAU1373_HP_CTRL,     0x00 },
0186     { ADAU1373_HP_CTRL2,        0x00 },
0187     { ADAU1373_LS_CTRL,     0x00 },
0188     { ADAU1373_EP_CTRL,     0x00 },
0189     { ADAU1373_MICBIAS_CTRL1,   0x00 },
0190     { ADAU1373_MICBIAS_CTRL2,   0x00 },
0191     { ADAU1373_OUTPUT_CTRL,     0x00 },
0192     { ADAU1373_PWDN_CTRL1,      0x00 },
0193     { ADAU1373_PWDN_CTRL2,      0x00 },
0194     { ADAU1373_PWDN_CTRL3,      0x00 },
0195     { ADAU1373_DPLL_CTRL(0),    0x00 },
0196     { ADAU1373_PLL_CTRL1(0),    0x00 },
0197     { ADAU1373_PLL_CTRL2(0),    0x00 },
0198     { ADAU1373_PLL_CTRL3(0),    0x00 },
0199     { ADAU1373_PLL_CTRL4(0),    0x00 },
0200     { ADAU1373_PLL_CTRL5(0),    0x00 },
0201     { ADAU1373_PLL_CTRL6(0),    0x02 },
0202     { ADAU1373_DPLL_CTRL(1),    0x00 },
0203     { ADAU1373_PLL_CTRL1(1),    0x00 },
0204     { ADAU1373_PLL_CTRL2(1),    0x00 },
0205     { ADAU1373_PLL_CTRL3(1),    0x00 },
0206     { ADAU1373_PLL_CTRL4(1),    0x00 },
0207     { ADAU1373_PLL_CTRL5(1),    0x00 },
0208     { ADAU1373_PLL_CTRL6(1),    0x02 },
0209     { ADAU1373_HEADDECT,        0x00 },
0210     { ADAU1373_ADC_CTRL,        0x00 },
0211     { ADAU1373_CLK_SRC_DIV(0),  0x00 },
0212     { ADAU1373_CLK_SRC_DIV(1),  0x00 },
0213     { ADAU1373_DAI(0),      0x0a },
0214     { ADAU1373_DAI(1),      0x0a },
0215     { ADAU1373_DAI(2),      0x0a },
0216     { ADAU1373_BCLKDIV(0),      0x00 },
0217     { ADAU1373_BCLKDIV(1),      0x00 },
0218     { ADAU1373_BCLKDIV(2),      0x00 },
0219     { ADAU1373_SRC_RATIOA(0),   0x00 },
0220     { ADAU1373_SRC_RATIOB(0),   0x00 },
0221     { ADAU1373_SRC_RATIOA(1),   0x00 },
0222     { ADAU1373_SRC_RATIOB(1),   0x00 },
0223     { ADAU1373_SRC_RATIOA(2),   0x00 },
0224     { ADAU1373_SRC_RATIOB(2),   0x00 },
0225     { ADAU1373_DEEMP_CTRL,      0x00 },
0226     { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
0227     { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
0228     { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
0229     { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
0230     { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
0231     { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
0232     { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
0233     { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
0234     { ADAU1373_DOUT_MIX_CTRL(0),    0x00 },
0235     { ADAU1373_DOUT_MIX_CTRL(1),    0x00 },
0236     { ADAU1373_DOUT_MIX_CTRL(2),    0x00 },
0237     { ADAU1373_DOUT_MIX_CTRL(3),    0x00 },
0238     { ADAU1373_DOUT_MIX_CTRL(4),    0x00 },
0239     { ADAU1373_DAI_PBL_VOL(0),  0x00 },
0240     { ADAU1373_DAI_PBR_VOL(0),  0x00 },
0241     { ADAU1373_DAI_PBL_VOL(1),  0x00 },
0242     { ADAU1373_DAI_PBR_VOL(1),  0x00 },
0243     { ADAU1373_DAI_PBL_VOL(2),  0x00 },
0244     { ADAU1373_DAI_PBR_VOL(2),  0x00 },
0245     { ADAU1373_DAI_RECL_VOL(0), 0x00 },
0246     { ADAU1373_DAI_RECR_VOL(0), 0x00 },
0247     { ADAU1373_DAI_RECL_VOL(1), 0x00 },
0248     { ADAU1373_DAI_RECR_VOL(1), 0x00 },
0249     { ADAU1373_DAI_RECL_VOL(2), 0x00 },
0250     { ADAU1373_DAI_RECR_VOL(2), 0x00 },
0251     { ADAU1373_DAC1_PBL_VOL,    0x00 },
0252     { ADAU1373_DAC1_PBR_VOL,    0x00 },
0253     { ADAU1373_DAC2_PBL_VOL,    0x00 },
0254     { ADAU1373_DAC2_PBR_VOL,    0x00 },
0255     { ADAU1373_ADC_RECL_VOL,    0x00 },
0256     { ADAU1373_ADC_RECR_VOL,    0x00 },
0257     { ADAU1373_DMIC_RECL_VOL,   0x00 },
0258     { ADAU1373_DMIC_RECR_VOL,   0x00 },
0259     { ADAU1373_VOL_GAIN1,       0x00 },
0260     { ADAU1373_VOL_GAIN2,       0x00 },
0261     { ADAU1373_VOL_GAIN3,       0x00 },
0262     { ADAU1373_HPF_CTRL,        0x00 },
0263     { ADAU1373_BASS1,       0x00 },
0264     { ADAU1373_BASS2,       0x00 },
0265     { ADAU1373_DRC(0) + 0x0,    0x78 },
0266     { ADAU1373_DRC(0) + 0x1,    0x18 },
0267     { ADAU1373_DRC(0) + 0x2,    0x00 },
0268     { ADAU1373_DRC(0) + 0x3,    0x00 },
0269     { ADAU1373_DRC(0) + 0x4,    0x00 },
0270     { ADAU1373_DRC(0) + 0x5,    0xc0 },
0271     { ADAU1373_DRC(0) + 0x6,    0x00 },
0272     { ADAU1373_DRC(0) + 0x7,    0x00 },
0273     { ADAU1373_DRC(0) + 0x8,    0x00 },
0274     { ADAU1373_DRC(0) + 0x9,    0xc0 },
0275     { ADAU1373_DRC(0) + 0xa,    0x88 },
0276     { ADAU1373_DRC(0) + 0xb,    0x7a },
0277     { ADAU1373_DRC(0) + 0xc,    0xdf },
0278     { ADAU1373_DRC(0) + 0xd,    0x20 },
0279     { ADAU1373_DRC(0) + 0xe,    0x00 },
0280     { ADAU1373_DRC(0) + 0xf,    0x00 },
0281     { ADAU1373_DRC(1) + 0x0,    0x78 },
0282     { ADAU1373_DRC(1) + 0x1,    0x18 },
0283     { ADAU1373_DRC(1) + 0x2,    0x00 },
0284     { ADAU1373_DRC(1) + 0x3,    0x00 },
0285     { ADAU1373_DRC(1) + 0x4,    0x00 },
0286     { ADAU1373_DRC(1) + 0x5,    0xc0 },
0287     { ADAU1373_DRC(1) + 0x6,    0x00 },
0288     { ADAU1373_DRC(1) + 0x7,    0x00 },
0289     { ADAU1373_DRC(1) + 0x8,    0x00 },
0290     { ADAU1373_DRC(1) + 0x9,    0xc0 },
0291     { ADAU1373_DRC(1) + 0xa,    0x88 },
0292     { ADAU1373_DRC(1) + 0xb,    0x7a },
0293     { ADAU1373_DRC(1) + 0xc,    0xdf },
0294     { ADAU1373_DRC(1) + 0xd,    0x20 },
0295     { ADAU1373_DRC(1) + 0xe,    0x00 },
0296     { ADAU1373_DRC(1) + 0xf,    0x00 },
0297     { ADAU1373_DRC(2) + 0x0,    0x78 },
0298     { ADAU1373_DRC(2) + 0x1,    0x18 },
0299     { ADAU1373_DRC(2) + 0x2,    0x00 },
0300     { ADAU1373_DRC(2) + 0x3,    0x00 },
0301     { ADAU1373_DRC(2) + 0x4,    0x00 },
0302     { ADAU1373_DRC(2) + 0x5,    0xc0 },
0303     { ADAU1373_DRC(2) + 0x6,    0x00 },
0304     { ADAU1373_DRC(2) + 0x7,    0x00 },
0305     { ADAU1373_DRC(2) + 0x8,    0x00 },
0306     { ADAU1373_DRC(2) + 0x9,    0xc0 },
0307     { ADAU1373_DRC(2) + 0xa,    0x88 },
0308     { ADAU1373_DRC(2) + 0xb,    0x7a },
0309     { ADAU1373_DRC(2) + 0xc,    0xdf },
0310     { ADAU1373_DRC(2) + 0xd,    0x20 },
0311     { ADAU1373_DRC(2) + 0xe,    0x00 },
0312     { ADAU1373_DRC(2) + 0xf,    0x00 },
0313     { ADAU1373_3D_CTRL1,        0x00 },
0314     { ADAU1373_3D_CTRL2,        0x00 },
0315     { ADAU1373_FDSP_SEL1,       0x00 },
0316     { ADAU1373_FDSP_SEL2,       0x00 },
0317     { ADAU1373_FDSP_SEL2,       0x00 },
0318     { ADAU1373_FDSP_SEL4,       0x00 },
0319     { ADAU1373_DIGMICCTRL,      0x00 },
0320     { ADAU1373_DIGEN,       0x00 },
0321 };
0322 
0323 static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,
0324     0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
0325     8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
0326     16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
0327     24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
0328 );
0329 
0330 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
0331 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
0332 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
0333 
0334 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
0335 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
0336 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
0337 
0338 static const char *adau1373_fdsp_sel_text[] = {
0339     "None",
0340     "Channel 1",
0341     "Channel 2",
0342     "Channel 3",
0343     "Channel 4",
0344     "Channel 5",
0345 };
0346 
0347 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
0348     ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
0349 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
0350     ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
0351 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
0352     ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
0353 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
0354     ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
0355 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
0356     ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
0357 
0358 static const char *adau1373_hpf_cutoff_text[] = {
0359     "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
0360     "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
0361     "800Hz",
0362 };
0363 
0364 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
0365     ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
0366 
0367 static const char *adau1373_bass_lpf_cutoff_text[] = {
0368     "801Hz", "1001Hz",
0369 };
0370 
0371 static const char *adau1373_bass_clip_level_text[] = {
0372     "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
0373 };
0374 
0375 static const unsigned int adau1373_bass_clip_level_values[] = {
0376     1, 2, 3, 4, 5, 6, 7,
0377 };
0378 
0379 static const char *adau1373_bass_hpf_cutoff_text[] = {
0380     "158Hz", "232Hz", "347Hz", "520Hz",
0381 };
0382 
0383 static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,
0384     0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
0385     3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
0386     5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
0387 );
0388 
0389 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
0390     ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
0391 
0392 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
0393     ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
0394     adau1373_bass_clip_level_values);
0395 
0396 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
0397     ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
0398 
0399 static const char *adau1373_3d_level_text[] = {
0400     "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
0401     "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
0402     "80%", "86.67", "99.33%", "100%"
0403 };
0404 
0405 static const char *adau1373_3d_cutoff_text[] = {
0406     "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
0407     "0.16875 fs", "0.27083 fs"
0408 };
0409 
0410 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
0411     ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
0412 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
0413     ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
0414 
0415 static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,
0416     0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
0417     1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
0418 );
0419 
0420 static const char *adau1373_lr_mux_text[] = {
0421     "Mute",
0422     "Right Channel (L+R)",
0423     "Left Channel (L+R)",
0424     "Stereo",
0425 };
0426 
0427 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
0428     ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
0429 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
0430     ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
0431 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
0432     ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
0433 
0434 static const struct snd_kcontrol_new adau1373_controls[] = {
0435     SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
0436         ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
0437     SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
0438         ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
0439     SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
0440         ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
0441 
0442     SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
0443         ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
0444     SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
0445         ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
0446 
0447     SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
0448         ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
0449     SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
0450         ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
0451     SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
0452         ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
0453 
0454     SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
0455         ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
0456     SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
0457         ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
0458 
0459     SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
0460         ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
0461     SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
0462         ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
0463     SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
0464         ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
0465 
0466     SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
0467         ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
0468     SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
0469         ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
0470     SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
0471         ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
0472     SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
0473         ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
0474 
0475     SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
0476         adau1373_ep_tlv),
0477 
0478     SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
0479         1, 0, adau1373_gain_boost_tlv),
0480     SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
0481         1, 0, adau1373_gain_boost_tlv),
0482     SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
0483         1, 0, adau1373_gain_boost_tlv),
0484     SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
0485         1, 0, adau1373_gain_boost_tlv),
0486     SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
0487         1, 0, adau1373_gain_boost_tlv),
0488     SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
0489         1, 0, adau1373_gain_boost_tlv),
0490     SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
0491         1, 0, adau1373_gain_boost_tlv),
0492     SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
0493         1, 0, adau1373_gain_boost_tlv),
0494     SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
0495         1, 0, adau1373_gain_boost_tlv),
0496     SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
0497         1, 0, adau1373_gain_boost_tlv),
0498 
0499     SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
0500         1, 0, adau1373_input_boost_tlv),
0501     SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
0502         1, 0, adau1373_input_boost_tlv),
0503     SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
0504         1, 0, adau1373_input_boost_tlv),
0505     SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
0506         1, 0, adau1373_input_boost_tlv),
0507 
0508     SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
0509         1, 0, adau1373_speaker_boost_tlv),
0510 
0511     SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
0512     SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
0513 
0514     SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
0515     SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
0516     SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
0517 
0518     SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
0519     SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
0520     SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
0521     SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
0522     SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
0523         adau1373_bass_tlv),
0524     SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
0525 
0526     SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
0527     SOC_ENUM("3D Level", adau1373_3d_level_enum),
0528     SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
0529     SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
0530         adau1373_3d_tlv),
0531     SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
0532 
0533     SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
0534 };
0535 
0536 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
0537     SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
0538         ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
0539     SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
0540 };
0541 
0542 static const struct snd_kcontrol_new adau1373_drc_controls[] = {
0543     SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
0544     SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
0545     SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
0546 };
0547 
0548 static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
0549     struct snd_kcontrol *kcontrol, int event)
0550 {
0551     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0552     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
0553     unsigned int pll_id = w->name[3] - '1';
0554     unsigned int val;
0555 
0556     if (SND_SOC_DAPM_EVENT_ON(event))
0557         val = ADAU1373_PLL_CTRL6_PLL_EN;
0558     else
0559         val = 0;
0560 
0561     regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
0562         ADAU1373_PLL_CTRL6_PLL_EN, val);
0563 
0564     if (SND_SOC_DAPM_EVENT_ON(event))
0565         mdelay(5);
0566 
0567     return 0;
0568 }
0569 
0570 static const char *adau1373_decimator_text[] = {
0571     "ADC",
0572     "DMIC1",
0573 };
0574 
0575 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
0576     adau1373_decimator_text);
0577 
0578 static const struct snd_kcontrol_new adau1373_decimator_mux =
0579     SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
0580 
0581 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
0582     SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
0583     SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
0584     SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
0585     SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
0586     SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
0587 };
0588 
0589 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
0590     SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
0591     SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
0592     SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
0593     SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
0594     SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
0595 };
0596 
0597 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
0598 const struct snd_kcontrol_new _name[] = { \
0599     SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
0600     SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
0601     SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
0602     SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
0603     SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
0604     SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
0605     SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
0606     SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
0607 }
0608 
0609 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
0610     ADAU1373_LLINE1_MIX);
0611 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
0612     ADAU1373_RLINE1_MIX);
0613 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
0614     ADAU1373_LLINE2_MIX);
0615 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
0616     ADAU1373_RLINE2_MIX);
0617 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
0618     ADAU1373_LSPK_MIX);
0619 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
0620     ADAU1373_RSPK_MIX);
0621 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
0622     ADAU1373_EP_MIX);
0623 
0624 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
0625     SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
0626     SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
0627     SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
0628     SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
0629     SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
0630     SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
0631 };
0632 
0633 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
0634     SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
0635     SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
0636     SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
0637     SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
0638     SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
0639     SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
0640 };
0641 
0642 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
0643 const struct snd_kcontrol_new _name[] = { \
0644     SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
0645     SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
0646     SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
0647     SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
0648     SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
0649     SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
0650     SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
0651 }
0652 
0653 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
0654     ADAU1373_DIN_MIX_CTRL(0));
0655 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
0656     ADAU1373_DIN_MIX_CTRL(1));
0657 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
0658     ADAU1373_DIN_MIX_CTRL(2));
0659 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
0660     ADAU1373_DIN_MIX_CTRL(3));
0661 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
0662     ADAU1373_DIN_MIX_CTRL(4));
0663 
0664 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
0665 const struct snd_kcontrol_new _name[] = { \
0666     SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
0667     SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
0668     SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
0669     SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
0670     SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
0671 }
0672 
0673 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
0674     ADAU1373_DOUT_MIX_CTRL(0));
0675 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
0676     ADAU1373_DOUT_MIX_CTRL(1));
0677 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
0678     ADAU1373_DOUT_MIX_CTRL(2));
0679 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
0680     ADAU1373_DOUT_MIX_CTRL(3));
0681 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
0682     ADAU1373_DOUT_MIX_CTRL(4));
0683 
0684 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
0685     /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
0686      * doesn't seem to be the case. */
0687     SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
0688     SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
0689 
0690     SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
0691     SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
0692 
0693     SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
0694         &adau1373_decimator_mux),
0695 
0696     SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
0697     SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
0698 
0699     SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
0700     SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
0701     SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
0702     SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
0703 
0704     SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
0705     SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
0706     SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
0707     SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
0708 
0709     SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
0710         adau1373_left_adc_mixer_controls),
0711     SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
0712         adau1373_right_adc_mixer_controls),
0713 
0714     SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
0715         adau1373_left_line2_mixer_controls),
0716     SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
0717         adau1373_right_line2_mixer_controls),
0718     SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
0719         adau1373_left_line1_mixer_controls),
0720     SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
0721         adau1373_right_line1_mixer_controls),
0722 
0723     SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
0724         adau1373_ep_mixer_controls),
0725     SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
0726         adau1373_left_spk_mixer_controls),
0727     SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
0728         adau1373_right_spk_mixer_controls),
0729     SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
0730         adau1373_left_hp_mixer_controls),
0731     SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
0732         adau1373_right_hp_mixer_controls),
0733     SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
0734         NULL, 0),
0735 
0736     SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
0737         NULL, 0),
0738     SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
0739         NULL, 0),
0740     SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
0741         NULL, 0),
0742     SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
0743         NULL, 0),
0744     SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
0745         NULL, 0),
0746     SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
0747         NULL, 0),
0748     SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
0749         NULL, 0),
0750     SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
0751         NULL, 0),
0752     SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
0753         NULL, 0),
0754 
0755     SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
0756     SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
0757     SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
0758     SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
0759     SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
0760     SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
0761 
0762     SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
0763         adau1373_dsp_channel1_mixer_controls),
0764     SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
0765         adau1373_dsp_channel2_mixer_controls),
0766     SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
0767         adau1373_dsp_channel3_mixer_controls),
0768     SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
0769         adau1373_dsp_channel4_mixer_controls),
0770     SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
0771         adau1373_dsp_channel5_mixer_controls),
0772 
0773     SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
0774         adau1373_aif1_mixer_controls),
0775     SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
0776         adau1373_aif2_mixer_controls),
0777     SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
0778         adau1373_aif3_mixer_controls),
0779     SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
0780         adau1373_dac1_mixer_controls),
0781     SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
0782         adau1373_dac2_mixer_controls),
0783 
0784     SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
0785     SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
0786     SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
0787     SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
0788     SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
0789 
0790     SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
0791         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0792     SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
0793         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0794     SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
0795     SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
0796 
0797     SND_SOC_DAPM_INPUT("AIN1L"),
0798     SND_SOC_DAPM_INPUT("AIN1R"),
0799     SND_SOC_DAPM_INPUT("AIN2L"),
0800     SND_SOC_DAPM_INPUT("AIN2R"),
0801     SND_SOC_DAPM_INPUT("AIN3L"),
0802     SND_SOC_DAPM_INPUT("AIN3R"),
0803     SND_SOC_DAPM_INPUT("AIN4L"),
0804     SND_SOC_DAPM_INPUT("AIN4R"),
0805 
0806     SND_SOC_DAPM_INPUT("DMIC1DAT"),
0807     SND_SOC_DAPM_INPUT("DMIC2DAT"),
0808 
0809     SND_SOC_DAPM_OUTPUT("LOUT1L"),
0810     SND_SOC_DAPM_OUTPUT("LOUT1R"),
0811     SND_SOC_DAPM_OUTPUT("LOUT2L"),
0812     SND_SOC_DAPM_OUTPUT("LOUT2R"),
0813     SND_SOC_DAPM_OUTPUT("HPL"),
0814     SND_SOC_DAPM_OUTPUT("HPR"),
0815     SND_SOC_DAPM_OUTPUT("SPKL"),
0816     SND_SOC_DAPM_OUTPUT("SPKR"),
0817     SND_SOC_DAPM_OUTPUT("EP"),
0818 };
0819 
0820 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
0821     struct snd_soc_dapm_widget *sink)
0822 {
0823     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0824     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
0825     unsigned int dai;
0826     const char *clk;
0827 
0828     dai = sink->name[3] - '1';
0829 
0830     if (!adau1373->dais[dai].clock_provider)
0831         return 0;
0832 
0833     if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
0834         clk = "SYSCLK1";
0835     else
0836         clk = "SYSCLK2";
0837 
0838     return strcmp(source->name, clk) == 0;
0839 }
0840 
0841 static int adau1373_check_src(struct snd_soc_dapm_widget *source,
0842     struct snd_soc_dapm_widget *sink)
0843 {
0844     struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
0845     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
0846     unsigned int dai;
0847 
0848     dai = sink->name[3] - '1';
0849 
0850     return adau1373->dais[dai].enable_src;
0851 }
0852 
0853 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
0854     { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
0855     { _sink, "DMIC2 Switch", "DMIC2" }, \
0856     { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
0857     { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
0858     { _sink, "AIF1 Switch", "AIF1 IN" }, \
0859     { _sink, "AIF2 Switch", "AIF2 IN" }, \
0860     { _sink, "AIF3 Switch", "AIF3 IN" }
0861 
0862 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
0863     { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
0864     { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
0865     { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
0866     { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
0867     { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
0868 
0869 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
0870     { _sink, "Right DAC2 Switch", "Right DAC2" }, \
0871     { _sink, "Left DAC2 Switch", "Left DAC2" }, \
0872     { _sink, "Right DAC1 Switch", "Right DAC1" }, \
0873     { _sink, "Left DAC1 Switch", "Left DAC1" }, \
0874     { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
0875     { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
0876     { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
0877     { _sink, "Input 4 Bypass Switch", "IN4PGA" }
0878 
0879 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
0880     { _sink, "Right DAC2 Switch", "Right DAC2" }, \
0881     { _sink, "Left DAC2 Switch", "Left DAC2" }, \
0882     { _sink, "Right DAC1 Switch", "Right DAC1" }, \
0883     { _sink, "Left DAC1 Switch", "Left DAC1" }, \
0884     { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
0885     { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
0886     { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
0887     { _sink, "Input 4 Bypass Switch", "IN4PGA" }
0888 
0889 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
0890     { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
0891     { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
0892     { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
0893     { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
0894     { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
0895 
0896     { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
0897     { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
0898     { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
0899     { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
0900     { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
0901 
0902     { "Left ADC", NULL, "Left ADC Mixer" },
0903     { "Right ADC", NULL, "Right ADC Mixer" },
0904 
0905     { "Decimator Mux", "ADC", "Left ADC" },
0906     { "Decimator Mux", "ADC", "Right ADC" },
0907     { "Decimator Mux", "DMIC1", "DMIC1" },
0908 
0909     DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
0910     DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
0911     DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
0912     DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
0913     DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
0914 
0915     DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
0916     DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
0917     DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
0918     DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
0919     DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
0920 
0921     { "AIF1 OUT", NULL, "AIF1 Mixer" },
0922     { "AIF2 OUT", NULL, "AIF2 Mixer" },
0923     { "AIF3 OUT", NULL, "AIF3 Mixer" },
0924     { "Left DAC1", NULL, "DAC1 Mixer" },
0925     { "Right DAC1", NULL, "DAC1 Mixer" },
0926     { "Left DAC2", NULL, "DAC2 Mixer" },
0927     { "Right DAC2", NULL, "DAC2 Mixer" },
0928 
0929     LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
0930     RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
0931     LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
0932     RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
0933     LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
0934     RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
0935 
0936     { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
0937     { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
0938     { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
0939     { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
0940     { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
0941     { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
0942     { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
0943     { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
0944     { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
0945     { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
0946     { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
0947     { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
0948 
0949     { "Left Headphone Mixer", NULL, "Headphone Enable" },
0950     { "Right Headphone Mixer", NULL, "Headphone Enable" },
0951 
0952     { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
0953     { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
0954     { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
0955     { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
0956     { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
0957     { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
0958     { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
0959     { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
0960 
0961     { "LOUT1L", NULL, "Left Lineout1 Mixer" },
0962     { "LOUT1R", NULL, "Right Lineout1 Mixer" },
0963     { "LOUT2L", NULL, "Left Lineout2 Mixer" },
0964     { "LOUT2R", NULL, "Right Lineout2 Mixer" },
0965     { "SPKL", NULL, "Left Speaker Mixer" },
0966     { "SPKR", NULL, "Right Speaker Mixer" },
0967     { "HPL", NULL, "Left Headphone Mixer" },
0968     { "HPR", NULL, "Right Headphone Mixer" },
0969     { "EP", NULL, "Earpiece Mixer" },
0970 
0971     { "IN1PGA", NULL, "AIN1L" },
0972     { "IN2PGA", NULL, "AIN2L" },
0973     { "IN3PGA", NULL, "AIN3L" },
0974     { "IN4PGA", NULL, "AIN4L" },
0975     { "IN1PGA", NULL, "AIN1R" },
0976     { "IN2PGA", NULL, "AIN2R" },
0977     { "IN3PGA", NULL, "AIN3R" },
0978     { "IN4PGA", NULL, "AIN4R" },
0979 
0980     { "SYSCLK1", NULL, "PLL1" },
0981     { "SYSCLK2", NULL, "PLL2" },
0982 
0983     { "Left DAC1", NULL, "SYSCLK1" },
0984     { "Right DAC1", NULL, "SYSCLK1" },
0985     { "Left DAC2", NULL, "SYSCLK1" },
0986     { "Right DAC2", NULL, "SYSCLK1" },
0987     { "Left ADC", NULL, "SYSCLK1" },
0988     { "Right ADC", NULL, "SYSCLK1" },
0989 
0990     { "DSP", NULL, "SYSCLK1" },
0991 
0992     { "AIF1 Mixer", NULL, "DSP" },
0993     { "AIF2 Mixer", NULL, "DSP" },
0994     { "AIF3 Mixer", NULL, "DSP" },
0995     { "DAC1 Mixer", NULL, "DSP" },
0996     { "DAC2 Mixer", NULL, "DSP" },
0997     { "DAC1 Mixer", NULL, "Playback Engine A" },
0998     { "DAC2 Mixer", NULL, "Playback Engine B" },
0999     { "Left ADC Mixer", NULL, "Recording Engine A" },
1000     { "Right ADC Mixer", NULL, "Recording Engine A" },
1001 
1002     { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1003     { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1004     { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1005     { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1006     { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1007     { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1008 
1009     { "AIF1 IN", NULL, "AIF1 CLK" },
1010     { "AIF1 OUT", NULL, "AIF1 CLK" },
1011     { "AIF2 IN", NULL, "AIF2 CLK" },
1012     { "AIF2 OUT", NULL, "AIF2 CLK" },
1013     { "AIF3 IN", NULL, "AIF3 CLK" },
1014     { "AIF3 OUT", NULL, "AIF3 CLK" },
1015     { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
1016     { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
1017     { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
1018     { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
1019     { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
1020     { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
1021 
1022     { "DMIC1", NULL, "DMIC1DAT" },
1023     { "DMIC1", NULL, "SYSCLK1" },
1024     { "DMIC1", NULL, "Recording Engine A" },
1025     { "DMIC2", NULL, "DMIC2DAT" },
1026     { "DMIC2", NULL, "SYSCLK1" },
1027     { "DMIC2", NULL, "Recording Engine B" },
1028 };
1029 
1030 static int adau1373_hw_params(struct snd_pcm_substream *substream,
1031     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1032 {
1033     struct snd_soc_component *component = dai->component;
1034     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1035     struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1036     unsigned int div;
1037     unsigned int freq;
1038     unsigned int ctrl;
1039 
1040     freq = adau1373_dai->sysclk;
1041 
1042     if (freq % params_rate(params) != 0)
1043         return -EINVAL;
1044 
1045     switch (freq / params_rate(params)) {
1046     case 1024: /* sysclk / 256 */
1047         div = 0;
1048         break;
1049     case 1536: /* 2/3 sysclk / 256 */
1050         div = 1;
1051         break;
1052     case 2048: /* 1/2 sysclk / 256 */
1053         div = 2;
1054         break;
1055     case 3072: /* 1/3 sysclk / 256 */
1056         div = 3;
1057         break;
1058     case 4096: /* 1/4 sysclk / 256 */
1059         div = 4;
1060         break;
1061     case 6144: /* 1/6 sysclk / 256 */
1062         div = 5;
1063         break;
1064     case 5632: /* 2/11 sysclk / 256 */
1065         div = 6;
1066         break;
1067     default:
1068         return -EINVAL;
1069     }
1070 
1071     adau1373_dai->enable_src = (div != 0);
1072 
1073     regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1074         ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
1075         (div << 2) | ADAU1373_BCLKDIV_64);
1076 
1077     switch (params_width(params)) {
1078     case 16:
1079         ctrl = ADAU1373_DAI_WLEN_16;
1080         break;
1081     case 20:
1082         ctrl = ADAU1373_DAI_WLEN_20;
1083         break;
1084     case 24:
1085         ctrl = ADAU1373_DAI_WLEN_24;
1086         break;
1087     case 32:
1088         ctrl = ADAU1373_DAI_WLEN_32;
1089         break;
1090     default:
1091         return -EINVAL;
1092     }
1093 
1094     return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1095             ADAU1373_DAI_WLEN_MASK, ctrl);
1096 }
1097 
1098 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1099 {
1100     struct snd_soc_component *component = dai->component;
1101     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1102     struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1103     unsigned int ctrl;
1104 
1105     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1106     case SND_SOC_DAIFMT_CBP_CFP:
1107         ctrl = ADAU1373_DAI_MASTER;
1108         adau1373_dai->clock_provider = true;
1109         break;
1110     case SND_SOC_DAIFMT_CBC_CFC:
1111         ctrl = 0;
1112         adau1373_dai->clock_provider = false;
1113         break;
1114     default:
1115         return -EINVAL;
1116     }
1117 
1118     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1119     case SND_SOC_DAIFMT_I2S:
1120         ctrl |= ADAU1373_DAI_FORMAT_I2S;
1121         break;
1122     case SND_SOC_DAIFMT_LEFT_J:
1123         ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
1124         break;
1125     case SND_SOC_DAIFMT_RIGHT_J:
1126         ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
1127         break;
1128     case SND_SOC_DAIFMT_DSP_B:
1129         ctrl |= ADAU1373_DAI_FORMAT_DSP;
1130         break;
1131     default:
1132         return -EINVAL;
1133     }
1134 
1135     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1136     case SND_SOC_DAIFMT_NB_NF:
1137         break;
1138     case SND_SOC_DAIFMT_IB_NF:
1139         ctrl |= ADAU1373_DAI_INVERT_BCLK;
1140         break;
1141     case SND_SOC_DAIFMT_NB_IF:
1142         ctrl |= ADAU1373_DAI_INVERT_LRCLK;
1143         break;
1144     case SND_SOC_DAIFMT_IB_IF:
1145         ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
1146         break;
1147     default:
1148         return -EINVAL;
1149     }
1150 
1151     regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1152         ~ADAU1373_DAI_WLEN_MASK, ctrl);
1153 
1154     return 0;
1155 }
1156 
1157 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1158     int clk_id, unsigned int freq, int dir)
1159 {
1160     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);
1161     struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1162 
1163     switch (clk_id) {
1164     case ADAU1373_CLK_SRC_PLL1:
1165     case ADAU1373_CLK_SRC_PLL2:
1166         break;
1167     default:
1168         return -EINVAL;
1169     }
1170 
1171     adau1373_dai->sysclk = freq;
1172     adau1373_dai->clk_src = clk_id;
1173 
1174     regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1175         ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1176 
1177     return 0;
1178 }
1179 
1180 static const struct snd_soc_dai_ops adau1373_dai_ops = {
1181     .hw_params  = adau1373_hw_params,
1182     .set_sysclk = adau1373_set_dai_sysclk,
1183     .set_fmt    = adau1373_set_dai_fmt,
1184 };
1185 
1186 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1187     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1188 
1189 static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1190     {
1191         .id = 0,
1192         .name = "adau1373-aif1",
1193         .playback = {
1194             .stream_name = "AIF1 Playback",
1195             .channels_min = 2,
1196             .channels_max = 2,
1197             .rates = SNDRV_PCM_RATE_8000_48000,
1198             .formats = ADAU1373_FORMATS,
1199         },
1200         .capture = {
1201             .stream_name = "AIF1 Capture",
1202             .channels_min = 2,
1203             .channels_max = 2,
1204             .rates = SNDRV_PCM_RATE_8000_48000,
1205             .formats = ADAU1373_FORMATS,
1206         },
1207         .ops = &adau1373_dai_ops,
1208         .symmetric_rate = 1,
1209     },
1210     {
1211         .id = 1,
1212         .name = "adau1373-aif2",
1213         .playback = {
1214             .stream_name = "AIF2 Playback",
1215             .channels_min = 2,
1216             .channels_max = 2,
1217             .rates = SNDRV_PCM_RATE_8000_48000,
1218             .formats = ADAU1373_FORMATS,
1219         },
1220         .capture = {
1221             .stream_name = "AIF2 Capture",
1222             .channels_min = 2,
1223             .channels_max = 2,
1224             .rates = SNDRV_PCM_RATE_8000_48000,
1225             .formats = ADAU1373_FORMATS,
1226         },
1227         .ops = &adau1373_dai_ops,
1228         .symmetric_rate = 1,
1229     },
1230     {
1231         .id = 2,
1232         .name = "adau1373-aif3",
1233         .playback = {
1234             .stream_name = "AIF3 Playback",
1235             .channels_min = 2,
1236             .channels_max = 2,
1237             .rates = SNDRV_PCM_RATE_8000_48000,
1238             .formats = ADAU1373_FORMATS,
1239         },
1240         .capture = {
1241             .stream_name = "AIF3 Capture",
1242             .channels_min = 2,
1243             .channels_max = 2,
1244             .rates = SNDRV_PCM_RATE_8000_48000,
1245             .formats = ADAU1373_FORMATS,
1246         },
1247         .ops = &adau1373_dai_ops,
1248         .symmetric_rate = 1,
1249     },
1250 };
1251 
1252 static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,
1253     int source, unsigned int freq_in, unsigned int freq_out)
1254 {
1255     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1256     unsigned int dpll_div = 0;
1257     uint8_t pll_regs[5];
1258     int ret;
1259 
1260     switch (pll_id) {
1261     case ADAU1373_PLL1:
1262     case ADAU1373_PLL2:
1263         break;
1264     default:
1265         return -EINVAL;
1266     }
1267 
1268     switch (source) {
1269     case ADAU1373_PLL_SRC_BCLK1:
1270     case ADAU1373_PLL_SRC_BCLK2:
1271     case ADAU1373_PLL_SRC_BCLK3:
1272     case ADAU1373_PLL_SRC_LRCLK1:
1273     case ADAU1373_PLL_SRC_LRCLK2:
1274     case ADAU1373_PLL_SRC_LRCLK3:
1275     case ADAU1373_PLL_SRC_MCLK1:
1276     case ADAU1373_PLL_SRC_MCLK2:
1277     case ADAU1373_PLL_SRC_GPIO1:
1278     case ADAU1373_PLL_SRC_GPIO2:
1279     case ADAU1373_PLL_SRC_GPIO3:
1280     case ADAU1373_PLL_SRC_GPIO4:
1281         break;
1282     default:
1283         return -EINVAL;
1284     }
1285 
1286     if (freq_in < 7813 || freq_in > 27000000)
1287         return -EINVAL;
1288 
1289     if (freq_out < 45158000 || freq_out > 49152000)
1290         return -EINVAL;
1291 
1292     /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
1293      * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
1294     while (freq_in < 8000000) {
1295         freq_in *= 2;
1296         dpll_div++;
1297     }
1298 
1299     ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
1300     if (ret)
1301         return -EINVAL;
1302 
1303     if (dpll_div) {
1304         dpll_div = 11 - dpll_div;
1305         regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1306             ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1307     } else {
1308         regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1309             ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1310             ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1311     }
1312 
1313     regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1314         (source << 4) | dpll_div);
1315     regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
1316     regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
1317     regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
1318     regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
1319     regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
1320 
1321     /* Set sysclk to pll_rate / 4 */
1322     regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1323 
1324     return 0;
1325 }
1326 
1327 static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1328     unsigned int nr, uint8_t *drc)
1329 {
1330     unsigned int i;
1331 
1332     for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1333         regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1334 }
1335 
1336 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
1337 {
1338     switch (micbias) {
1339     case ADAU1373_MICBIAS_2_9V:
1340     case ADAU1373_MICBIAS_2_2V:
1341     case ADAU1373_MICBIAS_2_6V:
1342     case ADAU1373_MICBIAS_1_8V:
1343         return true;
1344     default:
1345         break;
1346     }
1347     return false;
1348 }
1349 
1350 static int adau1373_probe(struct snd_soc_component *component)
1351 {
1352     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1353     struct adau1373_platform_data *pdata = component->dev->platform_data;
1354     bool lineout_differential = false;
1355     unsigned int val;
1356     int i;
1357 
1358     if (pdata) {
1359         if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting))
1360             return -EINVAL;
1361 
1362         if (!adau1373_valid_micbias(pdata->micbias1) ||
1363             !adau1373_valid_micbias(pdata->micbias2))
1364             return -EINVAL;
1365 
1366         for (i = 0; i < pdata->num_drc; ++i) {
1367             adau1373_load_drc_settings(adau1373, i,
1368                 pdata->drc_setting[i]);
1369         }
1370 
1371         snd_soc_add_component_controls(component, adau1373_drc_controls,
1372             pdata->num_drc);
1373 
1374         val = 0;
1375         for (i = 0; i < 4; ++i) {
1376             if (pdata->input_differential[i])
1377                 val |= BIT(i);
1378         }
1379         regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1380 
1381         val = 0;
1382         if (pdata->lineout_differential)
1383             val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1384         if (pdata->lineout_ground_sense)
1385             val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1386         regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1387 
1388         lineout_differential = pdata->lineout_differential;
1389 
1390         regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1391             (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1392             (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1393     }
1394 
1395     if (!lineout_differential) {
1396         snd_soc_add_component_controls(component, adau1373_lineout2_controls,
1397             ARRAY_SIZE(adau1373_lineout2_controls));
1398     }
1399 
1400     regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1401         ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1402 
1403     return 0;
1404 }
1405 
1406 static int adau1373_set_bias_level(struct snd_soc_component *component,
1407     enum snd_soc_bias_level level)
1408 {
1409     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1410 
1411     switch (level) {
1412     case SND_SOC_BIAS_ON:
1413         break;
1414     case SND_SOC_BIAS_PREPARE:
1415         break;
1416     case SND_SOC_BIAS_STANDBY:
1417         regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1418             ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1419         break;
1420     case SND_SOC_BIAS_OFF:
1421         regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1422             ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1423         break;
1424     }
1425     return 0;
1426 }
1427 
1428 static int adau1373_resume(struct snd_soc_component *component)
1429 {
1430     struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1431 
1432     regcache_sync(adau1373->regmap);
1433 
1434     return 0;
1435 }
1436 
1437 static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1438 {
1439     switch (reg) {
1440     case ADAU1373_SOFT_RESET:
1441     case ADAU1373_ADC_DAC_STATUS:
1442         return true;
1443     default:
1444         return false;
1445     }
1446 }
1447 
1448 static const struct regmap_config adau1373_regmap_config = {
1449     .val_bits = 8,
1450     .reg_bits = 8,
1451 
1452     .volatile_reg = adau1373_register_volatile,
1453     .max_register = ADAU1373_SOFT_RESET,
1454 
1455     .cache_type = REGCACHE_RBTREE,
1456     .reg_defaults = adau1373_reg_defaults,
1457     .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1458 };
1459 
1460 static const struct snd_soc_component_driver adau1373_component_driver = {
1461     .probe          = adau1373_probe,
1462     .resume         = adau1373_resume,
1463     .set_bias_level     = adau1373_set_bias_level,
1464     .set_pll        = adau1373_set_pll,
1465     .controls       = adau1373_controls,
1466     .num_controls       = ARRAY_SIZE(adau1373_controls),
1467     .dapm_widgets       = adau1373_dapm_widgets,
1468     .num_dapm_widgets   = ARRAY_SIZE(adau1373_dapm_widgets),
1469     .dapm_routes        = adau1373_dapm_routes,
1470     .num_dapm_routes    = ARRAY_SIZE(adau1373_dapm_routes),
1471     .use_pmdown_time    = 1,
1472     .endianness     = 1,
1473 };
1474 
1475 static int adau1373_i2c_probe(struct i2c_client *client)
1476 {
1477     struct adau1373 *adau1373;
1478     int ret;
1479 
1480     adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
1481     if (!adau1373)
1482         return -ENOMEM;
1483 
1484     adau1373->regmap = devm_regmap_init_i2c(client,
1485         &adau1373_regmap_config);
1486     if (IS_ERR(adau1373->regmap))
1487         return PTR_ERR(adau1373->regmap);
1488 
1489     regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
1490 
1491     dev_set_drvdata(&client->dev, adau1373);
1492 
1493     ret = devm_snd_soc_register_component(&client->dev,
1494             &adau1373_component_driver,
1495             adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
1496     return ret;
1497 }
1498 
1499 static const struct i2c_device_id adau1373_i2c_id[] = {
1500     { "adau1373", 0 },
1501     { }
1502 };
1503 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
1504 
1505 static struct i2c_driver adau1373_i2c_driver = {
1506     .driver = {
1507         .name = "adau1373",
1508     },
1509     .probe_new = adau1373_i2c_probe,
1510     .id_table = adau1373_i2c_id,
1511 };
1512 
1513 module_i2c_driver(adau1373_i2c_driver);
1514 
1515 MODULE_DESCRIPTION("ASoC ADAU1373 driver");
1516 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1517 MODULE_LICENSE("GPL");
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