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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices ADAU1372 Audio Codec driver
0004  *
0005  * Copyright 2016 Analog Devices Inc.
0006  * Author: Lars-Peter Clausen <lars@metafoo.de>
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/gcd.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/pm.h>
0016 #include <linux/slab.h>
0017 
0018 #include <sound/core.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/tlv.h>
0022 #include <sound/soc.h>
0023 
0024 #include "adau1372.h"
0025 #include "adau-utils.h"
0026 
0027 struct adau1372 {
0028     struct clk *clk;
0029     struct regmap *regmap;
0030     void (*switch_mode)(struct device *dev);
0031     bool use_pll;
0032     bool enabled;
0033     bool clock_provider;
0034 
0035     struct snd_pcm_hw_constraint_list rate_constraints;
0036     unsigned int slot_width;
0037 
0038     struct clk *mclk;
0039     struct gpio_desc *pd_gpio;
0040     struct device *dev;
0041 };
0042 
0043 #define ADAU1372_REG_CLK_CTRL       0x00
0044 #define ADAU1372_REG_PLL(x)     (0x01 + (x))
0045 #define ADAU1372_REG_DAC_SOURCE     0x11
0046 #define ADAU1372_REG_SOUT_SOURCE_0_1    0x13
0047 #define ADAU1372_REG_SOUT_SOURCE_2_3    0x14
0048 #define ADAU1372_REG_SOUT_SOURCE_4_5    0x15
0049 #define ADAU1372_REG_SOUT_SOURCE_6_7    0x16
0050 #define ADAU1372_REG_ADC_SDATA_CH   0x17
0051 #define ADAU1372_REG_ASRCO_SOURCE_0_1   0x18
0052 #define ADAU1372_REG_ASRCO_SOURCE_2_3   0x19
0053 #define ADAU1372_REG_ASRC_MODE      0x1a
0054 #define ADAU1372_REG_ADC_CTRL0      0x1b
0055 #define ADAU1372_REG_ADC_CTRL1      0x1c
0056 #define ADAU1372_REG_ADC_CTRL2      0x1d
0057 #define ADAU1372_REG_ADC_CTRL3      0x1e
0058 #define ADAU1372_REG_ADC_VOL(x)     (0x1f + (x))
0059 #define ADAU1372_REG_PGA_CTRL(x)    (0x23 + (x))
0060 #define ADAU1372_REG_PGA_BOOST      0x28
0061 #define ADAU1372_REG_MICBIAS        0x2d
0062 #define ADAU1372_REG_DAC_CTRL       0x2e
0063 #define ADAU1372_REG_DAC_VOL(x)     (0x2f + (x))
0064 #define ADAU1372_REG_OP_STAGE_MUTE  0x31
0065 #define ADAU1372_REG_SAI0       0x32
0066 #define ADAU1372_REG_SAI1       0x33
0067 #define ADAU1372_REG_SOUT_CTRL      0x34
0068 #define ADAU1372_REG_MODE_MP(x)     (0x38 + (x))
0069 #define ADAU1372_REG_OP_STAGE_CTRL  0x43
0070 #define ADAU1372_REG_DECIM_PWR      0x44
0071 #define ADAU1372_REG_INTERP_PWR     0x45
0072 #define ADAU1372_REG_BIAS_CTRL0     0x46
0073 #define ADAU1372_REG_BIAS_CTRL1     0x47
0074 
0075 #define ADAU1372_CLK_CTRL_PLL_EN    BIT(7)
0076 #define ADAU1372_CLK_CTRL_XTAL_DIS  BIT(4)
0077 #define ADAU1372_CLK_CTRL_CLKSRC    BIT(3)
0078 #define ADAU1372_CLK_CTRL_CC_MDIV   BIT(1)
0079 #define ADAU1372_CLK_CTRL_MCLK_EN   BIT(0)
0080 
0081 #define ADAU1372_SAI0_DELAY1        (0x0 << 6)
0082 #define ADAU1372_SAI0_DELAY0        (0x1 << 6)
0083 #define ADAU1372_SAI0_DELAY_MASK    (0x3 << 6)
0084 #define ADAU1372_SAI0_SAI_I2S       (0x0 << 4)
0085 #define ADAU1372_SAI0_SAI_TDM2      (0x1 << 4)
0086 #define ADAU1372_SAI0_SAI_TDM4      (0x2 << 4)
0087 #define ADAU1372_SAI0_SAI_TDM8      (0x3 << 4)
0088 #define ADAU1372_SAI0_SAI_MASK      (0x3 << 4)
0089 #define ADAU1372_SAI0_FS_48     0x0
0090 #define ADAU1372_SAI0_FS_8      0x1
0091 #define ADAU1372_SAI0_FS_12     0x2
0092 #define ADAU1372_SAI0_FS_16     0x3
0093 #define ADAU1372_SAI0_FS_24     0x4
0094 #define ADAU1372_SAI0_FS_32     0x5
0095 #define ADAU1372_SAI0_FS_96     0x6
0096 #define ADAU1372_SAI0_FS_192        0x7
0097 #define ADAU1372_SAI0_FS_MASK       0xf
0098 
0099 #define ADAU1372_SAI1_TDM_TS        BIT(7)
0100 #define ADAU1372_SAI1_BCLK_TDMC     BIT(6)
0101 #define ADAU1372_SAI1_LR_MODE       BIT(5)
0102 #define ADAU1372_SAI1_LR_POL        BIT(4)
0103 #define ADAU1372_SAI1_BCLKRATE      BIT(2)
0104 #define ADAU1372_SAI1_BCLKEDGE      BIT(1)
0105 #define ADAU1372_SAI1_MS        BIT(0)
0106 
0107 static const unsigned int adau1372_rates[] = {
0108     [ADAU1372_SAI0_FS_8] = 8000,
0109     [ADAU1372_SAI0_FS_12] = 12000,
0110     [ADAU1372_SAI0_FS_16] = 16000,
0111     [ADAU1372_SAI0_FS_24] = 24000,
0112     [ADAU1372_SAI0_FS_32] = 32000,
0113     [ADAU1372_SAI0_FS_48] = 48000,
0114     [ADAU1372_SAI0_FS_96] = 96000,
0115     [ADAU1372_SAI0_FS_192] = 192000,
0116 };
0117 
0118 /* 8k, 12k, 24k, 48k */
0119 #define ADAU1372_RATE_MASK_TDM8 0x17
0120 /* + 16k, 96k */
0121 #define ADAU1372_RATE_MASK_TDM4_MASTER (ADAU1372_RATE_MASK_TDM8 | 0x48 | 0x20)
0122 /* +32k */
0123 #define ADAU1372_RATE_MASK_TDM4 (ADAU1372_RATE_MASK_TDM4_MASTER | 0x20)
0124 /* + 192k */
0125 #define ADAU1372_RATE_MASK_TDM2 (ADAU1372_RATE_MASK_TDM4 | 0x80)
0126 
0127 static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
0128 static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
0129 static const DECLARE_TLV_DB_SCALE(adau1372_pga_boost_tlv, 0, 1000, 0);
0130 
0131 static const char * const adau1372_bias_text[] = {
0132     "Normal operation", "Extreme power saving", "Enhanced performance",
0133     "Power saving",
0134 };
0135 
0136 static const unsigned int adau1372_bias_adc_values[] = {
0137     0, 2, 3,
0138 };
0139 
0140 static const char * const adau1372_bias_adc_text[] = {
0141     "Normal operation", "Enhanced performance", "Power saving",
0142 };
0143 
0144 static const char * const adau1372_bias_dac_text[] = {
0145     "Normal operation", "Power saving", "Superior performance",
0146     "Enhanced performance",
0147 };
0148 
0149 static SOC_ENUM_SINGLE_DECL(adau1372_bias_hp_enum,
0150     ADAU1372_REG_BIAS_CTRL0, 6, adau1372_bias_text);
0151 static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe0_1_enum,
0152     ADAU1372_REG_BIAS_CTRL0, 4, adau1372_bias_text);
0153 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc2_3_enum,
0154     ADAU1372_REG_BIAS_CTRL0, 2, 0x3, adau1372_bias_adc_text,
0155     adau1372_bias_adc_values);
0156 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc0_1_enum,
0157     ADAU1372_REG_BIAS_CTRL0, 0, 0x3, adau1372_bias_adc_text,
0158     adau1372_bias_adc_values);
0159 static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe2_3_enum,
0160     ADAU1372_REG_BIAS_CTRL1, 4, adau1372_bias_text);
0161 static SOC_ENUM_SINGLE_DECL(adau1372_bias_mic_enum,
0162     ADAU1372_REG_BIAS_CTRL1, 2, adau1372_bias_text);
0163 static SOC_ENUM_SINGLE_DECL(adau1372_bias_dac_enum,
0164     ADAU1372_REG_BIAS_CTRL1, 0, adau1372_bias_dac_text);
0165 
0166 static const char * const adau1372_hpf_text[] = {
0167     "Off",
0168     "1 Hz",
0169     "4 Hz",
0170     "8 Hz",
0171 };
0172 
0173 static SOC_ENUM_SINGLE_DECL(adau1372_hpf0_1_enum, ADAU1372_REG_ADC_CTRL2, 5,
0174                 adau1372_hpf_text);
0175 static SOC_ENUM_SINGLE_DECL(adau1372_hpf2_3_enum, ADAU1372_REG_ADC_CTRL3, 5,
0176                 adau1372_hpf_text);
0177 static const struct snd_kcontrol_new adau1372_controls[] = {
0178     SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
0179                0, 0xff, 1, adau1372_digital_tlv),
0180     SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
0181                0, 0xff, 1, adau1372_digital_tlv),
0182     SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
0183                0, 0xff, 1, adau1372_digital_tlv),
0184     SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
0185                0, 0xff, 1, adau1372_digital_tlv),
0186     SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
0187     SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
0188     SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
0189     SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
0190 
0191     SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
0192     SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
0193 
0194     SOC_SINGLE_TLV("PGA 0 Capture Volume", ADAU1372_REG_PGA_CTRL(0),
0195                0, 0x3f, 0, adau1372_pga_tlv),
0196     SOC_SINGLE_TLV("PGA 1 Capture Volume", ADAU1372_REG_PGA_CTRL(1),
0197                0, 0x3f, 0, adau1372_pga_tlv),
0198     SOC_SINGLE_TLV("PGA 2 Capture Volume", ADAU1372_REG_PGA_CTRL(2),
0199                0, 0x3f, 0, adau1372_pga_tlv),
0200     SOC_SINGLE_TLV("PGA 3 Capture Volume", ADAU1372_REG_PGA_CTRL(3),
0201                0, 0x3f, 0, adau1372_pga_tlv),
0202     SOC_SINGLE_TLV("PGA 0 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
0203                0, 1, 0, adau1372_pga_boost_tlv),
0204     SOC_SINGLE_TLV("PGA 1 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
0205                1, 1, 0, adau1372_pga_boost_tlv),
0206     SOC_SINGLE_TLV("PGA 2 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
0207                2, 1, 0, adau1372_pga_boost_tlv),
0208     SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
0209                3, 1, 0, adau1372_pga_boost_tlv),
0210     SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 1),
0211     SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 1),
0212     SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 1),
0213     SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 1),
0214 
0215     SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
0216                0, 0xff, 1, adau1372_digital_tlv),
0217     SOC_SINGLE_TLV("DAC 1 Playback Volume", ADAU1372_REG_DAC_VOL(1),
0218                0, 0xff, 1, adau1372_digital_tlv),
0219     SOC_SINGLE("DAC 0 Playback Switch", ADAU1372_REG_DAC_CTRL, 3, 1, 1),
0220     SOC_SINGLE("DAC 1 Playback Switch", ADAU1372_REG_DAC_CTRL, 4, 1, 1),
0221 
0222     SOC_ENUM("Headphone Bias", adau1372_bias_hp_enum),
0223     SOC_ENUM("Microphone Bias", adau1372_bias_mic_enum),
0224     SOC_ENUM("AFE 0+1 Bias", adau1372_bias_afe0_1_enum),
0225     SOC_ENUM("AFE 2+3 Bias", adau1372_bias_afe2_3_enum),
0226     SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
0227     SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
0228     SOC_ENUM("DAC 0+1 Bias", adau1372_bias_dac_enum),
0229 };
0230 
0231 static const char * const adau1372_decimator_mux_text[] = {
0232     "ADC",
0233     "DMIC",
0234 };
0235 
0236 static SOC_ENUM_SINGLE_DECL(adau1372_decimator0_1_mux_enum, ADAU1372_REG_ADC_CTRL2,
0237                 2, adau1372_decimator_mux_text);
0238 
0239 static const struct snd_kcontrol_new adau1372_decimator0_1_mux_control =
0240     SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
0241 
0242 static SOC_ENUM_SINGLE_DECL(adau1372_decimator2_3_mux_enum, ADAU1372_REG_ADC_CTRL3,
0243                 2, adau1372_decimator_mux_text);
0244 
0245 static const struct snd_kcontrol_new adau1372_decimator2_3_mux_control =
0246     SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
0247 
0248 static const unsigned int adau1372_asrco_mux_values[] = {
0249     4, 5, 6, 7,
0250 };
0251 
0252 static const char * const adau1372_asrco_mux_text[] = {
0253     "Decimator0",
0254     "Decimator1",
0255     "Decimator2",
0256     "Decimator3",
0257 };
0258 
0259 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco0_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
0260                   0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
0261 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco1_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
0262                   4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
0263 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco2_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
0264                   0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
0265 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco3_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
0266                   4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
0267 
0268 static const struct snd_kcontrol_new adau1372_asrco0_mux_control =
0269     SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
0270 static const struct snd_kcontrol_new adau1372_asrco1_mux_control =
0271     SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
0272 static const struct snd_kcontrol_new adau1372_asrco2_mux_control =
0273     SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
0274 static const struct snd_kcontrol_new adau1372_asrco3_mux_control =
0275     SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
0276 
0277 static const unsigned int adau1372_sout_mux_values[] = {
0278     4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
0279 };
0280 
0281 static const char * const adau1372_sout_mux_text[] = {
0282     "Output ASRC0",
0283     "Output ASRC1",
0284     "Output ASRC2",
0285     "Output ASRC3",
0286     "Serial Input 0",
0287     "Serial Input 1",
0288     "Serial Input 2",
0289     "Serial Input 3",
0290     "Serial Input 4",
0291     "Serial Input 5",
0292     "Serial Input 6",
0293     "Serial Input 7",
0294 };
0295 
0296 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout0_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
0297                   0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0298 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout1_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
0299                   4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0300 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout2_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
0301                   0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0302 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout3_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
0303                   4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0304 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout4_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
0305                   0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0306 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout5_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
0307                   4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0308 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout6_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
0309                   0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0310 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout7_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
0311                   4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
0312 
0313 static const struct snd_kcontrol_new adau1372_sout0_mux_control =
0314     SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
0315 static const struct snd_kcontrol_new adau1372_sout1_mux_control =
0316     SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
0317 static const struct snd_kcontrol_new adau1372_sout2_mux_control =
0318     SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
0319 static const struct snd_kcontrol_new adau1372_sout3_mux_control =
0320     SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
0321 static const struct snd_kcontrol_new adau1372_sout4_mux_control =
0322     SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
0323 static const struct snd_kcontrol_new adau1372_sout5_mux_control =
0324     SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
0325 static const struct snd_kcontrol_new adau1372_sout6_mux_control =
0326     SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
0327 static const struct snd_kcontrol_new adau1372_sout7_mux_control =
0328     SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
0329 
0330 static const char * const adau1372_asrci_mux_text[] = {
0331     "Serial Input 0+1",
0332     "Serial Input 2+3",
0333     "Serial Input 4+5",
0334     "Serial Input 6+7",
0335 };
0336 
0337 static SOC_ENUM_SINGLE_DECL(adau1372_asrci_mux_enum,
0338     ADAU1372_REG_ASRC_MODE, 2, adau1372_asrci_mux_text);
0339 
0340 static const struct snd_kcontrol_new adau1372_asrci_mux_control =
0341     SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
0342 
0343 static const unsigned int adau1372_dac_mux_values[] = {
0344     12, 13
0345 };
0346 
0347 static const char * const adau1372_dac_mux_text[] = {
0348     "Input ASRC0",
0349     "Input ASRC1",
0350 };
0351 
0352 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac0_mux_enum, ADAU1372_REG_DAC_SOURCE,
0353                   0, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
0354 static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac1_mux_enum, ADAU1372_REG_DAC_SOURCE,
0355                   4, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
0356 
0357 static const struct snd_kcontrol_new adau1372_dac0_mux_control =
0358     SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
0359 static const struct snd_kcontrol_new adau1372_dac1_mux_control =
0360     SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
0361 
0362 static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = {
0363     SND_SOC_DAPM_INPUT("AIN0"),
0364     SND_SOC_DAPM_INPUT("AIN1"),
0365     SND_SOC_DAPM_INPUT("AIN2"),
0366     SND_SOC_DAPM_INPUT("AIN3"),
0367     SND_SOC_DAPM_INPUT("DMIC0_1"),
0368     SND_SOC_DAPM_INPUT("DMIC2_3"),
0369 
0370     SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
0371     SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
0372 
0373     SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 0, NULL, 0),
0374     SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 0, NULL, 0),
0375     SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 0, NULL, 0),
0376     SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 0, NULL, 0),
0377     SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
0378     SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
0379     SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
0380     SND_SOC_DAPM_ADC("ADC3", NULL, ADAU1372_REG_ADC_CTRL3, 1, 0),
0381 
0382     SND_SOC_DAPM_SUPPLY("ADC0 Filter", ADAU1372_REG_DECIM_PWR, 0, 0, NULL, 0),
0383     SND_SOC_DAPM_SUPPLY("ADC1 Filter", ADAU1372_REG_DECIM_PWR, 1, 0, NULL, 0),
0384     SND_SOC_DAPM_SUPPLY("ADC2 Filter", ADAU1372_REG_DECIM_PWR, 2, 0, NULL, 0),
0385     SND_SOC_DAPM_SUPPLY("ADC3 Filter", ADAU1372_REG_DECIM_PWR, 3, 0, NULL, 0),
0386     SND_SOC_DAPM_SUPPLY("Output ASRC0 Decimator", ADAU1372_REG_DECIM_PWR, 4, 0, NULL, 0),
0387     SND_SOC_DAPM_SUPPLY("Output ASRC1 Decimator", ADAU1372_REG_DECIM_PWR, 5, 0, NULL, 0),
0388     SND_SOC_DAPM_SUPPLY("Output ASRC2 Decimator", ADAU1372_REG_DECIM_PWR, 6, 0, NULL, 0),
0389     SND_SOC_DAPM_SUPPLY("Output ASRC3 Decimator", ADAU1372_REG_DECIM_PWR, 7, 0, NULL, 0),
0390 
0391     SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
0392     SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
0393     SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
0394     SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
0395 
0396     SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
0397     SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
0398     SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
0399     SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
0400     SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
0401              &adau1372_sout0_mux_control),
0402     SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
0403              &adau1372_sout1_mux_control),
0404     SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
0405              &adau1372_sout2_mux_control),
0406     SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
0407              &adau1372_sout3_mux_control),
0408     SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
0409              &adau1372_sout4_mux_control),
0410     SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
0411              &adau1372_sout5_mux_control),
0412     SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
0413              &adau1372_sout6_mux_control),
0414     SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
0415              &adau1372_sout7_mux_control),
0416 
0417     SND_SOC_DAPM_AIF_IN("Serial Input 0", NULL, 0, SND_SOC_NOPM, 0, 0),
0418     SND_SOC_DAPM_AIF_IN("Serial Input 1", NULL, 1, SND_SOC_NOPM, 0, 0),
0419     SND_SOC_DAPM_AIF_IN("Serial Input 2", NULL, 2, SND_SOC_NOPM, 0, 0),
0420     SND_SOC_DAPM_AIF_IN("Serial Input 3", NULL, 3, SND_SOC_NOPM, 0, 0),
0421     SND_SOC_DAPM_AIF_IN("Serial Input 4", NULL, 4, SND_SOC_NOPM, 0, 0),
0422     SND_SOC_DAPM_AIF_IN("Serial Input 5", NULL, 5, SND_SOC_NOPM, 0, 0),
0423     SND_SOC_DAPM_AIF_IN("Serial Input 6", NULL, 6, SND_SOC_NOPM, 0, 0),
0424     SND_SOC_DAPM_AIF_IN("Serial Input 7", NULL, 7, SND_SOC_NOPM, 0, 0),
0425 
0426     SND_SOC_DAPM_AIF_OUT("Serial Output 0", NULL, 0, SND_SOC_NOPM, 0, 0),
0427     SND_SOC_DAPM_AIF_OUT("Serial Output 1", NULL, 1, SND_SOC_NOPM, 0, 0),
0428     SND_SOC_DAPM_AIF_OUT("Serial Output 2", NULL, 2, SND_SOC_NOPM, 0, 0),
0429     SND_SOC_DAPM_AIF_OUT("Serial Output 3", NULL, 3, SND_SOC_NOPM, 0, 0),
0430     SND_SOC_DAPM_AIF_OUT("Serial Output 4", NULL, 4, SND_SOC_NOPM, 0, 0),
0431     SND_SOC_DAPM_AIF_OUT("Serial Output 5", NULL, 5, SND_SOC_NOPM, 0, 0),
0432     SND_SOC_DAPM_AIF_OUT("Serial Output 6", NULL, 6, SND_SOC_NOPM, 0, 0),
0433     SND_SOC_DAPM_AIF_OUT("Serial Output 7", NULL, 7, SND_SOC_NOPM, 0, 0),
0434 
0435     SND_SOC_DAPM_SUPPLY("Output ASRC Supply", ADAU1372_REG_ASRC_MODE, 1, 0, NULL, 0),
0436     SND_SOC_DAPM_SUPPLY("Input ASRC Supply", ADAU1372_REG_ASRC_MODE, 0, 0, NULL, 0),
0437 
0438     SND_SOC_DAPM_SUPPLY("DAC1 Modulator", ADAU1372_REG_INTERP_PWR, 3, 0, NULL, 0),
0439     SND_SOC_DAPM_SUPPLY("DAC0 Modulator", ADAU1372_REG_INTERP_PWR, 2, 0, NULL, 0),
0440     SND_SOC_DAPM_SUPPLY("Input ASRC1 Interpolator", ADAU1372_REG_INTERP_PWR, 1, 0, NULL, 0),
0441     SND_SOC_DAPM_SUPPLY("Input ASRC0 Interpolator", ADAU1372_REG_INTERP_PWR, 0, 0, NULL, 0),
0442 
0443     SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
0444     SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
0445 
0446     SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
0447     SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
0448 
0449     SND_SOC_DAPM_DAC("DAC0", NULL, ADAU1372_REG_DAC_CTRL, 0, 0),
0450     SND_SOC_DAPM_DAC("DAC1", NULL, ADAU1372_REG_DAC_CTRL, 1, 0),
0451 
0452     SND_SOC_DAPM_OUT_DRV("OP_STAGE_LP", ADAU1372_REG_OP_STAGE_CTRL, 0, 1, NULL, 0),
0453     SND_SOC_DAPM_OUT_DRV("OP_STAGE_LN", ADAU1372_REG_OP_STAGE_CTRL, 1, 1, NULL, 0),
0454     SND_SOC_DAPM_OUT_DRV("OP_STAGE_RP", ADAU1372_REG_OP_STAGE_CTRL, 2, 1, NULL, 0),
0455     SND_SOC_DAPM_OUT_DRV("OP_STAGE_RN", ADAU1372_REG_OP_STAGE_CTRL, 3, 1, NULL, 0),
0456 
0457     SND_SOC_DAPM_OUTPUT("HPOUTL"),
0458     SND_SOC_DAPM_OUTPUT("HPOUTR"),
0459 };
0460 
0461 #define ADAU1372_SOUT_ROUTES(x) \
0462     { "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
0463     { "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
0464     { "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
0465     { "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
0466     { "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
0467     { "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
0468     { "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
0469     { "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
0470     { "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
0471     { "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
0472     { "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
0473     { "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
0474     { "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
0475     { "Capture", NULL, "Serial Output " #x }
0476 
0477 #define ADAU1372_ASRCO_ROUTES(x) \
0478     { "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
0479     { "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
0480     { "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
0481     { "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
0482 
0483 static const struct snd_soc_dapm_route adau1372_dapm_routes[] = {
0484     { "PGA0", NULL, "AIN0" },
0485     { "PGA1", NULL, "AIN1" },
0486     { "PGA2", NULL, "AIN2" },
0487     { "PGA3", NULL, "AIN3" },
0488 
0489     { "ADC0", NULL, "PGA0" },
0490     { "ADC1", NULL, "PGA1" },
0491     { "ADC2", NULL, "PGA2" },
0492     { "ADC3", NULL, "PGA3" },
0493 
0494     { "Decimator0 Mux", "ADC", "ADC0" },
0495     { "Decimator1 Mux", "ADC", "ADC1" },
0496     { "Decimator2 Mux", "ADC", "ADC2" },
0497     { "Decimator3 Mux", "ADC", "ADC3" },
0498 
0499     { "Decimator0 Mux", "DMIC", "DMIC0_1" },
0500     { "Decimator1 Mux", "DMIC", "DMIC0_1" },
0501     { "Decimator2 Mux", "DMIC", "DMIC2_3" },
0502     { "Decimator3 Mux", "DMIC", "DMIC2_3" },
0503 
0504     { "Decimator0 Mux", NULL, "ADC0 Filter" },
0505     { "Decimator1 Mux", NULL, "ADC1 Filter" },
0506     { "Decimator2 Mux", NULL, "ADC2 Filter" },
0507     { "Decimator3 Mux", NULL, "ADC3 Filter" },
0508 
0509     { "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
0510     { "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
0511     { "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
0512     { "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
0513     { "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
0514     { "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
0515     { "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
0516     { "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
0517 
0518     ADAU1372_ASRCO_ROUTES(0),
0519     ADAU1372_ASRCO_ROUTES(1),
0520     ADAU1372_ASRCO_ROUTES(2),
0521     ADAU1372_ASRCO_ROUTES(3),
0522 
0523     ADAU1372_SOUT_ROUTES(0),
0524     ADAU1372_SOUT_ROUTES(1),
0525     ADAU1372_SOUT_ROUTES(2),
0526     ADAU1372_SOUT_ROUTES(3),
0527     ADAU1372_SOUT_ROUTES(4),
0528     ADAU1372_SOUT_ROUTES(5),
0529     ADAU1372_SOUT_ROUTES(6),
0530     ADAU1372_SOUT_ROUTES(7),
0531 
0532     { "Serial Input 0", NULL, "Playback" },
0533     { "Serial Input 1", NULL, "Playback" },
0534     { "Serial Input 2", NULL, "Playback" },
0535     { "Serial Input 3", NULL, "Playback" },
0536     { "Serial Input 4", NULL, "Playback" },
0537     { "Serial Input 5", NULL, "Playback" },
0538     { "Serial Input 6", NULL, "Playback" },
0539     { "Serial Input 7", NULL, "Playback" },
0540 
0541     { "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
0542     { "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
0543     { "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
0544     { "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
0545     { "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
0546     { "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
0547     { "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
0548     { "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
0549     { "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
0550     { "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
0551     { "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
0552     { "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
0553 
0554     { "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
0555     { "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
0556     { "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
0557     { "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
0558 
0559     { "DAC0", NULL, "DAC 0 Mux" },
0560     { "DAC1", NULL, "DAC 1 Mux" },
0561     { "DAC0", NULL, "DAC0 Modulator" },
0562     { "DAC1", NULL, "DAC1 Modulator" },
0563 
0564     { "OP_STAGE_LP", NULL, "DAC0" },
0565     { "OP_STAGE_LN", NULL, "DAC0" },
0566     { "OP_STAGE_RP", NULL, "DAC1" },
0567     { "OP_STAGE_RN", NULL, "DAC1" },
0568 
0569     { "HPOUTL", NULL, "OP_STAGE_LP" },
0570     { "HPOUTL", NULL, "OP_STAGE_LN" },
0571     { "HPOUTR", NULL, "OP_STAGE_RP" },
0572     { "HPOUTR", NULL, "OP_STAGE_RN" },
0573 };
0574 
0575 static int adau1372_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0576 {
0577     struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
0578     unsigned int sai0 = 0, sai1 = 0;
0579     bool invert_lrclk = false;
0580 
0581     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0582     case SND_SOC_DAIFMT_CBP_CFP:
0583         adau1372->clock_provider = true;
0584         sai1 |= ADAU1372_SAI1_MS;
0585         break;
0586     case SND_SOC_DAIFMT_CBC_CFC:
0587         adau1372->clock_provider = false;
0588         break;
0589     default:
0590         return -EINVAL;
0591     }
0592 
0593     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0594     case SND_SOC_DAIFMT_NB_NF:
0595         invert_lrclk = false;
0596         break;
0597     case SND_SOC_DAIFMT_NB_IF:
0598         invert_lrclk = true;
0599         break;
0600     case SND_SOC_DAIFMT_IB_NF:
0601         invert_lrclk = false;
0602         sai1 |= ADAU1372_SAI1_BCLKEDGE;
0603         break;
0604     case SND_SOC_DAIFMT_IB_IF:
0605         invert_lrclk = true;
0606         sai1 |= ADAU1372_SAI1_BCLKEDGE;
0607         break;
0608     }
0609 
0610     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0611     case SND_SOC_DAIFMT_I2S:
0612         sai0 |= ADAU1372_SAI0_DELAY1;
0613         break;
0614     case SND_SOC_DAIFMT_LEFT_J:
0615         sai0 |= ADAU1372_SAI0_DELAY0;
0616         invert_lrclk = !invert_lrclk;
0617         break;
0618     case SND_SOC_DAIFMT_DSP_A:
0619         sai0 |= ADAU1372_SAI0_DELAY1;
0620         sai1 |= ADAU1372_SAI1_LR_MODE;
0621         break;
0622     case SND_SOC_DAIFMT_DSP_B:
0623         sai0 |= ADAU1372_SAI0_DELAY0;
0624         sai1 |= ADAU1372_SAI1_LR_MODE;
0625         break;
0626     }
0627 
0628     if (invert_lrclk)
0629         sai1 |= ADAU1372_SAI1_LR_POL;
0630 
0631     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
0632     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
0633                ADAU1372_SAI1_MS | ADAU1372_SAI1_BCLKEDGE |
0634                ADAU1372_SAI1_LR_MODE | ADAU1372_SAI1_LR_POL, sai1);
0635 
0636     return 0;
0637 }
0638 
0639 static int adau1372_hw_params(struct snd_pcm_substream *substream,
0640                   struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0641 {
0642     struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
0643     unsigned int rate = params_rate(params);
0644     unsigned int slot_width;
0645     unsigned int sai0, sai1;
0646     unsigned int i;
0647 
0648     for (i = 0; i < ARRAY_SIZE(adau1372_rates); i++) {
0649         if (rate == adau1372_rates[i])
0650             break;
0651     }
0652 
0653     if (i == ARRAY_SIZE(adau1372_rates))
0654         return -EINVAL;
0655 
0656     sai0 = i;
0657 
0658     slot_width = adau1372->slot_width;
0659     if (slot_width == 0)
0660         slot_width = params_width(params);
0661 
0662     switch (slot_width) {
0663     case 16:
0664         sai1 = ADAU1372_SAI1_BCLKRATE;
0665         break;
0666     case 32:
0667         sai1 = 0;
0668         break;
0669     default:
0670         return -EINVAL;
0671     }
0672 
0673     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
0674     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
0675 
0676     return 0;
0677 }
0678 
0679 static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
0680                  unsigned int rx_mask, int slots, int width)
0681 {
0682     struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
0683     unsigned int sai0, sai1;
0684 
0685     /* I2S mode */
0686     if (slots == 0) {
0687         /* The other settings dont matter in I2S mode */
0688         regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
0689                    ADAU1372_SAI0_SAI_MASK, ADAU1372_SAI0_SAI_I2S);
0690         adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
0691         adau1372->slot_width = 0;
0692         return 0;
0693     }
0694 
0695     /* We have 8 channels anything outside that is not supported */
0696     if ((tx_mask & ~0xff) != 0 || (rx_mask & ~0xff) != 0)
0697         return -EINVAL;
0698 
0699     switch (width) {
0700     case 16:
0701         sai1 = ADAU1372_SAI1_BCLK_TDMC;
0702         break;
0703     case 32:
0704         sai1 = 0;
0705         break;
0706     default:
0707         return -EINVAL;
0708     }
0709 
0710     switch (slots) {
0711     case 2:
0712         sai0 = ADAU1372_SAI0_SAI_TDM2;
0713         adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
0714         break;
0715     case 4:
0716         sai0 = ADAU1372_SAI0_SAI_TDM4;
0717         if (adau1372->clock_provider)
0718             adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
0719         else
0720             adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
0721         break;
0722     case 8:
0723         sai0 = ADAU1372_SAI0_SAI_TDM8;
0724         adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
0725         break;
0726     default:
0727         return -EINVAL;
0728     }
0729 
0730     adau1372->slot_width = width;
0731 
0732     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
0733     regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
0734 
0735     /* Mask is inverted in hardware */
0736     regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
0737 
0738     return 0;
0739 }
0740 
0741 static int adau1372_set_tristate(struct snd_soc_dai *dai, int tristate)
0742 {
0743     struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
0744     unsigned int sai1;
0745 
0746     if (tristate)
0747         sai1 = ADAU1372_SAI1_TDM_TS;
0748     else
0749         sai1 = 0;
0750 
0751     return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
0752 }
0753 
0754 static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
0755 {
0756     struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
0757 
0758     snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
0759                    &adau1372->rate_constraints);
0760 
0761     return 0;
0762 }
0763 
0764 static void adau1372_enable_pll(struct adau1372 *adau1372)
0765 {
0766     unsigned int val, timeout = 0;
0767     int ret;
0768 
0769     regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
0770                ADAU1372_CLK_CTRL_PLL_EN, ADAU1372_CLK_CTRL_PLL_EN);
0771     do {
0772         /* Takes about 1ms to lock */
0773         usleep_range(1000, 2000);
0774         ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
0775         if (ret)
0776             break;
0777         timeout++;
0778     } while (!(val & 1) && timeout < 3);
0779 
0780     if (ret < 0 || !(val & 1))
0781         dev_err(adau1372->dev, "Failed to lock PLL\n");
0782 }
0783 
0784 static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
0785 {
0786     if (adau1372->enabled == enable)
0787         return;
0788 
0789     if (enable) {
0790         unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN;
0791 
0792         clk_prepare_enable(adau1372->mclk);
0793         if (adau1372->pd_gpio)
0794             gpiod_set_value(adau1372->pd_gpio, 0);
0795 
0796         if (adau1372->switch_mode)
0797             adau1372->switch_mode(adau1372->dev);
0798 
0799         regcache_cache_only(adau1372->regmap, false);
0800 
0801         /*
0802          * Clocks needs to be enabled before any other register can be
0803          * accessed.
0804          */
0805         if (adau1372->use_pll) {
0806             adau1372_enable_pll(adau1372);
0807             clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;
0808         }
0809 
0810         regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
0811                    ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl);
0812         regcache_sync(adau1372->regmap);
0813     } else {
0814         if (adau1372->pd_gpio) {
0815             /*
0816              * This will turn everything off and reset the register
0817              * map. No need to do any register writes to manually
0818              * turn things off.
0819              */
0820             gpiod_set_value(adau1372->pd_gpio, 1);
0821             regcache_mark_dirty(adau1372->regmap);
0822         } else {
0823             regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
0824                        ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_PLL_EN, 0);
0825         }
0826         clk_disable_unprepare(adau1372->mclk);
0827         regcache_cache_only(adau1372->regmap, true);
0828     }
0829 
0830     adau1372->enabled = enable;
0831 }
0832 
0833 static int adau1372_set_bias_level(struct snd_soc_component *component,
0834                    enum snd_soc_bias_level level)
0835 {
0836     struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
0837 
0838     switch (level) {
0839     case SND_SOC_BIAS_ON:
0840         break;
0841     case SND_SOC_BIAS_PREPARE:
0842         break;
0843     case SND_SOC_BIAS_STANDBY:
0844         adau1372_set_power(adau1372, true);
0845         break;
0846     case SND_SOC_BIAS_OFF:
0847         adau1372_set_power(adau1372, false);
0848         break;
0849     }
0850 
0851     return 0;
0852 }
0853 
0854 static const struct snd_soc_component_driver adau1372_driver = {
0855     .set_bias_level = adau1372_set_bias_level,
0856     .controls = adau1372_controls,
0857     .num_controls = ARRAY_SIZE(adau1372_controls),
0858     .dapm_widgets = adau1372_dapm_widgets,
0859     .num_dapm_widgets = ARRAY_SIZE(adau1372_dapm_widgets),
0860     .dapm_routes = adau1372_dapm_routes,
0861     .num_dapm_routes = ARRAY_SIZE(adau1372_dapm_routes),
0862     .endianness = 1,
0863 };
0864 
0865 static const struct snd_soc_dai_ops adau1372_dai_ops = {
0866     .set_fmt = adau1372_set_dai_fmt,
0867     .set_tdm_slot = adau1372_set_tdm_slot,
0868     .set_tristate = adau1372_set_tristate,
0869     .hw_params = adau1372_hw_params,
0870     .startup = adau1372_startup,
0871 };
0872 
0873 #define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
0874 
0875 static struct snd_soc_dai_driver adau1372_dai_driver = {
0876     .name = "adau1372",
0877     .playback = {
0878         .stream_name = "Playback",
0879         .channels_min = 2,
0880         .channels_max = 8,
0881         .rates = SNDRV_PCM_RATE_KNOT,
0882         .formats = ADAU1372_FORMATS,
0883         .sig_bits = 24,
0884     },
0885     .capture = {
0886         .stream_name = "Capture",
0887         .channels_min = 2,
0888         .channels_max = 8,
0889         .rates = SNDRV_PCM_RATE_KNOT,
0890         .formats = ADAU1372_FORMATS,
0891         .sig_bits = 24,
0892     },
0893     .ops = &adau1372_dai_ops,
0894     .symmetric_rate = 1,
0895 };
0896 
0897 static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
0898 {
0899     u8 regs[5];
0900     unsigned int i;
0901     int ret;
0902 
0903     ret = adau_calc_pll_cfg(rate, 49152000, regs);
0904     if (ret < 0)
0905         return ret;
0906 
0907     for (i = 0; i < ARRAY_SIZE(regs); i++)
0908         regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
0909 
0910     return 0;
0911 }
0912 
0913 int adau1372_probe(struct device *dev, struct regmap *regmap,
0914            void (*switch_mode)(struct device *dev))
0915 {
0916     struct adau1372 *adau1372;
0917     unsigned int clk_ctrl;
0918     unsigned long rate;
0919     int ret;
0920 
0921     if (IS_ERR(regmap))
0922         return PTR_ERR(regmap);
0923 
0924     adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
0925     if (!adau1372)
0926         return -ENOMEM;
0927 
0928     adau1372->clk = devm_clk_get(dev, "mclk");
0929     if (IS_ERR(adau1372->clk))
0930         return PTR_ERR(adau1372->clk);
0931 
0932     adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
0933     if (IS_ERR(adau1372->pd_gpio))
0934         return PTR_ERR(adau1372->pd_gpio);
0935 
0936     adau1372->regmap = regmap;
0937     adau1372->switch_mode = switch_mode;
0938     adau1372->dev = dev;
0939     adau1372->rate_constraints.list = adau1372_rates;
0940     adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
0941     adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
0942 
0943     dev_set_drvdata(dev, adau1372);
0944 
0945     /*
0946      * The datasheet says that the internal MCLK always needs to run at
0947      * 12.288MHz. Automatically choose a valid configuration from the
0948      * external clock.
0949      */
0950     rate = clk_get_rate(adau1372->clk);
0951 
0952     switch (rate) {
0953     case 12288000:
0954         clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV;
0955         break;
0956     case 24576000:
0957         clk_ctrl = 0;
0958         break;
0959     default:
0960         clk_ctrl = 0;
0961         ret = adau1372_setup_pll(adau1372, rate);
0962         if (ret < 0)
0963             return ret;
0964         adau1372->use_pll = true;
0965         break;
0966     }
0967 
0968     /*
0969      * Most of the registers are inaccessible unless the internal clock is
0970      * enabled.
0971      */
0972     regcache_cache_only(regmap, true);
0973 
0974     regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl);
0975 
0976     /*
0977      * No pinctrl support yet, put the multi-purpose pins in the most
0978      * sensible mode for general purpose CODEC operation.
0979      */
0980     regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00); /* SDATA OUT */
0981     regmap_write(regmap, ADAU1372_REG_MODE_MP(6), 0x12); /* CLOCKOUT */
0982 
0983     regmap_write(regmap, ADAU1372_REG_OP_STAGE_MUTE, 0x0);
0984 
0985     regmap_write(regmap, 0x7, 0x01); /* CLOCK OUT */
0986 
0987     return  devm_snd_soc_register_component(dev, &adau1372_driver, &adau1372_dai_driver, 1);
0988 }
0989 EXPORT_SYMBOL(adau1372_probe);
0990 
0991 static const struct reg_default adau1372_reg_defaults[] = {
0992     { ADAU1372_REG_CLK_CTRL,        0x00 },
0993     { ADAU1372_REG_PLL(0),          0x00 },
0994     { ADAU1372_REG_PLL(1),          0x00 },
0995     { ADAU1372_REG_PLL(2),          0x00 },
0996     { ADAU1372_REG_PLL(3),          0x00 },
0997     { ADAU1372_REG_PLL(4),          0x00 },
0998     { ADAU1372_REG_PLL(5),          0x00 },
0999     { ADAU1372_REG_DAC_SOURCE,      0x10 },
1000     { ADAU1372_REG_SOUT_SOURCE_0_1,     0x54 },
1001     { ADAU1372_REG_SOUT_SOURCE_2_3,     0x76 },
1002     { ADAU1372_REG_SOUT_SOURCE_4_5,     0x54 },
1003     { ADAU1372_REG_SOUT_SOURCE_6_7,     0x76 },
1004     { ADAU1372_REG_ADC_SDATA_CH,        0x04 },
1005     { ADAU1372_REG_ASRCO_SOURCE_0_1,    0x10 },
1006     { ADAU1372_REG_ASRCO_SOURCE_2_3,    0x32 },
1007     { ADAU1372_REG_ASRC_MODE,       0x00 },
1008     { ADAU1372_REG_ADC_CTRL0,       0x19 },
1009     { ADAU1372_REG_ADC_CTRL1,       0x19 },
1010     { ADAU1372_REG_ADC_CTRL2,       0x00 },
1011     { ADAU1372_REG_ADC_CTRL3,       0x00 },
1012     { ADAU1372_REG_ADC_VOL(0),      0x00 },
1013     { ADAU1372_REG_ADC_VOL(1),      0x00 },
1014     { ADAU1372_REG_ADC_VOL(2),      0x00 },
1015     { ADAU1372_REG_ADC_VOL(3),      0x00 },
1016     { ADAU1372_REG_PGA_CTRL(0),     0x40 },
1017     { ADAU1372_REG_PGA_CTRL(1),     0x40 },
1018     { ADAU1372_REG_PGA_CTRL(2),     0x40 },
1019     { ADAU1372_REG_PGA_CTRL(3),     0x40 },
1020     { ADAU1372_REG_PGA_BOOST,       0x00 },
1021     { ADAU1372_REG_MICBIAS,         0x00 },
1022     { ADAU1372_REG_DAC_CTRL,        0x18 },
1023     { ADAU1372_REG_DAC_VOL(0),      0x00 },
1024     { ADAU1372_REG_DAC_VOL(1),      0x00 },
1025     { ADAU1372_REG_OP_STAGE_MUTE,       0x0f },
1026     { ADAU1372_REG_SAI0,            0x00 },
1027     { ADAU1372_REG_SAI1,            0x00 },
1028     { ADAU1372_REG_SOUT_CTRL,       0x00 },
1029     { ADAU1372_REG_MODE_MP(0),      0x00 },
1030     { ADAU1372_REG_MODE_MP(1),      0x10 },
1031     { ADAU1372_REG_MODE_MP(4),      0x00 },
1032     { ADAU1372_REG_MODE_MP(5),      0x00 },
1033     { ADAU1372_REG_MODE_MP(6),      0x11 },
1034     { ADAU1372_REG_OP_STAGE_CTRL,       0x0f },
1035     { ADAU1372_REG_DECIM_PWR,       0x00 },
1036     { ADAU1372_REG_INTERP_PWR,      0x00 },
1037     { ADAU1372_REG_BIAS_CTRL0,      0x00 },
1038     { ADAU1372_REG_BIAS_CTRL1,      0x00 },
1039 };
1040 
1041 static bool adau1372_volatile_register(struct device *dev, unsigned int reg)
1042 {
1043     if (reg == ADAU1372_REG_PLL(5))
1044         return true;
1045 
1046     return false;
1047 }
1048 
1049 const struct regmap_config adau1372_regmap_config = {
1050     .val_bits = 8,
1051     .reg_bits = 16,
1052     .max_register = 0x4d,
1053 
1054     .reg_defaults = adau1372_reg_defaults,
1055     .num_reg_defaults = ARRAY_SIZE(adau1372_reg_defaults),
1056     .volatile_reg = adau1372_volatile_register,
1057     .cache_type = REGCACHE_RBTREE,
1058 };
1059 EXPORT_SYMBOL_GPL(adau1372_regmap_config);
1060 
1061 MODULE_DESCRIPTION("ASoC ADAU1372 CODEC driver");
1062 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1063 MODULE_LICENSE("GPL v2");
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