soc/cirrus/ep93xx-ac97.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ASoC driver for Cirrus Logic EP93xx AC97 controller.
0004  *
0005  * Copyright (c) 2010 Mika Westerberg
0006  *
0007  * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
0008  */
0009
0010 #include <linux/delay.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017
0018 #include <sound/core.h>
0019 #include <sound/dmaengine_pcm.h>
0020 #include <sound/ac97_codec.h>
0021 #include <sound/soc.h>
0022
0023 #include <linux/platform_data/dma-ep93xx.h>
0024 #include <linux/soc/cirrus/ep93xx.h>
0025
0026 #include "ep93xx-pcm.h"
0027
0028 /*
0029  * Per channel (1-4) registers.
0030  */
0031 #define AC97CH(n)       (((n) - 1) * 0x20)
0032
0033 #define AC97DR(n)       (AC97CH(n) + 0x0000)
0034
0035 #define AC97RXCR(n)     (AC97CH(n) + 0x0004)
0036 #define AC97RXCR_REN        BIT(0)
0037 #define AC97RXCR_RX3        BIT(3)
0038 #define AC97RXCR_RX4        BIT(4)
0039 #define AC97RXCR_CM     BIT(15)
0040
0041 #define AC97TXCR(n)     (AC97CH(n) + 0x0008)
0042 #define AC97TXCR_TEN        BIT(0)
0043 #define AC97TXCR_TX3        BIT(3)
0044 #define AC97TXCR_TX4        BIT(4)
0045 #define AC97TXCR_CM     BIT(15)
0046
0047 #define AC97SR(n)       (AC97CH(n) + 0x000c)
0048 #define AC97SR_TXFE     BIT(1)
0049 #define AC97SR_TXUE     BIT(6)
0050
0051 #define AC97RISR(n)     (AC97CH(n) + 0x0010)
0052 #define AC97ISR(n)      (AC97CH(n) + 0x0014)
0053 #define AC97IE(n)       (AC97CH(n) + 0x0018)
0054
0055 /*
0056  * Global AC97 controller registers.
0057  */
0058 #define AC97S1DATA      0x0080
0059 #define AC97S2DATA      0x0084
0060 #define AC97S12DATA     0x0088
0061
0062 #define AC97RGIS        0x008c
0063 #define AC97GIS         0x0090
0064 #define AC97IM          0x0094
0065 /*
0066  * Common bits for RGIS, GIS and IM registers.
0067  */
0068 #define AC97_SLOT2RXVALID   BIT(1)
0069 #define AC97_CODECREADY     BIT(5)
0070 #define AC97_SLOT2TXCOMPLETE    BIT(6)
0071
0072 #define AC97EOI         0x0098
0073 #define AC97EOI_WINT        BIT(0)
0074 #define AC97EOI_CODECREADY  BIT(1)
0075
0076 #define AC97GCR         0x009c
0077 #define AC97GCR_AC97IFE     BIT(0)
0078
0079 #define AC97RESET       0x00a0
0080 #define AC97RESET_TIMEDRESET    BIT(0)
0081
0082 #define AC97SYNC        0x00a4
0083 #define AC97SYNC_TIMEDSYNC  BIT(0)
0084
0085 #define AC97_TIMEOUT        msecs_to_jiffies(5)
0086
0087 /**
0088  * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
0089  * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
0090  * @dev: pointer to the platform device dev structure
0091  * @regs: mapped AC97 controller registers
0092  * @done: bus ops wait here for an interrupt
0093  */
0094 struct ep93xx_ac97_info {
0095     struct mutex        lock;
0096     struct device       *dev;
0097     void __iomem        *regs;
0098     struct completion   done;
0099     struct snd_dmaengine_dai_dma_data dma_params_rx;
0100     struct snd_dmaengine_dai_dma_data dma_params_tx;
0101 };
0102
0103 /* currently ALSA only supports a single AC97 device */
0104 static struct ep93xx_ac97_info *ep93xx_ac97_info;
0105
0106 static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
0107     .name       = "ac97-pcm-out",
0108     .port       = EP93XX_DMA_AAC1,
0109     .direction  = DMA_MEM_TO_DEV,
0110 };
0111
0112 static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
0113     .name       = "ac97-pcm-in",
0114     .port       = EP93XX_DMA_AAC1,
0115     .direction  = DMA_DEV_TO_MEM,
0116 };
0117
0118 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
0119                         unsigned reg)
0120 {
0121     return __raw_readl(info->regs + reg);
0122 }
0123
0124 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
0125                      unsigned reg, unsigned val)
0126 {
0127     __raw_writel(val, info->regs + reg);
0128 }
0129
0130 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
0131                        unsigned short reg)
0132 {
0133     struct ep93xx_ac97_info *info = ep93xx_ac97_info;
0134     unsigned short val;
0135
0136     mutex_lock(&info->lock);
0137
0138     ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
0139     ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
0140     if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
0141         dev_warn(info->dev, "timeout reading register %x\n", reg);
0142         mutex_unlock(&info->lock);
0143         return -ETIMEDOUT;
0144     }
0145     val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
0146
0147     mutex_unlock(&info->lock);
0148     return val;
0149 }
0150
0151 static void ep93xx_ac97_write(struct snd_ac97 *ac97,
0152                   unsigned short reg,
0153                   unsigned short val)
0154 {
0155     struct ep93xx_ac97_info *info = ep93xx_ac97_info;
0156
0157     mutex_lock(&info->lock);
0158
0159     /*
0160      * Writes to the codec need to be done so that slot 2 is filled in
0161      * before slot 1.
0162      */
0163     ep93xx_ac97_write_reg(info, AC97S2DATA, val);
0164     ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
0165
0166     ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
0167     if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
0168         dev_warn(info->dev, "timeout writing register %x\n", reg);
0169
0170     mutex_unlock(&info->lock);
0171 }
0172
0173 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
0174 {
0175     struct ep93xx_ac97_info *info = ep93xx_ac97_info;
0176
0177     mutex_lock(&info->lock);
0178
0179     /*
0180      * We are assuming that before this functions gets called, the codec
0181      * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
0182      * control the SYNC signal directly via AC97SYNC register. Using
0183      * TIMEDSYNC the controller will keep the SYNC high > 1us.
0184      */
0185     ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
0186     ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
0187     if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
0188         dev_warn(info->dev, "codec warm reset timeout\n");
0189
0190     mutex_unlock(&info->lock);
0191 }
0192
0193 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
0194 {
0195     struct ep93xx_ac97_info *info = ep93xx_ac97_info;
0196
0197     mutex_lock(&info->lock);
0198
0199     /*
0200      * For doing cold reset, we disable the AC97 controller interface, clear
0201      * WINT and CODECREADY bits, and finally enable the interface again.
0202      */
0203     ep93xx_ac97_write_reg(info, AC97GCR, 0);
0204     ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
0205     ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
0206
0207     /*
0208      * Now, assert the reset and wait for the codec to become ready.
0209      */
0210     ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
0211     ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
0212     if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
0213         dev_warn(info->dev, "codec cold reset timeout\n");
0214
0215     /*
0216      * Give the codec some time to come fully out from the reset. This way
0217      * we ensure that the subsequent reads/writes will work.
0218      */
0219     usleep_range(15000, 20000);
0220
0221     mutex_unlock(&info->lock);
0222 }
0223
0224 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
0225 {
0226     struct ep93xx_ac97_info *info = dev_id;
0227     unsigned status, mask;
0228
0229     /*
0230      * Just mask out the interrupt and wake up the waiting thread.
0231      * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
0232      * the waiting thread.
0233      */
0234     status = ep93xx_ac97_read_reg(info, AC97GIS);
0235     mask = ep93xx_ac97_read_reg(info, AC97IM);
0236     mask &= ~status;
0237     ep93xx_ac97_write_reg(info, AC97IM, mask);
0238
0239     complete(&info->done);
0240     return IRQ_HANDLED;
0241 }
0242
0243 static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
0244     .read       = ep93xx_ac97_read,
0245     .write      = ep93xx_ac97_write,
0246     .reset      = ep93xx_ac97_cold_reset,
0247     .warm_reset = ep93xx_ac97_warm_reset,
0248 };
0249
0250 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
0251                    int cmd, struct snd_soc_dai *dai)
0252 {
0253     struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
0254     unsigned v = 0;
0255
0256     switch (cmd) {
0257     case SNDRV_PCM_TRIGGER_START:
0258     case SNDRV_PCM_TRIGGER_RESUME:
0259     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0260         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0261             /*
0262              * Enable compact mode, TX slots 3 & 4, and the TX FIFO
0263              * itself.
0264              */
0265             v |= AC97TXCR_CM;
0266             v |= AC97TXCR_TX3 | AC97TXCR_TX4;
0267             v |= AC97TXCR_TEN;
0268             ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
0269         } else {
0270             /*
0271              * Enable compact mode, RX slots 3 & 4, and the RX FIFO
0272              * itself.
0273              */
0274             v |= AC97RXCR_CM;
0275             v |= AC97RXCR_RX3 | AC97RXCR_RX4;
0276             v |= AC97RXCR_REN;
0277             ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
0278         }
0279         break;
0280
0281     case SNDRV_PCM_TRIGGER_STOP:
0282     case SNDRV_PCM_TRIGGER_SUSPEND:
0283     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0284         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0285             /*
0286              * As per Cirrus EP93xx errata described below:
0287              *
0288              * https://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
0289              *
0290              * we will wait for the TX FIFO to be empty before
0291              * clearing the TEN bit.
0292              */
0293             unsigned long timeout = jiffies + AC97_TIMEOUT;
0294
0295             do {
0296                 v = ep93xx_ac97_read_reg(info, AC97SR(1));
0297                 if (time_after(jiffies, timeout)) {
0298                     dev_warn(info->dev, "TX timeout\n");
0299                     break;
0300                 }
0301             } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
0302
0303             /* disable the TX FIFO */
0304             ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
0305         } else {
0306             /* disable the RX FIFO */
0307             ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
0308         }
0309         break;
0310
0311     default:
0312         dev_warn(info->dev, "unknown command %d\n", cmd);
0313         return -EINVAL;
0314     }
0315
0316     return 0;
0317 }
0318
0319 static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
0320 {
0321     struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
0322
0323     info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
0324     info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;
0325
0326     dai->playback_dma_data = &info->dma_params_tx;
0327     dai->capture_dma_data = &info->dma_params_rx;
0328
0329     return 0;
0330 }
0331
0332 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
0333     .trigger    = ep93xx_ac97_trigger,
0334 };
0335
0336 static struct snd_soc_dai_driver ep93xx_ac97_dai = {
0337     .name       = "ep93xx-ac97",
0338     .id     = 0,
0339     .probe      = ep93xx_ac97_dai_probe,
0340     .playback   = {
0341         .stream_name    = "AC97 Playback",
0342         .channels_min   = 2,
0343         .channels_max   = 2,
0344         .rates      = SNDRV_PCM_RATE_8000_48000,
0345         .formats    = SNDRV_PCM_FMTBIT_S16_LE,
0346     },
0347     .capture    = {
0348         .stream_name    = "AC97 Capture",
0349         .channels_min   = 2,
0350         .channels_max   = 2,
0351         .rates      = SNDRV_PCM_RATE_8000_48000,
0352         .formats    = SNDRV_PCM_FMTBIT_S16_LE,
0353     },
0354     .ops            = &ep93xx_ac97_dai_ops,
0355 };
0356
0357 static const struct snd_soc_component_driver ep93xx_ac97_component = {
0358     .name           = "ep93xx-ac97",
0359     .legacy_dai_naming  = 1,
0360 };
0361
0362 static int ep93xx_ac97_probe(struct platform_device *pdev)
0363 {
0364     struct ep93xx_ac97_info *info;
0365     int irq;
0366     int ret;
0367
0368     info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
0369     if (!info)
0370         return -ENOMEM;
0371
0372     info->regs = devm_platform_ioremap_resource(pdev, 0);
0373     if (IS_ERR(info->regs))
0374         return PTR_ERR(info->regs);
0375
0376     irq = platform_get_irq(pdev, 0);
0377     if (irq <= 0)
0378         return irq < 0 ? irq : -ENODEV;
0379
0380     ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
0381                    IRQF_TRIGGER_HIGH, pdev->name, info);
0382     if (ret)
0383         goto fail;
0384
0385     dev_set_drvdata(&pdev->dev, info);
0386
0387     mutex_init(&info->lock);
0388     init_completion(&info->done);
0389     info->dev = &pdev->dev;
0390
0391     ep93xx_ac97_info = info;
0392     platform_set_drvdata(pdev, info);
0393
0394     ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
0395     if (ret)
0396         goto fail;
0397
0398     ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
0399                      &ep93xx_ac97_dai, 1);
0400     if (ret)
0401         goto fail;
0402
0403     ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
0404     if (ret)
0405         goto fail_unregister;
0406
0407     return 0;
0408
0409 fail_unregister:
0410     snd_soc_unregister_component(&pdev->dev);
0411 fail:
0412     ep93xx_ac97_info = NULL;
0413     snd_soc_set_ac97_ops(NULL);
0414     return ret;
0415 }
0416
0417 static int ep93xx_ac97_remove(struct platform_device *pdev)
0418 {
0419     struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
0420
0421     snd_soc_unregister_component(&pdev->dev);
0422
0423     /* disable the AC97 controller */
0424     ep93xx_ac97_write_reg(info, AC97GCR, 0);
0425
0426     ep93xx_ac97_info = NULL;
0427
0428     snd_soc_set_ac97_ops(NULL);
0429
0430     return 0;
0431 }
0432
0433 static struct platform_driver ep93xx_ac97_driver = {
0434     .probe  = ep93xx_ac97_probe,
0435     .remove = ep93xx_ac97_remove,
0436     .driver = {
0437         .name = "ep93xx-ac97",
0438     },
0439 };
0440
0441 module_platform_driver(ep93xx_ac97_driver);
0442
0443 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
0444 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
0445 MODULE_LICENSE("GPL");
0446 MODULE_ALIAS("platform:ep93xx-ac97");