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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (C) 2014-2015 Broadcom Corporation */
0003 #ifndef __CYGNUS_SSP_H__
0004 #define __CYGNUS_SSP_H__
0005 
0006 #define CYGNUS_TDM_DAI_MAX_SLOTS 16
0007 
0008 #define CYGNUS_MAX_PLAYBACK_PORTS 4
0009 #define CYGNUS_MAX_CAPTURE_PORTS 3
0010 #define CYGNUS_MAX_I2S_PORTS 3
0011 #define CYGNUS_MAX_PORTS  CYGNUS_MAX_PLAYBACK_PORTS
0012 #define CYGNUS_AUIDO_MAX_NUM_CLKS 3
0013 
0014 #define CYGNUS_SSP_FRAMEBITS_DIV 1
0015 
0016 #define CYGNUS_SSPMODE_I2S 0
0017 #define CYGNUS_SSPMODE_TDM 1
0018 #define CYGNUS_SSPMODE_UNKNOWN -1
0019 
0020 #define CYGNUS_SSP_CLKSRC_PLL      0
0021 
0022 /* Max string length of our dt property names */
0023 #define PROP_LEN_MAX 40
0024 
0025 struct ringbuf_regs {
0026     unsigned rdaddr;
0027     unsigned wraddr;
0028     unsigned baseaddr;
0029     unsigned endaddr;
0030     unsigned fmark;   /* freemark for play, fullmark for caputure */
0031     unsigned period_bytes;
0032     unsigned buf_size;
0033 };
0034 
0035 #define RINGBUF_REG_PLAYBACK(num) ((struct ringbuf_regs) { \
0036     .rdaddr = SRC_RBUF_ ##num## _RDADDR_OFFSET, \
0037     .wraddr = SRC_RBUF_ ##num## _WRADDR_OFFSET, \
0038     .baseaddr = SRC_RBUF_ ##num## _BASEADDR_OFFSET, \
0039     .endaddr = SRC_RBUF_ ##num## _ENDADDR_OFFSET, \
0040     .fmark = SRC_RBUF_ ##num## _FREE_MARK_OFFSET, \
0041     .period_bytes = 0, \
0042     .buf_size = 0, \
0043 })
0044 
0045 #define RINGBUF_REG_CAPTURE(num) ((struct ringbuf_regs)  { \
0046     .rdaddr = DST_RBUF_ ##num## _RDADDR_OFFSET, \
0047     .wraddr = DST_RBUF_ ##num## _WRADDR_OFFSET, \
0048     .baseaddr = DST_RBUF_ ##num## _BASEADDR_OFFSET, \
0049     .endaddr = DST_RBUF_ ##num## _ENDADDR_OFFSET, \
0050     .fmark = DST_RBUF_ ##num## _FULL_MARK_OFFSET, \
0051     .period_bytes = 0, \
0052     .buf_size = 0, \
0053 })
0054 
0055 enum cygnus_audio_port_type {
0056     PORT_TDM,
0057     PORT_SPDIF,
0058 };
0059 
0060 struct cygnus_ssp_regs {
0061     u32 i2s_stream_cfg;
0062     u32 i2s_cfg;
0063     u32 i2s_cap_stream_cfg;
0064     u32 i2s_cap_cfg;
0065     u32 i2s_mclk_cfg;
0066 
0067     u32 bf_destch_ctrl;
0068     u32 bf_destch_cfg;
0069     u32 bf_sourcech_ctrl;
0070     u32 bf_sourcech_cfg;
0071     u32 bf_sourcech_grp;
0072 };
0073 
0074 struct cygnus_track_clk {
0075     bool cap_en;
0076     bool play_en;
0077     bool cap_clk_en;
0078     bool play_clk_en;
0079 };
0080 
0081 struct cygnus_aio_port {
0082     int portnum;
0083     int mode;
0084     bool is_slave;
0085     int streams_on;   /* will be 0 if both capture and play are off */
0086     int fsync_width;
0087     int port_type;
0088 
0089     u32 mclk;
0090     u32 lrclk;
0091     u32 bit_per_frame;
0092     u32 pll_clk_num;
0093 
0094     struct cygnus_audio *cygaud;
0095     struct cygnus_ssp_regs regs;
0096 
0097     struct ringbuf_regs play_rb_regs;
0098     struct ringbuf_regs capture_rb_regs;
0099 
0100     struct snd_pcm_substream *play_stream;
0101     struct snd_pcm_substream *capture_stream;
0102 
0103     struct cygnus_track_clk clk_trace;
0104 };
0105 
0106 
0107 struct cygnus_audio {
0108     struct cygnus_aio_port  portinfo[CYGNUS_MAX_PORTS];
0109 
0110     int irq_num;
0111     void __iomem *audio;
0112     struct device *dev;
0113     void __iomem *i2s_in;
0114 
0115     struct clk *audio_clk[CYGNUS_AUIDO_MAX_NUM_CLKS];
0116     int active_ports;
0117     unsigned long vco_rate;
0118 };
0119 
0120 extern int cygnus_ssp_get_mode(struct snd_soc_dai *cpu_dai);
0121 extern int cygnus_ssp_add_pll_tweak_controls(struct snd_soc_pcm_runtime *rtd);
0122 extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai,
0123                         int len);
0124 extern int cygnus_soc_platform_register(struct device *dev,
0125                     struct cygnus_audio *cygaud);
0126 extern int cygnus_soc_platform_unregister(struct device *dev);
0127 extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai,
0128     int len);
0129 #endif