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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 // linux/sound/bcm/bcm63xx-i2s-whistler.c
0003 // BCM63xx whistler i2s driver
0004 // Copyright (c) 2020 Broadcom Corporation
0005 // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
0006 
0007 #include <linux/clk.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/regmap.h>
0012 #include <sound/pcm_params.h>
0013 #include <sound/soc.h>
0014 #include "bcm63xx-i2s.h"
0015 
0016 #define DRV_NAME "brcm-i2s"
0017 
0018 static bool brcm_i2s_wr_reg(struct device *dev, unsigned int reg)
0019 {
0020     switch (reg) {
0021     case I2S_TX_CFG ... I2S_TX_DESC_IFF_LEN:
0022     case I2S_TX_CFG_2 ... I2S_RX_DESC_IFF_LEN:
0023     case I2S_RX_CFG_2 ... I2S_REG_MAX:
0024         return true;
0025     default:
0026         return false;
0027     }
0028 }
0029 
0030 static bool brcm_i2s_rd_reg(struct device *dev, unsigned int reg)
0031 {
0032     switch (reg) {
0033     case I2S_TX_CFG ... I2S_REG_MAX:
0034         return true;
0035     default:
0036         return false;
0037     }
0038 }
0039 
0040 static bool brcm_i2s_volatile_reg(struct device *dev, unsigned int reg)
0041 {
0042     switch (reg) {
0043     case I2S_TX_CFG:
0044     case I2S_TX_IRQ_CTL:
0045     case I2S_TX_DESC_IFF_ADDR:
0046     case I2S_TX_DESC_IFF_LEN:
0047     case I2S_TX_DESC_OFF_ADDR:
0048     case I2S_TX_DESC_OFF_LEN:
0049     case I2S_TX_CFG_2:
0050     case I2S_RX_CFG:
0051     case I2S_RX_IRQ_CTL:
0052     case I2S_RX_DESC_OFF_ADDR:
0053     case I2S_RX_DESC_OFF_LEN:
0054     case I2S_RX_DESC_IFF_LEN:
0055     case I2S_RX_DESC_IFF_ADDR:
0056     case I2S_RX_CFG_2:
0057         return true;
0058     default:
0059         return false;
0060     }
0061 }
0062 
0063 static const struct regmap_config brcm_i2s_regmap_config = {
0064     .reg_bits = 32,
0065     .reg_stride = 4,
0066     .val_bits = 32,
0067     .max_register = I2S_REG_MAX,
0068     .writeable_reg = brcm_i2s_wr_reg,
0069     .readable_reg = brcm_i2s_rd_reg,
0070     .volatile_reg = brcm_i2s_volatile_reg,
0071     .cache_type = REGCACHE_FLAT,
0072 };
0073 
0074 static int bcm63xx_i2s_hw_params(struct snd_pcm_substream *substream,
0075                  struct snd_pcm_hw_params *params,
0076                  struct snd_soc_dai *dai)
0077 {
0078     int ret = 0;
0079     struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
0080 
0081     ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params));
0082     if (ret < 0)
0083         dev_err(i2s_priv->dev,
0084             "Can't set sample rate, err: %d\n", ret);
0085 
0086     return ret;
0087 }
0088 
0089 static int bcm63xx_i2s_startup(struct snd_pcm_substream *substream,
0090                    struct snd_soc_dai *dai)
0091 {
0092     unsigned int slavemode;
0093     struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
0094     struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
0095 
0096     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0097         regmap_update_bits(regmap_i2s, I2S_TX_CFG,
0098                    I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
0099                    I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE,
0100                    I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
0101                    I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE);
0102         regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 0);
0103         regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 0);
0104         regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 1);
0105 
0106         /* TX and RX block each have an independent bit to indicate
0107          * if it is generating the clock for the I2S bus. The bus
0108          * clocks need to be generated from either the TX or RX block,
0109          * but not both
0110          */
0111         regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
0112         if (slavemode & I2S_RX_SLAVE_MODE_MASK)
0113             regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
0114                        I2S_TX_SLAVE_MODE_MASK,
0115                        I2S_TX_MASTER_MODE);
0116         else
0117             regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
0118                        I2S_TX_SLAVE_MODE_MASK,
0119                        I2S_TX_SLAVE_MODE);
0120     } else {
0121         regmap_update_bits(regmap_i2s, I2S_RX_CFG,
0122                    I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
0123                    I2S_RX_CLOCK_ENABLE,
0124                    I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
0125                    I2S_RX_CLOCK_ENABLE);
0126         regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 0);
0127         regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 0);
0128         regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 1);
0129 
0130         regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
0131         if (slavemode & I2S_TX_SLAVE_MODE_MASK)
0132             regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
0133                        I2S_RX_SLAVE_MODE_MASK, 0);
0134         else
0135             regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
0136                        I2S_RX_SLAVE_MODE_MASK,
0137                        I2S_RX_SLAVE_MODE);
0138     }
0139     return 0;
0140 }
0141 
0142 static void bcm63xx_i2s_shutdown(struct snd_pcm_substream *substream,
0143                 struct snd_soc_dai *dai)
0144 {
0145     unsigned int enabled, slavemode;
0146     struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
0147     struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
0148 
0149     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0150         regmap_update_bits(regmap_i2s, I2S_TX_CFG,
0151                    I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
0152                    I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE, 0);
0153         regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 1);
0154         regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 4);
0155         regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 4);
0156 
0157         regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
0158         slavemode = slavemode & I2S_TX_SLAVE_MODE_MASK;
0159         if (!slavemode) {
0160             regmap_read(regmap_i2s, I2S_RX_CFG, &enabled);
0161             enabled = enabled & I2S_RX_ENABLE_MASK;
0162             if (enabled)
0163                 regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
0164                            I2S_RX_SLAVE_MODE_MASK,
0165                            I2S_RX_MASTER_MODE);
0166         }
0167         regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
0168                    I2S_TX_SLAVE_MODE_MASK,
0169                    I2S_TX_SLAVE_MODE);
0170     } else {
0171         regmap_update_bits(regmap_i2s, I2S_RX_CFG,
0172                    I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
0173                    I2S_RX_CLOCK_ENABLE, 0);
0174         regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 1);
0175         regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 4);
0176         regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 4);
0177 
0178         regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
0179         slavemode = slavemode & I2S_RX_SLAVE_MODE_MASK;
0180         if (!slavemode) {
0181             regmap_read(regmap_i2s, I2S_TX_CFG, &enabled);
0182             enabled = enabled & I2S_TX_ENABLE_MASK;
0183             if (enabled)
0184                 regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
0185                            I2S_TX_SLAVE_MODE_MASK,
0186                            I2S_TX_MASTER_MODE);
0187         }
0188 
0189         regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
0190                    I2S_RX_SLAVE_MODE_MASK, I2S_RX_SLAVE_MODE);
0191     }
0192 }
0193 
0194 static const struct snd_soc_dai_ops bcm63xx_i2s_dai_ops = {
0195     .startup = bcm63xx_i2s_startup,
0196     .shutdown = bcm63xx_i2s_shutdown,
0197     .hw_params = bcm63xx_i2s_hw_params,
0198 };
0199 
0200 static struct snd_soc_dai_driver bcm63xx_i2s_dai = {
0201     .name = DRV_NAME,
0202     .playback = {
0203         .channels_min = 2,
0204         .channels_max = 2,
0205         .rates = SNDRV_PCM_RATE_8000_192000,
0206         .formats = SNDRV_PCM_FMTBIT_S32_LE,
0207     },
0208     .capture = {
0209         .channels_min = 2,
0210         .channels_max = 2,
0211         .rates = SNDRV_PCM_RATE_8000_192000,
0212         .formats = SNDRV_PCM_FMTBIT_S32_LE,
0213     },
0214     .ops = &bcm63xx_i2s_dai_ops,
0215     .symmetric_rate = 1,
0216     .symmetric_channels = 1,
0217 };
0218 
0219 static const struct snd_soc_component_driver bcm63xx_i2s_component = {
0220     .name = "bcm63xx",
0221     .legacy_dai_naming = 1,
0222 };
0223 
0224 static int bcm63xx_i2s_dev_probe(struct platform_device *pdev)
0225 {
0226     int ret = 0;
0227     void __iomem *regs;
0228     struct resource *r_mem, *region;
0229     struct bcm_i2s_priv *i2s_priv;
0230     struct regmap *regmap_i2s;
0231     struct clk *i2s_clk;
0232 
0233     i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);
0234     if (!i2s_priv)
0235         return -ENOMEM;
0236 
0237     i2s_clk = devm_clk_get(&pdev->dev, "i2sclk");
0238     if (IS_ERR(i2s_clk)) {
0239         dev_err(&pdev->dev, "%s: cannot get a brcm clock: %ld\n",
0240                     __func__, PTR_ERR(i2s_clk));
0241         return PTR_ERR(i2s_clk);
0242     }
0243 
0244     r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0245     if (!r_mem) {
0246         dev_err(&pdev->dev, "Unable to get register resource.\n");
0247         return -ENODEV;
0248     }
0249 
0250     region = devm_request_mem_region(&pdev->dev, r_mem->start,
0251                     resource_size(r_mem), DRV_NAME);
0252     if (!region) {
0253         dev_err(&pdev->dev, "Memory region already claimed\n");
0254         return -EBUSY;
0255     }
0256 
0257     regs = devm_ioremap_resource(&pdev->dev, r_mem);
0258     if (IS_ERR(regs)) {
0259         ret = PTR_ERR(regs);
0260         return ret;
0261     }
0262 
0263     regmap_i2s = devm_regmap_init_mmio(&pdev->dev,
0264                     regs, &brcm_i2s_regmap_config);
0265     if (IS_ERR(regmap_i2s))
0266         return PTR_ERR(regmap_i2s);
0267 
0268     regmap_update_bits(regmap_i2s, I2S_MISC_CFG,
0269                I2S_PAD_LVL_LOOP_DIS_MASK,
0270                I2S_PAD_LVL_LOOP_DIS_ENABLE);
0271 
0272     ret = devm_snd_soc_register_component(&pdev->dev,
0273                           &bcm63xx_i2s_component,
0274                           &bcm63xx_i2s_dai, 1);
0275     if (ret) {
0276         dev_err(&pdev->dev, "failed to register the dai\n");
0277         return ret;
0278     }
0279 
0280     i2s_priv->dev = &pdev->dev;
0281     i2s_priv->i2s_clk = i2s_clk;
0282     i2s_priv->regmap_i2s = regmap_i2s;
0283     dev_set_drvdata(&pdev->dev, i2s_priv);
0284 
0285     ret = bcm63xx_soc_platform_probe(pdev, i2s_priv);
0286     if (ret)
0287         dev_err(&pdev->dev, "failed to register the pcm\n");
0288 
0289     return ret;
0290 }
0291 
0292 static int bcm63xx_i2s_dev_remove(struct platform_device *pdev)
0293 {
0294     bcm63xx_soc_platform_remove(pdev);
0295     return 0;
0296 }
0297 
0298 #ifdef CONFIG_OF
0299 static const struct of_device_id snd_soc_bcm_audio_match[] = {
0300     {.compatible = "brcm,bcm63xx-i2s"},
0301     { }
0302 };
0303 #endif
0304 
0305 static struct platform_driver bcm63xx_i2s_driver = {
0306     .driver = {
0307         .name = DRV_NAME,
0308         .of_match_table = of_match_ptr(snd_soc_bcm_audio_match),
0309     },
0310     .probe = bcm63xx_i2s_dev_probe,
0311     .remove = bcm63xx_i2s_dev_remove,
0312 };
0313 
0314 module_platform_driver(bcm63xx_i2s_driver);
0315 
0316 MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");
0317 MODULE_DESCRIPTION("Broadcom DSL XPON ASOC I2S Interface");
0318 MODULE_LICENSE("GPL v2");
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