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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
0004  *
0005  * Author:  Florian Meier <florian.meier@koalo.de>
0006  *      Copyright 2013
0007  *
0008  * Based on
0009  *  Raspberry Pi PCM I2S ALSA Driver
0010  *  Copyright (c) by Phil Poole 2013
0011  *
0012  *  ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
0013  *      Vladimir Barinov, <vbarinov@embeddedalley.com>
0014  *  Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
0015  *
0016  *  OMAP ALSA SoC DAI driver using McBSP port
0017  *  Copyright (C) 2008 Nokia Corporation
0018  *  Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
0019  *       Peter Ujfalusi <peter.ujfalusi@ti.com>
0020  *
0021  *  Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
0022  *  Author: Timur Tabi <timur@freescale.com>
0023  *  Copyright 2007-2010 Freescale Semiconductor, Inc.
0024  */
0025 
0026 #include <linux/bitops.h>
0027 #include <linux/clk.h>
0028 #include <linux/delay.h>
0029 #include <linux/device.h>
0030 #include <linux/init.h>
0031 #include <linux/io.h>
0032 #include <linux/module.h>
0033 #include <linux/of_address.h>
0034 #include <linux/slab.h>
0035 
0036 #include <sound/core.h>
0037 #include <sound/dmaengine_pcm.h>
0038 #include <sound/initval.h>
0039 #include <sound/pcm.h>
0040 #include <sound/pcm_params.h>
0041 #include <sound/soc.h>
0042 
0043 /* I2S registers */
0044 #define BCM2835_I2S_CS_A_REG        0x00
0045 #define BCM2835_I2S_FIFO_A_REG      0x04
0046 #define BCM2835_I2S_MODE_A_REG      0x08
0047 #define BCM2835_I2S_RXC_A_REG       0x0c
0048 #define BCM2835_I2S_TXC_A_REG       0x10
0049 #define BCM2835_I2S_DREQ_A_REG      0x14
0050 #define BCM2835_I2S_INTEN_A_REG 0x18
0051 #define BCM2835_I2S_INTSTC_A_REG    0x1c
0052 #define BCM2835_I2S_GRAY_REG        0x20
0053 
0054 /* I2S register settings */
0055 #define BCM2835_I2S_STBY        BIT(25)
0056 #define BCM2835_I2S_SYNC        BIT(24)
0057 #define BCM2835_I2S_RXSEX       BIT(23)
0058 #define BCM2835_I2S_RXF     BIT(22)
0059 #define BCM2835_I2S_TXE     BIT(21)
0060 #define BCM2835_I2S_RXD     BIT(20)
0061 #define BCM2835_I2S_TXD     BIT(19)
0062 #define BCM2835_I2S_RXR     BIT(18)
0063 #define BCM2835_I2S_TXW     BIT(17)
0064 #define BCM2835_I2S_CS_RXERR        BIT(16)
0065 #define BCM2835_I2S_CS_TXERR        BIT(15)
0066 #define BCM2835_I2S_RXSYNC      BIT(14)
0067 #define BCM2835_I2S_TXSYNC      BIT(13)
0068 #define BCM2835_I2S_DMAEN       BIT(9)
0069 #define BCM2835_I2S_RXTHR(v)        ((v) << 7)
0070 #define BCM2835_I2S_TXTHR(v)        ((v) << 5)
0071 #define BCM2835_I2S_RXCLR       BIT(4)
0072 #define BCM2835_I2S_TXCLR       BIT(3)
0073 #define BCM2835_I2S_TXON        BIT(2)
0074 #define BCM2835_I2S_RXON        BIT(1)
0075 #define BCM2835_I2S_EN          (1)
0076 
0077 #define BCM2835_I2S_CLKDIS      BIT(28)
0078 #define BCM2835_I2S_PDMN        BIT(27)
0079 #define BCM2835_I2S_PDME        BIT(26)
0080 #define BCM2835_I2S_FRXP        BIT(25)
0081 #define BCM2835_I2S_FTXP        BIT(24)
0082 #define BCM2835_I2S_CLKM        BIT(23)
0083 #define BCM2835_I2S_CLKI        BIT(22)
0084 #define BCM2835_I2S_FSM     BIT(21)
0085 #define BCM2835_I2S_FSI     BIT(20)
0086 #define BCM2835_I2S_FLEN(v)     ((v) << 10)
0087 #define BCM2835_I2S_FSLEN(v)        (v)
0088 
0089 #define BCM2835_I2S_CHWEX       BIT(15)
0090 #define BCM2835_I2S_CHEN        BIT(14)
0091 #define BCM2835_I2S_CHPOS(v)        ((v) << 4)
0092 #define BCM2835_I2S_CHWID(v)        (v)
0093 #define BCM2835_I2S_CH1(v)      ((v) << 16)
0094 #define BCM2835_I2S_CH2(v)      (v)
0095 #define BCM2835_I2S_CH1_POS(v)      BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
0096 #define BCM2835_I2S_CH2_POS(v)      BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
0097 
0098 #define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
0099 #define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
0100 #define BCM2835_I2S_TX(v)       ((v) << 8)
0101 #define BCM2835_I2S_RX(v)       (v)
0102 
0103 #define BCM2835_I2S_INT_RXERR       BIT(3)
0104 #define BCM2835_I2S_INT_TXERR       BIT(2)
0105 #define BCM2835_I2S_INT_RXR     BIT(1)
0106 #define BCM2835_I2S_INT_TXW     BIT(0)
0107 
0108 /* Frame length register is 10 bit, maximum length 1024 */
0109 #define BCM2835_I2S_MAX_FRAME_LENGTH    1024
0110 
0111 /* General device struct */
0112 struct bcm2835_i2s_dev {
0113     struct device               *dev;
0114     struct snd_dmaengine_dai_dma_data   dma_data[2];
0115     unsigned int                fmt;
0116     unsigned int                tdm_slots;
0117     unsigned int                rx_mask;
0118     unsigned int                tx_mask;
0119     unsigned int                slot_width;
0120     unsigned int                frame_length;
0121 
0122     struct regmap               *i2s_regmap;
0123     struct clk              *clk;
0124     bool                    clk_prepared;
0125     int                 clk_rate;
0126 };
0127 
0128 static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
0129 {
0130     unsigned int provider = dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
0131 
0132     if (dev->clk_prepared)
0133         return;
0134 
0135     switch (provider) {
0136     case SND_SOC_DAIFMT_BP_FP:
0137     case SND_SOC_DAIFMT_BP_FC:
0138         clk_prepare_enable(dev->clk);
0139         dev->clk_prepared = true;
0140         break;
0141     default:
0142         break;
0143     }
0144 }
0145 
0146 static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
0147 {
0148     if (dev->clk_prepared)
0149         clk_disable_unprepare(dev->clk);
0150     dev->clk_prepared = false;
0151 }
0152 
0153 static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
0154                     bool tx, bool rx)
0155 {
0156     int timeout = 1000;
0157     uint32_t syncval;
0158     uint32_t csreg;
0159     uint32_t i2s_active_state;
0160     bool clk_was_prepared;
0161     uint32_t off;
0162     uint32_t clr;
0163 
0164     off =  tx ? BCM2835_I2S_TXON : 0;
0165     off |= rx ? BCM2835_I2S_RXON : 0;
0166 
0167     clr =  tx ? BCM2835_I2S_TXCLR : 0;
0168     clr |= rx ? BCM2835_I2S_RXCLR : 0;
0169 
0170     /* Backup the current state */
0171     regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
0172     i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
0173 
0174     /* Start clock if not running */
0175     clk_was_prepared = dev->clk_prepared;
0176     if (!clk_was_prepared)
0177         bcm2835_i2s_start_clock(dev);
0178 
0179     /* Stop I2S module */
0180     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
0181 
0182     /*
0183      * Clear the FIFOs
0184      * Requires at least 2 PCM clock cycles to take effect
0185      */
0186     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
0187 
0188     /* Wait for 2 PCM clock cycles */
0189 
0190     /*
0191      * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
0192      * FIXME: This does not seem to work for slave mode!
0193      */
0194     regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
0195     syncval &= BCM2835_I2S_SYNC;
0196 
0197     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0198             BCM2835_I2S_SYNC, ~syncval);
0199 
0200     /* Wait for the SYNC flag changing it's state */
0201     while (--timeout) {
0202         regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
0203         if ((csreg & BCM2835_I2S_SYNC) != syncval)
0204             break;
0205     }
0206 
0207     if (!timeout)
0208         dev_err(dev->dev, "I2S SYNC error!\n");
0209 
0210     /* Stop clock if it was not running before */
0211     if (!clk_was_prepared)
0212         bcm2835_i2s_stop_clock(dev);
0213 
0214     /* Restore I2S state */
0215     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0216             BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
0217 }
0218 
0219 static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
0220                       unsigned int fmt)
0221 {
0222     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0223     dev->fmt = fmt;
0224     return 0;
0225 }
0226 
0227 static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
0228                       unsigned int ratio)
0229 {
0230     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0231 
0232     if (!ratio) {
0233         dev->tdm_slots = 0;
0234         return 0;
0235     }
0236 
0237     if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
0238         return -EINVAL;
0239 
0240     dev->tdm_slots = 2;
0241     dev->rx_mask = 0x03;
0242     dev->tx_mask = 0x03;
0243     dev->slot_width = ratio / 2;
0244     dev->frame_length = ratio;
0245 
0246     return 0;
0247 }
0248 
0249 static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
0250     unsigned int tx_mask, unsigned int rx_mask,
0251     int slots, int width)
0252 {
0253     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0254 
0255     if (slots) {
0256         if (slots < 0 || width < 0)
0257             return -EINVAL;
0258 
0259         /* Limit masks to available slots */
0260         rx_mask &= GENMASK(slots - 1, 0);
0261         tx_mask &= GENMASK(slots - 1, 0);
0262 
0263         /*
0264          * The driver is limited to 2-channel setups.
0265          * Check that exactly 2 bits are set in the masks.
0266          */
0267         if (hweight_long((unsigned long) rx_mask) != 2
0268             || hweight_long((unsigned long) tx_mask) != 2)
0269             return -EINVAL;
0270 
0271         if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
0272             return -EINVAL;
0273     }
0274 
0275     dev->tdm_slots = slots;
0276 
0277     dev->rx_mask = rx_mask;
0278     dev->tx_mask = tx_mask;
0279     dev->slot_width = width;
0280     dev->frame_length = slots * width;
0281 
0282     return 0;
0283 }
0284 
0285 /*
0286  * Convert logical slot number into physical slot number.
0287  *
0288  * If odd_offset is 0 sequential number is identical to logical number.
0289  * This is used for DSP modes with slot numbering 0 1 2 3 ...
0290  *
0291  * Otherwise odd_offset defines the physical offset for odd numbered
0292  * slots. This is used for I2S and left/right justified modes to
0293  * translate from logical slot numbers 0 1 2 3 ... into physical slot
0294  * numbers 0 2 ... 3 4 ...
0295  */
0296 static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
0297 {
0298     if (!odd_offset)
0299         return slot;
0300 
0301     if (slot & 1)
0302         return (slot >> 1) + odd_offset;
0303 
0304     return slot >> 1;
0305 }
0306 
0307 /*
0308  * Calculate channel position from mask and slot width.
0309  *
0310  * Mask must contain exactly 2 set bits.
0311  * Lowest set bit is channel 1 position, highest set bit channel 2.
0312  * The constant offset is added to both channel positions.
0313  *
0314  * If odd_offset is > 0 slot positions are translated to
0315  * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
0316  * logical slot numbers starting at physical slot odd_offset.
0317  */
0318 static void bcm2835_i2s_calc_channel_pos(
0319     unsigned int *ch1_pos, unsigned int *ch2_pos,
0320     unsigned int mask, unsigned int width,
0321     unsigned int bit_offset, unsigned int odd_offset)
0322 {
0323     *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
0324             * width + bit_offset;
0325     *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
0326             * width + bit_offset;
0327 }
0328 
0329 static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
0330                  struct snd_pcm_hw_params *params,
0331                  struct snd_soc_dai *dai)
0332 {
0333     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0334     unsigned int data_length, data_delay, framesync_length;
0335     unsigned int slots, slot_width, odd_slot_offset;
0336     int frame_length, bclk_rate;
0337     unsigned int rx_mask, tx_mask;
0338     unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
0339     unsigned int mode, format;
0340     bool bit_clock_provider = false;
0341     bool frame_sync_provider = false;
0342     bool frame_start_falling_edge = false;
0343     uint32_t csreg;
0344     int ret = 0;
0345 
0346     /*
0347      * If a stream is already enabled,
0348      * the registers are already set properly.
0349      */
0350     regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
0351 
0352     if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
0353         return 0;
0354 
0355     data_length = params_width(params);
0356     data_delay = 0;
0357     odd_slot_offset = 0;
0358     mode = 0;
0359 
0360     if (dev->tdm_slots) {
0361         slots = dev->tdm_slots;
0362         slot_width = dev->slot_width;
0363         frame_length = dev->frame_length;
0364         rx_mask = dev->rx_mask;
0365         tx_mask = dev->tx_mask;
0366         bclk_rate = dev->frame_length * params_rate(params);
0367     } else {
0368         slots = 2;
0369         slot_width = params_width(params);
0370         rx_mask = 0x03;
0371         tx_mask = 0x03;
0372 
0373         frame_length = snd_soc_params_to_frame_size(params);
0374         if (frame_length < 0)
0375             return frame_length;
0376 
0377         bclk_rate = snd_soc_params_to_bclk(params);
0378         if (bclk_rate < 0)
0379             return bclk_rate;
0380     }
0381 
0382     /* Check if data fits into slots */
0383     if (data_length > slot_width)
0384         return -EINVAL;
0385 
0386     /* Check if CPU is bit clock provider */
0387     switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0388     case SND_SOC_DAIFMT_BP_FP:
0389     case SND_SOC_DAIFMT_BP_FC:
0390         bit_clock_provider = true;
0391         break;
0392     case SND_SOC_DAIFMT_BC_FP:
0393     case SND_SOC_DAIFMT_BC_FC:
0394         bit_clock_provider = false;
0395         break;
0396     default:
0397         return -EINVAL;
0398     }
0399 
0400     /* Check if CPU is frame sync provider */
0401     switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0402     case SND_SOC_DAIFMT_BP_FP:
0403     case SND_SOC_DAIFMT_BC_FP:
0404         frame_sync_provider = true;
0405         break;
0406     case SND_SOC_DAIFMT_BP_FC:
0407     case SND_SOC_DAIFMT_BC_FC:
0408         frame_sync_provider = false;
0409         break;
0410     default:
0411         return -EINVAL;
0412     }
0413 
0414     /* Clock should only be set up here if CPU is clock master */
0415     if (bit_clock_provider &&
0416         (!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
0417         if (dev->clk_prepared)
0418             bcm2835_i2s_stop_clock(dev);
0419 
0420         if (dev->clk_rate != bclk_rate) {
0421             ret = clk_set_rate(dev->clk, bclk_rate);
0422             if (ret)
0423                 return ret;
0424             dev->clk_rate = bclk_rate;
0425         }
0426 
0427         bcm2835_i2s_start_clock(dev);
0428     }
0429 
0430     /* Setup the frame format */
0431     format = BCM2835_I2S_CHEN;
0432 
0433     if (data_length >= 24)
0434         format |= BCM2835_I2S_CHWEX;
0435 
0436     format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
0437 
0438     /* CH2 format is the same as for CH1 */
0439     format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
0440 
0441     switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0442     case SND_SOC_DAIFMT_I2S:
0443         /* I2S mode needs an even number of slots */
0444         if (slots & 1)
0445             return -EINVAL;
0446 
0447         /*
0448          * Use I2S-style logical slot numbering: even slots
0449          * are in first half of frame, odd slots in second half.
0450          */
0451         odd_slot_offset = slots >> 1;
0452 
0453         /* MSB starts one cycle after frame start */
0454         data_delay = 1;
0455 
0456         /* Setup frame sync signal for 50% duty cycle */
0457         framesync_length = frame_length / 2;
0458         frame_start_falling_edge = true;
0459         break;
0460     case SND_SOC_DAIFMT_LEFT_J:
0461         if (slots & 1)
0462             return -EINVAL;
0463 
0464         odd_slot_offset = slots >> 1;
0465         data_delay = 0;
0466         framesync_length = frame_length / 2;
0467         frame_start_falling_edge = false;
0468         break;
0469     case SND_SOC_DAIFMT_RIGHT_J:
0470         if (slots & 1)
0471             return -EINVAL;
0472 
0473         /* Odd frame lengths aren't supported */
0474         if (frame_length & 1)
0475             return -EINVAL;
0476 
0477         odd_slot_offset = slots >> 1;
0478         data_delay = slot_width - data_length;
0479         framesync_length = frame_length / 2;
0480         frame_start_falling_edge = false;
0481         break;
0482     case SND_SOC_DAIFMT_DSP_A:
0483         data_delay = 1;
0484         framesync_length = 1;
0485         frame_start_falling_edge = false;
0486         break;
0487     case SND_SOC_DAIFMT_DSP_B:
0488         data_delay = 0;
0489         framesync_length = 1;
0490         frame_start_falling_edge = false;
0491         break;
0492     default:
0493         return -EINVAL;
0494     }
0495 
0496     bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
0497         rx_mask, slot_width, data_delay, odd_slot_offset);
0498     bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
0499         tx_mask, slot_width, data_delay, odd_slot_offset);
0500 
0501     /*
0502      * Transmitting data immediately after frame start, eg
0503      * in left-justified or DSP mode A, only works stable
0504      * if bcm2835 is the frame clock provider.
0505      */
0506     if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_provider)
0507         dev_warn(dev->dev,
0508             "Unstable consumer config detected, L/R may be swapped");
0509 
0510     /*
0511      * Set format for both streams.
0512      * We cannot set another frame length
0513      * (and therefore word length) anyway,
0514      * so the format will be the same.
0515      */
0516     regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, 
0517           format
0518         | BCM2835_I2S_CH1_POS(rx_ch1_pos)
0519         | BCM2835_I2S_CH2_POS(rx_ch2_pos));
0520     regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, 
0521           format
0522         | BCM2835_I2S_CH1_POS(tx_ch1_pos)
0523         | BCM2835_I2S_CH2_POS(tx_ch2_pos));
0524 
0525     /* Setup the I2S mode */
0526 
0527     if (data_length <= 16) {
0528         /*
0529          * Use frame packed mode (2 channels per 32 bit word)
0530          * We cannot set another frame length in the second stream
0531          * (and therefore word length) anyway,
0532          * so the format will be the same.
0533          */
0534         mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
0535     }
0536 
0537     mode |= BCM2835_I2S_FLEN(frame_length - 1);
0538     mode |= BCM2835_I2S_FSLEN(framesync_length);
0539 
0540     /* CLKM selects bcm2835 clock slave mode */
0541     if (!bit_clock_provider)
0542         mode |= BCM2835_I2S_CLKM;
0543 
0544     /* FSM selects bcm2835 frame sync slave mode */
0545     if (!frame_sync_provider)
0546         mode |= BCM2835_I2S_FSM;
0547 
0548     /* CLKI selects normal clocking mode, sampling on rising edge */
0549         switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
0550     case SND_SOC_DAIFMT_NB_NF:
0551     case SND_SOC_DAIFMT_NB_IF:
0552         mode |= BCM2835_I2S_CLKI;
0553         break;
0554     case SND_SOC_DAIFMT_IB_NF:
0555     case SND_SOC_DAIFMT_IB_IF:
0556         break;
0557     default:
0558         return -EINVAL;
0559     }
0560 
0561     /* FSI selects frame start on falling edge */
0562     switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
0563     case SND_SOC_DAIFMT_NB_NF:
0564     case SND_SOC_DAIFMT_IB_NF:
0565         if (frame_start_falling_edge)
0566             mode |= BCM2835_I2S_FSI;
0567         break;
0568     case SND_SOC_DAIFMT_NB_IF:
0569     case SND_SOC_DAIFMT_IB_IF:
0570         if (!frame_start_falling_edge)
0571             mode |= BCM2835_I2S_FSI;
0572         break;
0573     default:
0574         return -EINVAL;
0575     }
0576 
0577     regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
0578 
0579     /* Setup the DMA parameters */
0580     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0581             BCM2835_I2S_RXTHR(1)
0582             | BCM2835_I2S_TXTHR(1)
0583             | BCM2835_I2S_DMAEN, 0xffffffff);
0584 
0585     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
0586               BCM2835_I2S_TX_PANIC(0x10)
0587             | BCM2835_I2S_RX_PANIC(0x30)
0588             | BCM2835_I2S_TX(0x30)
0589             | BCM2835_I2S_RX(0x20), 0xffffffff);
0590 
0591     /* Clear FIFOs */
0592     bcm2835_i2s_clear_fifos(dev, true, true);
0593 
0594     dev_dbg(dev->dev,
0595         "slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
0596         slots, slot_width, rx_mask, tx_mask);
0597 
0598     dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
0599         frame_length, framesync_length, data_length);
0600 
0601     dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
0602         rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
0603 
0604     dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
0605         params_rate(params), bclk_rate);
0606 
0607     dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
0608         !!(mode & BCM2835_I2S_CLKM),
0609         !!(mode & BCM2835_I2S_CLKI),
0610         !!(mode & BCM2835_I2S_FSM),
0611         !!(mode & BCM2835_I2S_FSI),
0612         (mode & BCM2835_I2S_FSI) ? "falling" : "rising");
0613 
0614     return ret;
0615 }
0616 
0617 static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
0618         struct snd_soc_dai *dai)
0619 {
0620     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0621     uint32_t cs_reg;
0622 
0623     /*
0624      * Clear both FIFOs if the one that should be started
0625      * is not empty at the moment. This should only happen
0626      * after overrun. Otherwise, hw_params would have cleared
0627      * the FIFO.
0628      */
0629     regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
0630 
0631     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
0632             && !(cs_reg & BCM2835_I2S_TXE))
0633         bcm2835_i2s_clear_fifos(dev, true, false);
0634     else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
0635             && (cs_reg & BCM2835_I2S_RXD))
0636         bcm2835_i2s_clear_fifos(dev, false, true);
0637 
0638     return 0;
0639 }
0640 
0641 static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
0642         struct snd_pcm_substream *substream,
0643         struct snd_soc_dai *dai)
0644 {
0645     uint32_t mask;
0646 
0647     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0648         mask = BCM2835_I2S_RXON;
0649     else
0650         mask = BCM2835_I2S_TXON;
0651 
0652     regmap_update_bits(dev->i2s_regmap,
0653             BCM2835_I2S_CS_A_REG, mask, 0);
0654 
0655     /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
0656     if (!snd_soc_dai_active(dai) && !(dev->fmt & SND_SOC_DAIFMT_CONT))
0657         bcm2835_i2s_stop_clock(dev);
0658 }
0659 
0660 static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
0661                    struct snd_soc_dai *dai)
0662 {
0663     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0664     uint32_t mask;
0665 
0666     switch (cmd) {
0667     case SNDRV_PCM_TRIGGER_START:
0668     case SNDRV_PCM_TRIGGER_RESUME:
0669     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0670         bcm2835_i2s_start_clock(dev);
0671 
0672         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0673             mask = BCM2835_I2S_RXON;
0674         else
0675             mask = BCM2835_I2S_TXON;
0676 
0677         regmap_update_bits(dev->i2s_regmap,
0678                 BCM2835_I2S_CS_A_REG, mask, mask);
0679         break;
0680 
0681     case SNDRV_PCM_TRIGGER_STOP:
0682     case SNDRV_PCM_TRIGGER_SUSPEND:
0683     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0684         bcm2835_i2s_stop(dev, substream, dai);
0685         break;
0686     default:
0687         return -EINVAL;
0688     }
0689 
0690     return 0;
0691 }
0692 
0693 static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
0694                    struct snd_soc_dai *dai)
0695 {
0696     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0697 
0698     if (snd_soc_dai_active(dai))
0699         return 0;
0700 
0701     /* Should this still be running stop it */
0702     bcm2835_i2s_stop_clock(dev);
0703 
0704     /* Enable PCM block */
0705     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0706             BCM2835_I2S_EN, BCM2835_I2S_EN);
0707 
0708     /*
0709      * Disable STBY.
0710      * Requires at least 4 PCM clock cycles to take effect.
0711      */
0712     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0713             BCM2835_I2S_STBY, BCM2835_I2S_STBY);
0714 
0715     return 0;
0716 }
0717 
0718 static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
0719         struct snd_soc_dai *dai)
0720 {
0721     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0722 
0723     bcm2835_i2s_stop(dev, substream, dai);
0724 
0725     /* If both streams are stopped, disable module and clock */
0726     if (snd_soc_dai_active(dai))
0727         return;
0728 
0729     /* Disable the module */
0730     regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0731             BCM2835_I2S_EN, 0);
0732 
0733     /*
0734      * Stopping clock is necessary, because stop does
0735      * not stop the clock when SND_SOC_DAIFMT_CONT
0736      */
0737     bcm2835_i2s_stop_clock(dev);
0738 }
0739 
0740 static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
0741     .startup    = bcm2835_i2s_startup,
0742     .shutdown   = bcm2835_i2s_shutdown,
0743     .prepare    = bcm2835_i2s_prepare,
0744     .trigger    = bcm2835_i2s_trigger,
0745     .hw_params  = bcm2835_i2s_hw_params,
0746     .set_fmt    = bcm2835_i2s_set_dai_fmt,
0747     .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
0748     .set_tdm_slot   = bcm2835_i2s_set_dai_tdm_slot,
0749 };
0750 
0751 static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
0752 {
0753     struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0754 
0755     snd_soc_dai_init_dma_data(dai,
0756             &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
0757             &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
0758 
0759     return 0;
0760 }
0761 
0762 static struct snd_soc_dai_driver bcm2835_i2s_dai = {
0763     .name   = "bcm2835-i2s",
0764     .probe  = bcm2835_i2s_dai_probe,
0765     .playback = {
0766         .channels_min = 2,
0767         .channels_max = 2,
0768         .rates =    SNDRV_PCM_RATE_CONTINUOUS,
0769         .rate_min = 8000,
0770         .rate_max = 384000,
0771         .formats =  SNDRV_PCM_FMTBIT_S16_LE
0772                 | SNDRV_PCM_FMTBIT_S24_LE
0773                 | SNDRV_PCM_FMTBIT_S32_LE
0774         },
0775     .capture = {
0776         .channels_min = 2,
0777         .channels_max = 2,
0778         .rates =    SNDRV_PCM_RATE_CONTINUOUS,
0779         .rate_min = 8000,
0780         .rate_max = 384000,
0781         .formats =  SNDRV_PCM_FMTBIT_S16_LE
0782                 | SNDRV_PCM_FMTBIT_S24_LE
0783                 | SNDRV_PCM_FMTBIT_S32_LE
0784         },
0785     .ops = &bcm2835_i2s_dai_ops,
0786     .symmetric_rate = 1,
0787     .symmetric_sample_bits = 1,
0788 };
0789 
0790 static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
0791 {
0792     switch (reg) {
0793     case BCM2835_I2S_CS_A_REG:
0794     case BCM2835_I2S_FIFO_A_REG:
0795     case BCM2835_I2S_INTSTC_A_REG:
0796     case BCM2835_I2S_GRAY_REG:
0797         return true;
0798     default:
0799         return false;
0800     }
0801 }
0802 
0803 static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
0804 {
0805     switch (reg) {
0806     case BCM2835_I2S_FIFO_A_REG:
0807         return true;
0808     default:
0809         return false;
0810     }
0811 }
0812 
0813 static const struct regmap_config bcm2835_regmap_config = {
0814     .reg_bits = 32,
0815     .reg_stride = 4,
0816     .val_bits = 32,
0817     .max_register = BCM2835_I2S_GRAY_REG,
0818     .precious_reg = bcm2835_i2s_precious_reg,
0819     .volatile_reg = bcm2835_i2s_volatile_reg,
0820     .cache_type = REGCACHE_RBTREE,
0821 };
0822 
0823 static const struct snd_soc_component_driver bcm2835_i2s_component = {
0824     .name           = "bcm2835-i2s-comp",
0825     .legacy_dai_naming  = 1,
0826 };
0827 
0828 static int bcm2835_i2s_probe(struct platform_device *pdev)
0829 {
0830     struct bcm2835_i2s_dev *dev;
0831     int ret;
0832     void __iomem *base;
0833     const __be32 *addr;
0834     dma_addr_t dma_base;
0835 
0836     dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
0837                GFP_KERNEL);
0838     if (!dev)
0839         return -ENOMEM;
0840 
0841     /* get the clock */
0842     dev->clk_prepared = false;
0843     dev->clk = devm_clk_get(&pdev->dev, NULL);
0844     if (IS_ERR(dev->clk)) {
0845         ret = PTR_ERR(dev->clk);
0846         if (ret == -EPROBE_DEFER)
0847             dev_dbg(&pdev->dev, "could not get clk: %d\n", ret);
0848         else
0849             dev_err(&pdev->dev, "could not get clk: %d\n", ret);
0850         return ret;
0851     }
0852 
0853     /* Request ioarea */
0854     base = devm_platform_ioremap_resource(pdev, 0);
0855     if (IS_ERR(base))
0856         return PTR_ERR(base);
0857 
0858     dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
0859                 &bcm2835_regmap_config);
0860     if (IS_ERR(dev->i2s_regmap))
0861         return PTR_ERR(dev->i2s_regmap);
0862 
0863     /* Set the DMA address - we have to parse DT ourselves */
0864     addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
0865     if (!addr) {
0866         dev_err(&pdev->dev, "could not get DMA-register address\n");
0867         return -EINVAL;
0868     }
0869     dma_base = be32_to_cpup(addr);
0870 
0871     dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
0872         dma_base + BCM2835_I2S_FIFO_A_REG;
0873 
0874     dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
0875         dma_base + BCM2835_I2S_FIFO_A_REG;
0876 
0877     /* Set the bus width */
0878     dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
0879         DMA_SLAVE_BUSWIDTH_4_BYTES;
0880     dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
0881         DMA_SLAVE_BUSWIDTH_4_BYTES;
0882 
0883     /* Set burst */
0884     dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
0885     dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
0886 
0887     /*
0888      * Set the PACK flag to enable S16_LE support (2 S16_LE values
0889      * packed into 32-bit transfers).
0890      */
0891     dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags =
0892         SND_DMAENGINE_PCM_DAI_FLAG_PACK;
0893     dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
0894         SND_DMAENGINE_PCM_DAI_FLAG_PACK;
0895 
0896     /* Store the pdev */
0897     dev->dev = &pdev->dev;
0898     dev_set_drvdata(&pdev->dev, dev);
0899 
0900     ret = devm_snd_soc_register_component(&pdev->dev,
0901             &bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
0902     if (ret) {
0903         dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
0904         return ret;
0905     }
0906 
0907     ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
0908     if (ret) {
0909         dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
0910         return ret;
0911     }
0912 
0913     return 0;
0914 }
0915 
0916 static const struct of_device_id bcm2835_i2s_of_match[] = {
0917     { .compatible = "brcm,bcm2835-i2s", },
0918     {},
0919 };
0920 
0921 MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
0922 
0923 static struct platform_driver bcm2835_i2s_driver = {
0924     .probe      = bcm2835_i2s_probe,
0925     .driver     = {
0926         .name   = "bcm2835-i2s",
0927         .of_match_table = bcm2835_i2s_of_match,
0928     },
0929 };
0930 
0931 module_platform_driver(bcm2835_i2s_driver);
0932 
0933 MODULE_ALIAS("platform:bcm2835-i2s");
0934 MODULE_DESCRIPTION("BCM2835 I2S interface");
0935 MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
0936 MODULE_LICENSE("GPL v2");
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