soc/au1x/i2sc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Au1000/Au1500/Au1100 I2S controller driver for ASoC
0004  *
0005  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
0006  *
0007  * Note: clock supplied to the I2S controller must be 256x samplerate.
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/module.h>
0012 #include <linux/slab.h>
0013 #include <linux/suspend.h>
0014 #include <sound/core.h>
0015 #include <sound/pcm.h>
0016 #include <sound/initval.h>
0017 #include <sound/soc.h>
0018 #include <asm/mach-au1x00/au1000.h>
0019
0020 #include "psc.h"
0021
0022 #define I2S_RXTX    0x00
0023 #define I2S_CFG     0x04
0024 #define I2S_ENABLE  0x08
0025
0026 #define CFG_XU      (1 << 25)   /* tx underflow */
0027 #define CFG_XO      (1 << 24)
0028 #define CFG_RU      (1 << 23)
0029 #define CFG_RO      (1 << 22)
0030 #define CFG_TR      (1 << 21)
0031 #define CFG_TE      (1 << 20)
0032 #define CFG_TF      (1 << 19)
0033 #define CFG_RR      (1 << 18)
0034 #define CFG_RF      (1 << 17)
0035 #define CFG_ICK     (1 << 12)   /* clock invert */
0036 #define CFG_PD      (1 << 11)   /* set to make I2SDIO INPUT */
0037 #define CFG_LB      (1 << 10)   /* loopback */
0038 #define CFG_IC      (1 << 9)    /* word select invert */
0039 #define CFG_FM_I2S  (0 << 7)    /* I2S format */
0040 #define CFG_FM_LJ   (1 << 7)    /* left-justified */
0041 #define CFG_FM_RJ   (2 << 7)    /* right-justified */
0042 #define CFG_FM_MASK (3 << 7)
0043 #define CFG_TN      (1 << 6)    /* tx fifo en */
0044 #define CFG_RN      (1 << 5)    /* rx fifo en */
0045 #define CFG_SZ_8    (0x08)
0046 #define CFG_SZ_16   (0x10)
0047 #define CFG_SZ_18   (0x12)
0048 #define CFG_SZ_20   (0x14)
0049 #define CFG_SZ_24   (0x18)
0050 #define CFG_SZ_MASK (0x1f)
0051 #define EN_D        (1 << 1)    /* DISable */
0052 #define EN_CE       (1 << 0)    /* clock enable */
0053
0054 /* only limited by clock generator and board design */
0055 #define AU1XI2SC_RATES \
0056     SNDRV_PCM_RATE_CONTINUOUS
0057
0058 #define AU1XI2SC_FMTS \
0059     (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |        \
0060     SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
0061     SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
0062     SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE |   \
0063     SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_U18_3BE |   \
0064     SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE |   \
0065     SNDRV_PCM_FMTBIT_S20_3BE | SNDRV_PCM_FMTBIT_U20_3BE |   \
0066     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
0067     SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
0068     0)
0069
0070 static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
0071 {
0072     return __raw_readl(ctx->mmio + reg);
0073 }
0074
0075 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
0076 {
0077     __raw_writel(v, ctx->mmio + reg);
0078     wmb();
0079 }
0080
0081 static int au1xi2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
0082 {
0083     struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(cpu_dai);
0084     unsigned long c;
0085     int ret;
0086
0087     ret = -EINVAL;
0088     c = ctx->cfg;
0089
0090     c &= ~CFG_FM_MASK;
0091     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0092     case SND_SOC_DAIFMT_I2S:
0093         c |= CFG_FM_I2S;
0094         break;
0095     case SND_SOC_DAIFMT_MSB:
0096         c |= CFG_FM_RJ;
0097         break;
0098     case SND_SOC_DAIFMT_LSB:
0099         c |= CFG_FM_LJ;
0100         break;
0101     default:
0102         goto out;
0103     }
0104
0105     c &= ~(CFG_IC | CFG_ICK);       /* IB-IF */
0106     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0107     case SND_SOC_DAIFMT_NB_NF:
0108         c |= CFG_IC | CFG_ICK;
0109         break;
0110     case SND_SOC_DAIFMT_NB_IF:
0111         c |= CFG_IC;
0112         break;
0113     case SND_SOC_DAIFMT_IB_NF:
0114         c |= CFG_ICK;
0115         break;
0116     case SND_SOC_DAIFMT_IB_IF:
0117         break;
0118     default:
0119         goto out;
0120     }
0121
0122     /* I2S controller only supports provider */
0123     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0124     case SND_SOC_DAIFMT_BP_FP:  /* CODEC consumer */
0125         break;
0126     default:
0127         goto out;
0128     }
0129
0130     ret = 0;
0131     ctx->cfg = c;
0132 out:
0133     return ret;
0134 }
0135
0136 static int au1xi2s_trigger(struct snd_pcm_substream *substream,
0137                int cmd, struct snd_soc_dai *dai)
0138 {
0139     struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
0140     int stype = SUBSTREAM_TYPE(substream);
0141
0142     switch (cmd) {
0143     case SNDRV_PCM_TRIGGER_START:
0144     case SNDRV_PCM_TRIGGER_RESUME:
0145         /* power up */
0146         WR(ctx, I2S_ENABLE, EN_D | EN_CE);
0147         WR(ctx, I2S_ENABLE, EN_CE);
0148         ctx->cfg |= (stype == PCM_TX) ? CFG_TN : CFG_RN;
0149         WR(ctx, I2S_CFG, ctx->cfg);
0150         break;
0151     case SNDRV_PCM_TRIGGER_STOP:
0152     case SNDRV_PCM_TRIGGER_SUSPEND:
0153         ctx->cfg &= ~((stype == PCM_TX) ? CFG_TN : CFG_RN);
0154         WR(ctx, I2S_CFG, ctx->cfg);
0155         WR(ctx, I2S_ENABLE, EN_D);      /* power off */
0156         break;
0157     default:
0158         return -EINVAL;
0159     }
0160
0161     return 0;
0162 }
0163
0164 static unsigned long msbits_to_reg(int msbits)
0165 {
0166     switch (msbits) {
0167     case 8:
0168         return CFG_SZ_8;
0169     case 16:
0170         return CFG_SZ_16;
0171     case 18:
0172         return CFG_SZ_18;
0173     case 20:
0174         return CFG_SZ_20;
0175     case 24:
0176         return CFG_SZ_24;
0177     }
0178     return 0;
0179 }
0180
0181 static int au1xi2s_hw_params(struct snd_pcm_substream *substream,
0182                  struct snd_pcm_hw_params *params,
0183                  struct snd_soc_dai *dai)
0184 {
0185     struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
0186     unsigned long v;
0187
0188     v = msbits_to_reg(params->msbits);
0189     if (!v)
0190         return -EINVAL;
0191
0192     ctx->cfg &= ~CFG_SZ_MASK;
0193     ctx->cfg |= v;
0194     return 0;
0195 }
0196
0197 static int au1xi2s_startup(struct snd_pcm_substream *substream,
0198                struct snd_soc_dai *dai)
0199 {
0200     struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
0201     snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
0202     return 0;
0203 }
0204
0205 static const struct snd_soc_dai_ops au1xi2s_dai_ops = {
0206     .startup    = au1xi2s_startup,
0207     .trigger    = au1xi2s_trigger,
0208     .hw_params  = au1xi2s_hw_params,
0209     .set_fmt    = au1xi2s_set_fmt,
0210 };
0211
0212 static struct snd_soc_dai_driver au1xi2s_dai_driver = {
0213     .symmetric_rate     = 1,
0214     .playback = {
0215         .rates      = AU1XI2SC_RATES,
0216         .formats    = AU1XI2SC_FMTS,
0217         .channels_min   = 2,
0218         .channels_max   = 2,
0219     },
0220     .capture = {
0221         .rates      = AU1XI2SC_RATES,
0222         .formats    = AU1XI2SC_FMTS,
0223         .channels_min   = 2,
0224         .channels_max   = 2,
0225     },
0226     .ops = &au1xi2s_dai_ops,
0227 };
0228
0229 static const struct snd_soc_component_driver au1xi2s_component = {
0230     .name           = "au1xi2s",
0231     .legacy_dai_naming  = 1,
0232 };
0233
0234 static int au1xi2s_drvprobe(struct platform_device *pdev)
0235 {
0236     struct resource *iores, *dmares;
0237     struct au1xpsc_audio_data *ctx;
0238
0239     ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
0240     if (!ctx)
0241         return -ENOMEM;
0242
0243     iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0244     if (!iores)
0245         return -ENODEV;
0246
0247     if (!devm_request_mem_region(&pdev->dev, iores->start,
0248                      resource_size(iores),
0249                      pdev->name))
0250         return -EBUSY;
0251
0252     ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
0253                      resource_size(iores));
0254     if (!ctx->mmio)
0255         return -EBUSY;
0256
0257     dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
0258     if (!dmares)
0259         return -EBUSY;
0260     ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
0261
0262     dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
0263     if (!dmares)
0264         return -EBUSY;
0265     ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
0266
0267     platform_set_drvdata(pdev, ctx);
0268
0269     return snd_soc_register_component(&pdev->dev, &au1xi2s_component,
0270                       &au1xi2s_dai_driver, 1);
0271 }
0272
0273 static int au1xi2s_drvremove(struct platform_device *pdev)
0274 {
0275     struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
0276
0277     snd_soc_unregister_component(&pdev->dev);
0278
0279     WR(ctx, I2S_ENABLE, EN_D);  /* clock off, disable */
0280
0281     return 0;
0282 }
0283
0284 #ifdef CONFIG_PM
0285 static int au1xi2s_drvsuspend(struct device *dev)
0286 {
0287     struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
0288
0289     WR(ctx, I2S_ENABLE, EN_D);  /* clock off, disable */
0290
0291     return 0;
0292 }
0293
0294 static int au1xi2s_drvresume(struct device *dev)
0295 {
0296     return 0;
0297 }
0298
0299 static const struct dev_pm_ops au1xi2sc_pmops = {
0300     .suspend    = au1xi2s_drvsuspend,
0301     .resume     = au1xi2s_drvresume,
0302 };
0303
0304 #define AU1XI2SC_PMOPS (&au1xi2sc_pmops)
0305
0306 #else
0307
0308 #define AU1XI2SC_PMOPS NULL
0309
0310 #endif
0311
0312 static struct platform_driver au1xi2s_driver = {
0313     .driver = {
0314         .name   = "alchemy-i2sc",
0315         .pm = AU1XI2SC_PMOPS,
0316     },
0317     .probe      = au1xi2s_drvprobe,
0318     .remove     = au1xi2s_drvremove,
0319 };
0320
0321 module_platform_driver(au1xi2s_driver);
0322
0323 MODULE_LICENSE("GPL");
0324 MODULE_DESCRIPTION("Au1000/1500/1100 I2S ASoC driver");
0325 MODULE_AUTHOR("Manuel Lauss");