soc/au1x/ac97c.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
0004  *
0005  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
0006  *
0007  * based on the old ALSA driver originally written by
0008  *          Charles Eidsness <charles@cooper-street.com>
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/slab.h>
0014 #include <linux/device.h>
0015 #include <linux/delay.h>
0016 #include <linux/mutex.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/suspend.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/initval.h>
0022 #include <sound/soc.h>
0023 #include <asm/mach-au1x00/au1000.h>
0024
0025 #include "psc.h"
0026
0027 /* register offsets and bits */
0028 #define AC97_CONFIG 0x00
0029 #define AC97_STATUS 0x04
0030 #define AC97_DATA   0x08
0031 #define AC97_CMDRESP    0x0c
0032 #define AC97_ENABLE 0x10
0033
0034 #define CFG_RC(x)   (((x) & 0x3ff) << 13)   /* valid rx slots mask */
0035 #define CFG_XS(x)   (((x) & 0x3ff) << 3)    /* valid tx slots mask */
0036 #define CFG_SG      (1 << 2)    /* sync gate */
0037 #define CFG_SN      (1 << 1)    /* sync control */
0038 #define CFG_RS      (1 << 0)    /* acrst# control */
0039 #define STAT_XU     (1 << 11)   /* tx underflow */
0040 #define STAT_XO     (1 << 10)   /* tx overflow */
0041 #define STAT_RU     (1 << 9)    /* rx underflow */
0042 #define STAT_RO     (1 << 8)    /* rx overflow */
0043 #define STAT_RD     (1 << 7)    /* codec ready */
0044 #define STAT_CP     (1 << 6)    /* command pending */
0045 #define STAT_TE     (1 << 4)    /* tx fifo empty */
0046 #define STAT_TF     (1 << 3)    /* tx fifo full */
0047 #define STAT_RE     (1 << 1)    /* rx fifo empty */
0048 #define STAT_RF     (1 << 0)    /* rx fifo full */
0049 #define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
0050 #define CMD_GET_DATA(x) ((x) & 0xffff)
0051 #define CMD_READ    (1 << 7)
0052 #define CMD_WRITE   (0 << 7)
0053 #define CMD_IDX(x)  ((x) & 0x7f)
0054 #define EN_D        (1 << 1)    /* DISable bit */
0055 #define EN_CE       (1 << 0)    /* clock enable bit */
0056
0057 /* how often to retry failed codec register reads/writes */
0058 #define AC97_RW_RETRIES 5
0059
0060 #define AC97_RATES  \
0061     SNDRV_PCM_RATE_CONTINUOUS
0062
0063 #define AC97_FMTS   \
0064     (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
0065
0066 /* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
0067  * once AC97C on early Alchemy chips. The newer ones aren't so lucky.
0068  */
0069 static struct au1xpsc_audio_data *ac97c_workdata;
0070 #define ac97_to_ctx(x)      ac97c_workdata
0071
0072 static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
0073 {
0074     return __raw_readl(ctx->mmio + reg);
0075 }
0076
0077 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
0078 {
0079     __raw_writel(v, ctx->mmio + reg);
0080     wmb();
0081 }
0082
0083 static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
0084                       unsigned short r)
0085 {
0086     struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
0087     unsigned int tmo, retry;
0088     unsigned long data;
0089
0090     data = ~0;
0091     retry = AC97_RW_RETRIES;
0092     do {
0093         mutex_lock(&ctx->lock);
0094
0095         tmo = 6;
0096         while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
0097             udelay(21); /* wait an ac97 frame time */
0098         if (!tmo) {
0099             pr_debug("ac97rd timeout #1\n");
0100             goto next;
0101         }
0102
0103         WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
0104
0105         /* stupid errata: data is only valid for 21us, so
0106          * poll, Forrest, poll...
0107          */
0108         tmo = 0x10000;
0109         while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
0110             asm volatile ("nop");
0111         data = RD(ctx, AC97_CMDRESP);
0112
0113         if (!tmo)
0114             pr_debug("ac97rd timeout #2\n");
0115
0116 next:
0117         mutex_unlock(&ctx->lock);
0118     } while (--retry && !tmo);
0119
0120     pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
0121
0122     return retry ? data & 0xffff : 0xffff;
0123 }
0124
0125 static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
0126                  unsigned short v)
0127 {
0128     struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
0129     unsigned int tmo, retry;
0130
0131     retry = AC97_RW_RETRIES;
0132     do {
0133         mutex_lock(&ctx->lock);
0134
0135         for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
0136             udelay(21);
0137         if (!tmo) {
0138             pr_debug("ac97wr timeout #1\n");
0139             goto next;
0140         }
0141
0142         WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
0143
0144         for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
0145             udelay(21);
0146         if (!tmo)
0147             pr_debug("ac97wr timeout #2\n");
0148 next:
0149         mutex_unlock(&ctx->lock);
0150     } while (--retry && !tmo);
0151
0152     pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
0153 }
0154
0155 static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
0156 {
0157     struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
0158
0159     WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
0160     msleep(20);
0161     WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
0162     WR(ctx, AC97_CONFIG, ctx->cfg);
0163 }
0164
0165 static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
0166 {
0167     struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
0168     int i;
0169
0170     WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
0171     msleep(500);
0172     WR(ctx, AC97_CONFIG, ctx->cfg);
0173
0174     /* wait for codec ready */
0175     i = 50;
0176     while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
0177         msleep(20);
0178     if (!i)
0179         printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
0180 }
0181
0182 /* AC97 controller operations */
0183 static struct snd_ac97_bus_ops ac97c_bus_ops = {
0184     .read       = au1xac97c_ac97_read,
0185     .write      = au1xac97c_ac97_write,
0186     .reset      = au1xac97c_ac97_cold_reset,
0187     .warm_reset = au1xac97c_ac97_warm_reset,
0188 };
0189
0190 static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
0191                  struct snd_soc_dai *dai)
0192 {
0193     struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
0194     snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
0195     return 0;
0196 }
0197
0198 static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
0199     .startup        = alchemy_ac97c_startup,
0200 };
0201
0202 static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
0203 {
0204     return ac97c_workdata ? 0 : -ENODEV;
0205 }
0206
0207 static struct snd_soc_dai_driver au1xac97c_dai_driver = {
0208     .name           = "alchemy-ac97c",
0209     .probe          = au1xac97c_dai_probe,
0210     .playback = {
0211         .rates      = AC97_RATES,
0212         .formats    = AC97_FMTS,
0213         .channels_min   = 2,
0214         .channels_max   = 2,
0215     },
0216     .capture = {
0217         .rates      = AC97_RATES,
0218         .formats    = AC97_FMTS,
0219         .channels_min   = 2,
0220         .channels_max   = 2,
0221     },
0222     .ops            = &alchemy_ac97c_ops,
0223 };
0224
0225 static const struct snd_soc_component_driver au1xac97c_component = {
0226     .name           = "au1xac97c",
0227     .legacy_dai_naming  = 1,
0228 };
0229
0230 static int au1xac97c_drvprobe(struct platform_device *pdev)
0231 {
0232     int ret;
0233     struct resource *iores, *dmares;
0234     struct au1xpsc_audio_data *ctx;
0235
0236     ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
0237     if (!ctx)
0238         return -ENOMEM;
0239
0240     mutex_init(&ctx->lock);
0241
0242     iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0243     if (!iores)
0244         return -ENODEV;
0245
0246     if (!devm_request_mem_region(&pdev->dev, iores->start,
0247                      resource_size(iores),
0248                      pdev->name))
0249         return -EBUSY;
0250
0251     ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
0252                      resource_size(iores));
0253     if (!ctx->mmio)
0254         return -EBUSY;
0255
0256     dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
0257     if (!dmares)
0258         return -EBUSY;
0259     ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
0260
0261     dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
0262     if (!dmares)
0263         return -EBUSY;
0264     ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
0265
0266     /* switch it on */
0267     WR(ctx, AC97_ENABLE, EN_D | EN_CE);
0268     WR(ctx, AC97_ENABLE, EN_CE);
0269
0270     ctx->cfg = CFG_RC(3) | CFG_XS(3);
0271     WR(ctx, AC97_CONFIG, ctx->cfg);
0272
0273     platform_set_drvdata(pdev, ctx);
0274
0275     ret = snd_soc_set_ac97_ops(&ac97c_bus_ops);
0276     if (ret)
0277         return ret;
0278
0279     ret = snd_soc_register_component(&pdev->dev, &au1xac97c_component,
0280                      &au1xac97c_dai_driver, 1);
0281     if (ret)
0282         return ret;
0283
0284     ac97c_workdata = ctx;
0285     return 0;
0286 }
0287
0288 static int au1xac97c_drvremove(struct platform_device *pdev)
0289 {
0290     struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
0291
0292     snd_soc_unregister_component(&pdev->dev);
0293
0294     WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
0295
0296     ac97c_workdata = NULL;  /* MDEV */
0297
0298     return 0;
0299 }
0300
0301 #ifdef CONFIG_PM
0302 static int au1xac97c_drvsuspend(struct device *dev)
0303 {
0304     struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
0305
0306     WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
0307
0308     return 0;
0309 }
0310
0311 static int au1xac97c_drvresume(struct device *dev)
0312 {
0313     struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
0314
0315     WR(ctx, AC97_ENABLE, EN_D | EN_CE);
0316     WR(ctx, AC97_ENABLE, EN_CE);
0317     WR(ctx, AC97_CONFIG, ctx->cfg);
0318
0319     return 0;
0320 }
0321
0322 static const struct dev_pm_ops au1xpscac97_pmops = {
0323     .suspend    = au1xac97c_drvsuspend,
0324     .resume     = au1xac97c_drvresume,
0325 };
0326
0327 #define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
0328
0329 #else
0330
0331 #define AU1XPSCAC97_PMOPS NULL
0332
0333 #endif
0334
0335 static struct platform_driver au1xac97c_driver = {
0336     .driver = {
0337         .name   = "alchemy-ac97c",
0338         .pm = AU1XPSCAC97_PMOPS,
0339     },
0340     .probe      = au1xac97c_drvprobe,
0341     .remove     = au1xac97c_drvremove,
0342 };
0343
0344 module_platform_driver(au1xac97c_driver);
0345
0346 MODULE_LICENSE("GPL");
0347 MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
0348 MODULE_AUTHOR("Manuel Lauss");